TW531698B - Rapid and abnormal power shutdown prevention algorithm for flash memory - Google Patents

Abstract

A flash memory algorithm, especially a flash memory algorithm and its control system can rapidly set up table and prevent abnormal power shutdown from inducing data disorder, is provided. The main way is to store logic block address and connection relation mapping table of entity block address values corresponding to the logic block in a data entity block page of the memory. The address and table are protected by a set of ECC data. When the computer turns on normally, the control device directly loads the mapping table data into a register in the control device to control device access. The setup of its mapping table is instant and rapid. It is not necessary to rapidly construct the mapping table through scanning procedure. The turn-on time and operation procedure are saved. If the wrong mapping table is resulted from abnormal system operation, the mapping table will be back to the previous record to recover the system connection.

Description

V. Description of the invention (1) Description of the invention: It has im about a kind of flash memory calculation *, especially-a kind of flash memory, scapular method and its control system that are derived from erroneous data that can be prevented from abnormal power failure. . The rise of the product f Ϊf said thousands of miles ’is subject to faster and faster CPU speed and 1 Α flash memory. Among various data storage devices, it is widely used due to its fast use and easy access to data.

Symptom S. 5 shown in the picture is the structure of a general data storage system. I card M a data storage device (such as Mart Media memory system Aem〇ry StlCk memory cards and other flash memory) 1 19 main system The control device 20 is connected to the host computer 29 (of course, the dm is built into the subsystem of the host computer 29). The control unit has a microprocessor 25, which can be controlled by a host computer that complies with PCMCIA, She 2, MMC, SD, ComPaCt FUsh or its combined specification Xie Ge 1 machine interface controller 24 is interconnected with the host computer 29, and the micro-location writes material #, and the # end can be passed through a storage control logic circuit 2 6 to connect to that,

22: 2 2 1 1 ~ 1 9; the microprocessor 25 can also be connected to a temporary storage area controller μ sub-area controller 2 2 can control the computer host 2 9 temporary storage information Λ storage area 21 for accessing data ( The first register 211, the second register 213, and the temporary benefit 219). In addition, an E (χ logic circuit 23 is connected to the German processor 25, the register controller 22, and the storage control logic circuit 26, respectively. It is controlled by the microprocessor 25 and gives the magnetic field of the data to be accessed. Corresponding wrong collar

531698 V. Description of the invention (2) Correct code ECC data. In addition, the microprocessor 25 can be connected to a Lookup Table 255, and the search list 2 55 can be used to record the logic: two (L. ~ Lm + 1) and the corresponding data storage f settings ": Block Block Address Data Value (PBA). Have n

Each logical block address contains a record. Please refer to Figure 1B, search list 25 5 used for the credit card return machine access memory (RAM), mainly in characters (thanks D) ^ The order is taken as it stands, and it is divided into a plurality of character addresses (logical block addresses). L 1 The data values m A, / Μ ·· / Λ + ι which are relative to the physical block address of the memory. , Bm, ...). The flash memory 11 is mainly divided into three areas: "Γ real: sub" and f is divided into a plurality of physical block addresses VB n two: the physical block addresses Bfl ~ Bn are included in the physical block There are multiple block pages, and each 0 Uatan) TSfrr is opened in the white minimum storage, and § is in a recording area on the host side = :: = (二 I,;-can be added after the paging-scores Qi (Correspond to the error of the knife shell) Correct the code block ECC (; ln.g; ode) ^ ^ ^ t 1 2 3 1, Lm + 1) logical block address block LBA, where: = column and i Jiyi The logic of the LBA of the body 11 is the corresponding relation, the logic of the data Data ^ stored in the body block β0 of the σ5 memory.

= G ί: L refers to the magnetic field L2 in Λsou, 255, so its LBA will be stored without disappearing even after the power is off), that is, the login point is B. (This information is missing), as shown by the solid double arrow, and so on, as described in Section 531698 V. Invention Description (3) When the system is turned on, the PBA block of the search list 255 does not exist: The processor 25 will scan Each physical block of flash memory 11 ~ 19 has a value of micro-location address data lba, and the relatively cheap key is filled into the physical block address column PBA of the search list 255 according to the logical block address. In order to build a list of "Li Li ... Zheng Zhishen 2 5 5". However, it is not only inconvenient and wastes time to establish such a search method. "Also because of the structure of flash memory 11, its erasing or stocking is based on block B. As a unit, when there is a physical block modification and change (such as), the block 4 to be changed must be changed. The originally stored data "Seven: first transferred to a clean physical block (such as a2B) that is available but has not yet stored data, and the logical address is registered in the LBA block after this physical block Bm + i L1, and then erase the data Data2 in the block A to be changed-dry $ J records are not used. However, if a clean block (such as') has completed the asset transfer and filled in the logical address data value procedure, but wants to change the block 6 before the erasing action has been completed, an error such as a sudden power failure or a crash occurs. ^ Machine = 丄 When restarting and the microprocessor 25 scans the logical address data program of the block again, two things may happen: = 丄 and B㈣ both register the logical block address value u and point to the same One = 255 addresses of the brother list (as shown by the dashed double-headed arrow; if this is the case, then it is not only easy to cause data to be wrongly connected, 纟 σ, or even damage the data. Construction; Γ = Another update depends on flashing Memory mapping table and its construction method, which can not only establish the mapping directly and quickly when the system is powered on, but also prevent various unexpected operating conditions such as sudden or power failure.

531698 V. Description of the invention (4) Guarantee of data link The present invention intends to act on the good ideas of the information system. It has undergone countless trials and prevented inconsistencies.爰 Yes' The operation efficiency of the present invention uses a physical area to connect to the block processor and use scanning and scanning, so the operation efficiency of the present invention can be saved under the operation of the body block paging operation to save the operation efficiency of the present invention. One 0 The accuracy of the flash memory for another purpose of the present invention has long been a difficult point for users to eagerly hope and solve. The inventor has been engaged in product research, development, and sales for many years. The practical experience is to consider and improve his personal expertise. After various designs and discussions, and after A-like and improvement, he finally created a flash memory algorithm and control system of the present invention with fast operation effects. The main purpose is to provide a fast and prevent improper flash memory performance algorithm and its control system. It is mainly used to store the mapping table data in paging blocks, and it is reproduced in a temporary register when the system is turned on. Fast switching without the need for micro-programming programs to perform logical address data on each physical block of memory can not only simplify the operation time of the microprocessor, but also Significantly. The secondary purpose is to provide a fast and prevent improper decision-making algorithm and its control system. The memory records the mapping table data in the memory, thereby avoiding the abnormal connection of data due to abnormalities. Sorry. An object is to provide a fast and prevent improper flash memory performance algorithm and its control system. The mapping table is protected by ECC data to improve the accuracy of its data. It is to provide a fast and prevent improper performance algorithm and Its control system, which can

531698 V. Description of the invention (5): The number of memory blocks is divided into a plurality of segment areas according to the temporary register or the block paging record, and each segment area has a corresponding one; Relationship, when there is a change in block data, it will only affect $ to the related mapping table data, so it can effectively reduce the mapping table's "second time" and can effectively reduce the occurrence of data error link conditions. Another object of the present invention is to provide a flash memory algorithm and a control system with fast and preventive effects, which can divide the two physical blocks into a plurality of partitions, so that the mapping table The size is reduced and a magnetic area (256 Words) is saved, so that this mapping table can also be stored in flash memory as secondary protection data, so the memory capacity of the registration block and address data can be greatly saved. , And can be applied to the storage system of linked records. The detailed description of the structure, characteristics, and description of the present invention by the review committee of the gate is as follows: Legend of the right yoke and = read :: A :, the flash memory storage system of the present invention is not a map) The flash memory 3 and 39 are mainly controlled by a control device 40 = 1: the brain host 49 is connected (of course, the control device Λ is built in the = subsystem of the thin host 49), the microprocessor 45 , Which can be-in accordance with pcmcu, ide, at broad: C, SD, Compact Flash or a combination thereof; = machine 49 is connected to each other, and the microprocessor 45 = can be controlled by a storage logic logic ^ ...... The processor 45 can also be connected to the controller J to connect a temporary storage area controller 42.

ilM Page 8 531698 V. Description of the invention (6)] = Two controls two = To: fetch data temporarily stored in-Zi M, temporary storage number control circuit 43 is connected to the microprocessor processor 45: fJ To control the logic circuit 46, it is controlled by micro-ECC data. The error correction code corresponding to the area M is used to store the records of each Shijibei body i # "The part of the temporary register 419 can be used for the mapping of the PBA 2 9 (: Shell body block related entity block address data The value ^ T'4i9 (mapping table). An ancient shore = ^ 2 map, in the embodiment of the present invention, 'it records the relative = address data value PBA mapping table 419 is registered in the second control unit, the temporary register 419 , For the register page 419 or the entity 'ghost u0) knife page (1) called 6) memory storage capacity of 256 bytes or 512 bytes (also 疋 128 or 256 characters), each digit w of the mapping table 419 .1, ... u contains the address of the corresponding-corresponding block b., Bι, two, so a mapping table 419 can correspond to 128 or less than 256 memory physical blocks (B.), Therefore, the total number of memory physical blocks can be timely divided into multiple partition families (SegQ ~ Segn). The number of blocks (Biock) contained in each segmented segment will be limited to 256 (or (Within 128) 'Of course, each segment has a special reserved block that specifically records the mapping update (as indicated by * in 2b or 2C). Each segmentation segment has a special reserved block corresponding to Mapping update (the initial value of this mapping block is created during system initialization) to establish the data mapping relationship.

Page 9 531698 V. Description of the invention (7) When accessing the case data, the LBA value transmitted by the microprocessor 45 m of the control device 40 and the machine 49 is divided by the physical error value contained in the partition. Divide by the number of sectors contained in the block to obtain the mapping table in the desired ghost segment 'and map this partition mapping table to the latest update of the special reserved block :: = Plng UPdate): It is stored in the mapping register 419, so as to facilitate the transfer of the physical block address of Li Yier ... every minute: block: = = appingupdate) special reserved block to store the maximum i = f mapping relationship, when there are changes in the block mapping information is updated only Ϊ ^ due to update the latest points = Xi (mapping update) special reserved blocks of lower 2 t modifier can effectively reduce the operation time of the entire map, and can effectively reduce poverty material error link The situation happened. It is known that the shooting table 419 itself is a storable data, so t KH new rpping update) in the physical area of the special reserved block "W", and this part of the page 311 is marked with a special mark "several Partition pages MT., MT1, MT2, ....., MT "JU Ercut is a complex material. See Figure 2 °. When the registration information in the mapping table 419 — ate) is special; leaving P Er to make it poor. Eight storages—When the map is updated, it is stored in +1, and each time new registration data is added

Erase hl · ηύ., Shots will be written to non-paged pages, until they are full, they will be renewed, and mapping update (Mapping update) special reserved blocks will be updated from the page, page 8 of the invention description (8), as a memory 41 g The data can be reprinted immediately when the large computer is turned on. This invention is temporarily scanned by the host computer 49. This invention does not require the data to be re-established as in the conventional storage system. Search for the logical address of the & ) It is also possible to use the big program s # 二, so not only can the computer host 49 make it of course, but also the time of constructing the search list by i; ::.

The focus of f and p in the physical block page is that the mapping table data can be stored in a mapping table memory ^ f will be directly and quickly captured when the system is turned on, please come to Q (or read ) Wrestling: Catch: The flash memory of the present invention is not being written. Its main steps include: η action-private picture, as shown in step 30 1 'The computer host system is in standby state; system 4 After setting it to boot or supply, the whole step: 3 02, waiting for the host to issue a write instruction; the computer host needs access to the case data, and the micro-designated lba data specified by the control device is processed to obtain the = The mapping table data is reproduced from the paging page of a physical block in :: 304. The microprocessor finds the memory physical block corresponding to the file data taken by the e-man through the partition mapping table data, and writes the master to write The data is transferred to the Sector Buffer (Sector Register) in step 305. The written page in the old block is compared with the bit that will be written to it.

The address detects whether the write instruction is in the block and does not need to update the mapping: ',, overwrite status, if not, write directly to the old area, step 305; the mapping relationship and return to the standby state; if so, go to step 30 6, It means there is a Xu write, first write the new data into the steam ——: a page of data in the product block will be covered by step 307, and the clean block previously reserved by the system will be moved into this clean block;: stored in the old block Step 308 of the data that has not been changed, erase all the data in the clean memory that was originally retained ^^ to become another system net block; the block 'becomes a dry step that will be used next time. 309, change the mapping table with Bu, + Ying, in order to hope that the logical address data value of the ^ Muguan block in relative step 31, will temporarily store the correct connection relationship between the two; Kao Festival; Mapping resources (, P: ng update) special reserved blocks, middle-to-lower one, and mapping update. The control device is a page when the computer is turned on, as the last, please refer to the information in the mapping table. The operation flow chart at the time of the table; as shown in the figure * The month system is constructing a mapping Step 4 0 1

The address of the paging mapping table that was entered; when the missing '^ conversion has been obtained, it must be found by: special mark, mapping = let ^ y in the example, from a particular F paging mapping table that is not mapped; The & block reads the specified =, 4, 3. If the coffee in the mapping table is wrong, the work of the two people has experienced abnormal behavior, then it is not on the table-W ^ ^ does not § Implementation; j V. Description of the invention (10) 404; if not, it means that all positive steps are performed 404, which means that abnormal operation = double then step 40 is performed; the coping relationship of the mapping table, as long as you reconnect / I must, Go back to the previous update) Mapping update in the special reserved block; 4 1 —Map paging to the memory step, 405, continue to perform system actions. Flash memory calculation is derived from power failure. Therefore, the present invention Those who are effective should comply with the patent application, pray for examples, and make clear the changes and amendments of the patent application: as mentioned, when the present invention is related to f, especially a type that can be quickly built and prevented = fast Flash memory algorithm is progressive and available for industry: use 4h s. Ja ° month Undoubtedly, it ’s a pity for Ji to propose an invention based on an early grant of a patent by law. Non-use :: 1 catty is only the scope of the present invention-a better practice. For anyone who steals according to this issue, the shape, structure, characteristics, and spirit of the two should be included in the scope of the patent application of the present invention. Drawing number comparison description: 20 control device 2 11 first register 219th N temporary storage Device 23 ECC logic circuit 25 microprocessor 29 host computer 11 ~ 19 flash memory 21 data temporary storage area 213 second temporary storage device 22 temporary storage area controller 24 host interface controller 26 storage control logic circuit 531698 5. Invention Explanation (π) 255 Mapping table 31 ~ 39 Flash memory 311 Partial paging 40 Control device 41 Data temporary storage area 411 First temporary storage device 413 Second temporary storage device 419 Mapping table 42 temporary storage area controller 43 ECC logic circuit 44 Host interface controller 45 Microprocessor 46 Storage control logic 49 Computer host

Page 14 531698 Brief description of the diagram Figure 1 A: Schematic diagram of the general flash memory storage system; Figure 1 B: Schematic diagram of the mapping table of conventional flash memory; Figure 2 A: The present invention Schematic diagram of the structure of the flash memory storage system; Figure 2B: a schematic diagram of the mapping table structure of the flash memory of the present invention; Figure 2C: the structure of the partial page of the flash memory physical block of the present invention is not intended, FIG. 3 is a flowchart of operations of the flash memory of the present invention when accessing data; and FIG. 4 is a flowchart of operations of the present invention when constructing a mapping table.

Claims (1)

531698 6. Scope of patent application A flash memory control system ~ The device is connected to a computer host and at least-the fast system is controlled by a plurality of ^ A memory in the control device, which is used to load The logical block address and the sub-register can be mapped to 2 data values in the mapping table data. This mapping table block address memory is part of the physical block. 、 // Can be stored in a flash 3 The number of physical blocks in the flash memory as described in item i of the patent application scope is two for temporary storage, "/, and the flash can be segmented into multiple Zoning ethnic groups. The storage capacity of the port is described in item 2: control system ... each.廿 T is stored in the corresponding page of the physical block of memory. 4 6 ′ The data control system as described in Table 1 ^^ / ^^ item 1 is used, among which- Ziguli can choose between 256 bytes and 512 bytes, as shown in the table above, and the control system described above is ^ ^ 2 5 6 of the order, the number of memory blocks can be selected 1 2 8 and the control system described in item 1 of the table above, wherein the number of memory areas of the mapping ^ characters (W0rd) can be registered and mapped to a corresponding registration #specified in item 1 The control system, wherein the register of the recordable mapping table may be a data storage device. 7 VI. Scope of patent application 8 If it is less than item 1 of the scope of patent application ^ There is a memory and return control system for mapping table data, which is stored in it. . ^ _Only a block is provided with a special marker 9 ;; a flash memory is stored in the algorithm body > It is mainly in a flash memory, the corresponding logical block = address data value and At this time, by-control device = shooting table "bucket, when the system is turned on 10 is contained in one of the control devices temporarily ^ = this mapping table data is directly transferred to the patent application scope item 9 steps: t times of different methods, yet When including the data stored in the following step blocks, this will be the first to be changed: the data is reprinted in-all available data blocks that are not stored yet, and then the block to be changed is temporarily connected Save and write the two spears, and the relevant entity block address data will be stored in the mapping of the W ~ f state. The 11 mapping table data will be stored in the memory of the other? Later, this change will be applied as soon as possible 4 丨 ^ , In the other consistent block of the dagger body. The algorithm described in item 10 of the step has been included, and it also includes the following when the data in the block to be modified has been erased, When the situation occurs and the device is restarted, the control device will: The map data will be reproduced in the scope of patenting algorithms staging 12 of the first nine, also include the following on page 17 531 698 The reason for the storage is 13 14 1516 Whether it is the same as the application Steps: It is recorded when the extension is stored. If the application memory is segmented as in the application area, one of the applications in the application memory area has the patent patent memory stored on the page, and the entity of the patent patent can be turned into a plurality of patent patent blocks. Block 0 shoots the ECC data of the physical block of the table data to identify the normal operation. ° The algorithm described in item 9 also includes one of the physical block sections of the mapping table data memory of the following related block addresses of each physical block, and the address includes a special mark to facilitate the system Search the page mapping table data and reproduce it in the algorithm described in Item 9 of the register, where the number of flash memory blocks can be divided into groups for the storage capacity of the register. The algorithm described in item 13 above, wherein each segment I has a corresponding partition mapping table. The algorithm described in item 9 above, wherein the number of mapping tables (words) is recordable and maps a corresponding record 1 7 · As in the algorithm described in item 9 of the scope of patent application, one of the mapping tables can The number of mapped memory physical blocks is one of 28 and 256 ^. 18 · The algorithm described in item 9 of the scope of patent application, in which the modified mapping table data can also be directly stored in a fixed mapping table data physical block page. '