TWI557559B - Method for writing into and reading from bad pages of a flash memory - Google Patents

Description

Method of accessing data by using bad pages of flash memory

The present invention relates to a data access method for flash memory, and more particularly to a method for accessing data using a bad page of a flash memory.

With the application of cloud technology and big data materials, the performance requirements for storage systems are increasing. Using NAND flash memory as the storage medium and various controllers for various operations, the solid state disk (SSD) has gradually replaced the traditional hard disk. . Obviously, in the basic design architecture of solid state drives, control chips and NAND flash memory are important factors affecting the performance and stability of solid state drives.

The conventional control chip, its functions include: input/output command (I/O Command), data management (Data Shaping), wear leveling technology (Wear Leveling), space recovery (Garbage Collection) processing power, and power supply, The management capabilities of the cache (Cache) and Bad Block. Of particular importance are the support methods for TRIM commands and the Error Checking and Correcting (ECC), which is more important as the size of NAND flash memory is smaller. All of the above must rely on the control chip to operate to optimize the performance and stability of the solid state hard disk.

In NAND flash memory, the smallest unit that stores data is called a memory cell. The memory cell is composed of a transistor, which is made of a wafer. The organization of the transistor inside the wafer is basically a page, a block, and a data recording matrix (Plane). Each row of "pages" is grouped into a "block" by sorting rows and columns, and each of the "blocks" constitutes a "data record matrix". However, SSDs have a special unit limit on reading and writing data. The smallest unit that can be read or written is the "page". When there is already data in a "page", the new data cannot be directly written. The data must be cleared before writing. The action of clearing data is called garbage collection, and the solid state hard disk is a "block" as the smallest unit for clearing data. Therefore, the minimum unit for reading and writing and erasing data on a solid state drive is not equal.

As the size of NAND flash memory is getting smaller and smaller, the programming/Erase Cycle (P/E Cycle) is becoming less and less, making the service life of NAND flash memory shorter and shorter. Therefore, the life of NAND flash memory will become more and more important. In general, control chips must use more advanced techniques and algorithms to extend the life of NAND flash memory.

At present, the most important methods for improving the lifetime of NAND flash memory are:

First, use Wear Leveling to average use each block in the flash memory to avoid some "specific" storage blocks from forming bad blocks due to overuse. .

Second, use Data Deduplication or Data Compression to reduce the amount of data written.

Third, Downgraded Flash Memory: In NAND flash memory, in order to indicate different data states, a single cell can use multiple bits to indicate multiple states. Taking a multi-level cell (MLC) as an example, MLC stores two bits in one memory cell to represent four states, but with the wear and tear of MLC, it will not be able to distinguish correctly. State. However, if the two states can still be distinguished, the MLC can be used as a single level cell (SLC). Another method of secondary flash memory is to manage the corrupted memory blocks in the NAND flash memory and remap them to the normal memory blocks (Block) so that one has The NAND flash memory chip of the damaged block can still be used normally.

In summary, the prior art mostly focuses on dispersing wear evenly, reducing the amount of data written, or managing damaged blocks, but does not consider how to reuse the damaged blocks.

It is an object of the present invention to provide a method for accessing data using a bad page of a flash memory to extend the life of the flash memory.

In order to achieve the above object, the present invention provides a method for accessing data by using a bad page of a flash memory, the method comprising a writing program and a reading program for initializing a page size The data is written into a flash memory having two bad pages and can be read. In the following description, the two bad pages are respectively referred to as a first bad page and a second bad page, both of which have plural numbers. Error bit.

The writing process includes the following basic steps: using a data separator to split the original data into a first sub-data and a second sub-data, and copying the first sub-data and the second sub-data separately. Forming two first sub-data and two second sub-data; using a data masker to convert one of the two first sub-data and one of the two second sub-data into one Two dummy data, and forming a first data group and a second data group, wherein the first data group includes two of the first sub-data and the other one of the two virtual materials, the first The second data set includes two of the second sub-data and the other of the two virtual data; generating, by the encoder, a first parity correction code according to the first data set, and generating according to the second data set a second parity correction code; and combining the two first sub-data and the first parity correction code into the first bad page, and combining the two second sub-data and the second parity correction code into the second bad page.

The reading program comprises the following basic steps: dividing the physical storage space on the first bad page into a first segment and a second segment; the data masker converts the data content stored in the first segment into virtual data; a decoder corrects the data content stored in the second segment according to the first parity correction code, and restores the data content stored in the second segment to the first sub-data; averages the physical storage space on the second bad page Divided into a third segment and a fourth segment; the data masker converts the data content stored in the third segment into virtual data; and uses the decoder to correct the data content stored in the fourth segment according to the second parity correction code, The data content stored in the fourth segment is restored to the second sub-data; and the first sub-data and the second sub-data obtained by the reduction are combined into the original data by using a data assembler.

In an embodiment, if the decoder cannot restore the data stored in the second segment to the first sub-data according to the first parity correction code, the reading process further includes the following steps: the data masker determines the first The number of such error bits in the second segment is greater than the number of the wrong bits in the first segment, and the data selected in the second segment is reselected to be converted into virtual data, and the data stored in the first segment is retained. And the decoder corrects the data content stored in the first segment according to the first parity correction code, and restores the data content stored in the first segment to the first sub-data.

In an embodiment, if the decoder cannot restore the data stored in the fourth segment to the second sub-data according to the second parity correction code, the reading process further includes the following steps: the data masker determines the fourth The number of such error bits in the segment is greater than the number of the wrong bits in the third segment, and then re-selecting the data stored in the fourth segment into virtual data, while retaining the data content stored in the third segment And the decoder corrects the data content stored in the third segment according to the second parity correction code, and restores the data content stored in the third segment to the second sub-data.

In one embodiment, the above method of accessing data using a bad page of a flash memory is applied to a flash memory controller. The flash memory controller is electrically connected to the flash memory and has a flash translation layer (FTL), wherein if the original data needs to be split and stored in two bad pages, the original The data will be transferred to the data splitter via the flash memory conversion layer. The flash memory controller is included in a data processing system including a file system, a flash memory controller, a memory technology device (MTD), and a flash memory. The host generates the original data, and transmits the original data to the flash memory conversion layer, and the flash memory conversion layer inputs the original data into the data separator, and the data set of the "two first sub-data" output by the data separator And the data set of "two second sub-data" is finally transmitted to the memory technology device, and then written into the flash memory.

In one embodiment, the first bad page and the second bad page are located in adjacent storage mats of the same die in the flash memory, and the first bad page and the second bad page Have the same offset (Offset) on each of the storage matrices. In this way, a parallel command can be provided to the foregoing memory technology device, and two copies of the first sub-data and the first parity correction code are combined into the first bad page, and the second sub-data and the second The two parity correction codes are combined and written into the second bad page.

In an embodiment, the method for accessing data by using a bad page of the flash memory further includes: providing a bad page recorder to record physical addresses of the first bad page and the second bad page.

In an embodiment, the first bad page has a first spare area and the second bad page has a second spare area. In the above writing process, the first parity correction code is written to the first spare area, and the second parity correction code is written to the second spare area.

The biggest difference between the method of the present invention and the prior art is that the method of the present invention can recover and reuse the damaged "page" space in the NAND flash memory chip, and the data can be stored through the management layer of the present invention. In these originally damaged page spaces, and later, the original data can be correctly read and restored, and the life of the NAND flash memory chip is extended by the bad page reuse.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. The directional terms mentioned in the following embodiments, such as upper, lower, left, right, front or rear, etc., are only used to refer to the directions of the accompanying drawings. Therefore, the directional terms are used for illustration only and are not intended to limit the invention.

The method for accessing data by using a bad page of a flash memory disclosed in the present invention can be applied to a flash memory controller of a data processing system. FIG. 1 is a schematic diagram of an overall architecture of a data processing system 100 according to an embodiment. The data processing system 100 includes a host 110, a flash memory controller 120, a memory technology device (MTD) 130, and a flash memory 140. The host device 110 is electrically connected to the flash memory controller 120; and the memory technology device 130 is electrically connected between the flash memory controller 120 and the flash memory 140. The host 110 has an operating system 111 and a file system 112. The plurality of applications 200a, 200b...200n generate an original material through the operation of the operating system 111 and the file system 112. The original data is transferred from the host 110 to the flash memory controller 120 via an interface 150, and then written into the flash memory 140 by the memory technology device 130. The flash memory 140 of this embodiment is a NAND flash memory chip. The smallest hardware unit for storing data is a memory cell, and the memory cell is composed of a transistor. The crystal is made of a wafer. The organization of the transistor inside the wafer is divided into a page, a block, and a data record matrix. Each of the "pages" is grouped into a "block", and each of the "blocks" constitutes a "data record matrix".

In the embodiment of the present invention, the flash memory controller 120 has a flash translation layer (FTL) and an encoder/decoder 122 (ECC Encoder/) that performs error checking and correction mechanisms. In addition to Decoder, a management layer of 123 is added.

The flash memory conversion layer 121 includes a logical/physical address translation module 1211 (Logical/Physical Address Translation), a space collection module 1212 (Garbage Collection), and a wear leveling module 1213 (Wear Leveling).

The management layer 123 is connected between the flash memory conversion layer 121, the error checking and correcting mechanism of the encoder/decoder 122 and the memory technology device 130, and is used to execute a write program to convert a page size original. The data is written into a flash memory 140 having two bad pages, and after writing, a corresponding reading program can be provided. In this way, the controller manufacturer does not need to modify the original architecture of the flash memory controller 120 to achieve the purpose of accessing the data by using the bad pages of the flash memory 140.

The management layer 123 consists of four main components: a bad page recorder 1231 (Bad Page Recorder), a data separator 1232 (Data Separator), a data masker 1233 (Data Masker), and a data combiner 1234 (Data Assembler). The composition is as follows:

(1) Bad Page Recorder 1231: Used to record the physical address of the currently damaged "page".

(2) Data separator 1232: In the management layer 123, it is necessary to split the data of one page size into two halves, and store them separately on the two damaged "pages", so the data separator 1232 is required to be responsible for the data. Split and store. In this embodiment, the original data split by the data separator 1232 is transmitted through the flash memory conversion layer 121, and the split sub-data is transmitted to the memory technology device 130, and then written. Flash memory 140.

(3) The data masker 1233: the two first sub-data and the two second sub-data after the original data are separated by the data separator 1232, and the sub-data of each half-page capacity is replaced by the data shutter 1233. After the dummy data (Dummy Data), and forming a first data group and a second data group, wherein the first data group includes the first sub-data plus the virtual data, and the second data group includes the second sub-data plus the virtual data The data is then subjected to error checking and ECC encoding by the ECC encoder/decoder 122 to generate two error correction codes corresponding to the first data group and the second data group. In this way, a two-page error correction code can be used for the original data of one page size, thereby redefining its parity correction code (Parity).

(4) Data combiner 1234: Since the original data is rearranged in two "page" spaces by using the data separator 1232 before writing the data, the original data needs to be restored through the data combiner 1234 to be read.

Referring to FIG. 2 and FIG. 3, the inventive concept of the present embodiment is explained as follows: if the error checking and correction mechanism (ECC) correction capability is n bits per page (bits/page), then in a page space When the number of Error Bits exceeds n, this page space can no longer be used to store data correctly. Such a page space is referred to as a "Bad Page" in this embodiment. If the management layer 123 in this embodiment is used, as long as the number of error bits in the bad page does not exceed 2n, any two bad pages can be selected by the management layer 123 to store the original data of one page size. In principle, assuming that the number of error bits of a bad page is 2n, if the physical storage space of the bad page is equally divided into two segments, one of the segments can always be found, and the number of error bits is Between 0~n.

For further explanation, please refer to FIG. 2. Page P _A has 4 error bits. If the error checking and correction mechanism (ECC) correction capability is 2 bits per page, the page P _A cannot be corrected, so page P _A will It is considered a bad page. At this time, the management layer 123 divides the physical storage space of the bad page P _A into a first segment S _1A and a second segment S _2A . Conceptually, according to the number of error bits included in each segment S _1A or S _2A , respectively, it is called Strong Segment and Weak Segment, and the number of error bits in the strong segment is less than or equal to Weak section. The best case is that the error bits of the bad page P _A are concentrated in the weak segment, and the strong segment has no occurrence of the error bit. For example, the strong segment of the bad page P _A is the second segment S _2A . The worst case is that all the error bits are evenly distributed in two segments, such as a third segment S _1B and a fourth segment S _{2B of the} bad page P _B . Despite the worst case, it is still possible to use ECC to correct the two segments S _1B and/or S _{1B of the} bad page P _B .

As shown in FIG. 3, in one embodiment, two bad pages P _A and P _B may be combined into one bad page group P _set (Bad-Page Set) to store a page size original data D ₀ . Through the above process, half of the size of the original data D ₀ can be stored in each of the bad pages P _A or P _B , such as a first sub-data D _A or a second sub-data D _B .

About 123 management in the implementation details, such as the sub-data D _A and D _B P _A respective presence of the bad page P _B and the data structure, the original data D ₀ and writes bad page P _B P _A, and The entire flow of reading the original data D ₀ from the bad pages P _A and P _B is described in detail as follows:

4 shows the process of writing the original data D ₀ to the bad page group P _set of one page size using the management layer 123. The writing process is mainly performed by the data separator 1232 and the data masker 1233. After the original data D ₀ is transmitted to the management layer 123 through the flash memory conversion layer 121, the management layer 123 first uses the data separator 1232 to divide the content and size of the original data D ₀ into two halves, as shown in FIG. The first sub-data D _A and the second sub-data D _B , and the sub-data D _A and the sub-data D _{B are} separately copied to form a two-page capacity data D _AA and D _BB , and each page of data D _AA ( Or D _BB ) includes two copies of sub-data D _A (or two sub-data D _B ). Thus, when the two pages of data D _AA and D _BB are written to the bad page group P _set , the sub-data D _A and D _B are respectively stored in the two bad pages P _A and P _B of the bad page group P _set . And the two sub-data D _A respectively have a segment S _1A (or S _2A ) of the bad page P _A and two sub-data D _B respectively exist in one segment S _1B (or S _2B ) of the bad page P _B , which can be guaranteed One of D _A (or D _B ) in D _AA (or D _BB ) may be in the strong segment of bad page P _A (or P _B ). Next, the data masker 1233 is used to replace one of the sub-data D _A of the first page data D _AA after the copy processing with the virtual material D _u , and one of the sub-data D _{B of the} second page data D _BB . Substituting the virtual data D _u to form two data sets D _AM1 and D _BM1 such as "sub-data D _A + virtual data D _u " and "sub-data D _B + virtual data D _u ". Then, the two data sets D _AM1 and D _{BM1 are} respectively ECC-encoded to redefine a first parity correction code P _CA (Parity) and a second parity correction code P _CB . The correction code P _{CA is} used to maintain the half-page size sub-data D _A ; the correction code P _{CB is} used to maintain the half-page size sub-data D _B . Finally, the two sub-data D _A and the correction code P _CA in the first page data D _AA are merged into the bad page P _A ; and the two sub-data D _B in the second page data D _BB are combined with the correction code P _CB Go to the bad page P _B and complete the writing process. In practice, since each segment S _1A , S _2A , S _1B or S _{2B of} each bad page P _A or P _B may have an erroneous bit, there is actually a data content and sub-section in each segment S _1A and S _2A . The data D _A may be missing, and the codes D _1A and D _{2A are} used. The data "D _1A + D _2A + P _CA " stored in the bad page P _A is represented by D _AW . Similarly, the data "D _1B + D _2B + P _CB " stored in the bad page P _B is represented by D _BW .

FIG. 5 shows a process of using the management layer 123 to read the data D _AW and D _BW previously stored in the bad page group P _set and restore it to a page size original data D ₀ . The reading program is mainly by the data combiner. 1234 and the data masker 1233 are cooperatively completed. The basic steps of reading the program are described below with reference to FIG. 2 as follows:

The data masker 1233 selects one of the first page S _1A or the second segment S _{1B of} one of the bad pages P _A to be shielded, such as P _AM as shown in FIG. 2 , for example, a segment to be masked The bits in S _1A are filled with 0, that is, the data content D _1A stored in the first segment S _1A is converted into the virtual data D _u by the data masker 1233; and the mask is processed by the ECC encoder/decoder 122. information group D _AM2, which comprises a first correction code parity P _CA, virtual information stored in the second section D _U S _2A and the contents of the information D _2A, by correcting the stored data in the second segment S _2A content D _{2A is} restored to the first sub-data D _A .

Similarly, the data content D _1B stored in the third segment S _1B is converted into the virtual material D _u by the data masker 1233. Using the ECC encoder/decoder 122, according to the masked processed data set D _BM2 , including the second _parity correction code P _CB , the virtual data _Du and the data content stored in the fourth segment S _2B , the correction is performed and stored in the first The data content D _{2B of the} four-segment S _2B is restored to the second sub-data D _B . Finally, the data subcombiner 1234 is used to combine the restored first sub-data D _A and the second sub-data D _B into the original data D ₀ and transmitted back to the flash memory conversion layer 121 to be transmitted to the host 110. Complete the reading process.

As shown in FIG. 5, in an embodiment, if the ECC encoder/decoder 122 fails to restore the data content D _2A stored in the second segment S _2A to the first sub-data D according to the first parity correction code P _CA . _A , the data masker 1233 determines that the second segment S _2A is a weak segment, and reselects to convert the data content D _2A stored in the second segment S _2A into the virtual data D _u and keeps the first segment S _1A 's data content D _1A . The ECC encoder/decoder 122 then corrects the data content D _1A stored in the first segment S _1A according to the first parity correction code P _CA , and restores the data content D _1A stored in the first segment S _1A to The first sub-data D _A .

Similarly, if the ECC encoder/decoder 122 cannot restore the data content D _2B stored in the fourth segment S _2B to the second sub-data D _B according to the second parity correction code P _CB , the data masker 1233 will determine the first _2B is a weak four S segment, and re-select S data stored in the fourth paragraph D _{2B 2B} content into virtual data D _u, and stored in the third paragraph of S reserved content material _1B, D _1B. The ECC encoder/decoder 122 then corrects the data content D _1B stored in the third segment S _1B according to the second parity correction code P _CB , and restores the data content D _1B stored in the third segment S _1B to the first The second sub-data D _B .

Referring again to FIG. 3, in an embodiment, the management layer 123 may select two bad pages having the same displacement to form a bad page in two storage matrices adjacent to each other in the same die. Group P _set . As such, the management layer 123 can use the advanced parallel instructions to operate the two bad pages to ease the burden on the data processing system 100 and speed up the processing. In other words, the management layer 123 can provide a parallel instruction to the memory technology device 130, and combine the two first sub-data D _A and the first parity correction code P _CA into the first bad page P _A . The two second sub-data D _B and the second parity correction code are also combined and written into the second bad page P _B . In this way, the "parallel instruction" is used to simultaneously write data to two bad pages instead of sequentially writing data, so that the processing time at the time of writing can be reduced.

In an embodiment, the physical storage space of the first bad page P _A includes a first spare area S _aA (Spare Area), and the physical storage space of the second bad page P _B includes a second spare area S _aB . In the above writing procedure, the first parity correction code P _CA is written to the first spare area _{Sa a} and the second _parity correction code P _CB is written to the second spare area _SaB . Since the management layer 123 uses two bad pages P _A and P _{B to} store the original data D ₀ of one page size, there are two spare areas (Spare Area) for the original data D _{0 of} one page size. It can be used to store longer parity codes.

In the prior art, manufacturers usually use hardware to implement an ECC encoder/decoder in order to speed up the calculation of ECC. In a conventional practice, if it is necessary to generate a longer parity correction code, it is necessary to increase the output of the ECC encoder, and thus the hardware of the ECC encoder must be changed. However, the management layer 123 of the present invention can achieve the ECC enhanced effect without changing the hardware of the ECC. The key point is that instead of using a double-sized ECC parity correction code to maintain a page size data, the present invention maintains two half page size data using two normal size ECC parity correction codes. When ECC encoding the half-page size data, the management layer 123 fills the other half of the storage bits with dummy data, such as "0", to form a page size data to conform to the general ECC encoder. Input format. Since the data content of the half of the dummy data is a known value, the generated ECC parity correction code only needs to protect the data of half page size. As shown in Figure 4, this is the reason why data is masked to generate virtual data when ECC is encoded.

When the method of the present invention is applied to a platform of a solid state hard disk, it can cooperate with an operating environment such as Windows XP, Linux (Ubuntu 9), Multimedia, and Financial workload. The experimental results show that using the method of the present invention can increase the life of the solid state hard disk by 48.54%, 28.38%, 65.45% and 44.77%, respectively, under the above four working environments.

The biggest difference between the method of the present invention and the prior art is that the method of the present invention can recover and reuse the damaged "page" space in the NAND flash memory chip, and the data can be stored through the management layer of the present invention. In these originally damaged page spaces, and later, the original data can be correctly read and restored, and the life of the NAND flash memory chip is extended by the bad page reuse.

The present invention and the prior art are known to solve the problem of the lifetime of a flash memory, except that the present invention takes into account characteristics not noticed by the prior art, that is, reusing the already damaged one. Flash memory block. Through the software management layer designed by the present invention, bad pages can be converted into normal pages for continued use. The management layer of the present invention does not conflict with the prior art, so the present invention can be arbitrarily added to the prior art to further extend the life of the flash memory.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

100‧‧‧Data Processing System
110‧‧‧Host
111‧‧‧Operating system
112‧‧‧File System
120‧‧‧Flash Memory Controller
121‧‧‧Flash memory conversion layer
1211‧‧‧Logical/Physical Address Translation Module
1212‧‧‧ Space Recycling Module
1213‧‧‧ wear leveling module
122‧‧‧Encoder/decoder for performing error checking and correction mechanisms
123‧‧‧Management
1231‧‧‧Bad page recorder
1232‧‧‧ data separator
1233‧‧‧ data shutter
1234‧‧‧Data combiner
130‧‧‧Memory technology device
140‧‧‧Flash memory
200a, 200b...200n‧‧‧ plural applications
150‧‧‧ interface
P _A , P _B ‧‧ ‧ bad page
P _AM , P _BM ‧‧‧bad pages (masked)
Entity storage space segmentation in S _1A , S _2A ‧‧ ‧ bad page P _A
Entity storage space segmentation in S _1B , S _2B ‧‧ ‧ bad page P _B
S _aA ‧‧‧The spare area in the bad page P _A
Spare area in S _aB ‧‧‧Bad page P _B
P _set ‧‧‧bad page group
D ₀ ‧‧‧Source
D _A ‧‧‧ first sub-data
D _B ‧‧‧Second sub-data
D _AA , D _BB ‧‧‧Data written by the data separator in the program
D _u ‧‧‧virtual information
D _AM1 , D _BM1 ‧‧‧ Data set output by the data masker in the program
D _AM2 , D _BM2 ‧‧‧Reading the data set output by the data masker
P _CA ‧‧‧First parity correction code
P _CB ‧‧‧Second parity correction code
D _AW ‧‧‧Information actually stored on the bad page P _A
D _BW ‧‧‧Information actually stored on the bad page P _B
D _1A , D _2A ‧ ‧ sub-data actually stored in the bad page P _A
D _1B , D _2B ‧ ‧ sub-data actually stored in the bad page P _B

1 is a schematic diagram of the overall architecture of a data processing system to which the method of the present invention is applied.

2 is a schematic diagram of a bad page and a method for determining a strong/weak segment according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of storing original data in a bad page group after rearranging the original data according to an embodiment of the present invention.

4 is a schematic diagram of a data writing procedure of a management layer according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a data reading program of a management layer according to an embodiment of the present invention.

no

no

1232‧‧‧ data separator

1233‧‧‧ data shutter

122‧‧‧Encoder/decoder for performing error checking and correction mechanisms

P _set ‧‧‧bad page group

P _A , P _B ‧‧ ‧ bad page

Entity storage space segmentation in S _1A , S _2A ‧‧ ‧ bad page P _A

Entity storage space segmentation in S _1B , S _2B ‧‧ ‧ bad page P _B

S _aA ‧‧‧The spare area in the bad page P _A

Spare area in S _aB ‧‧‧Bad page P _B

D ₀ ‧‧‧Source

D _A ‧‧‧ first sub-data

D _B ‧‧‧Second sub-data

D _AA , D _BB ‧‧‧Data written by the data separator in the program

D _u ‧‧‧virtual information

D _AM1 , D _BM1 ‧‧‧ Data set output by the data masker in the program

D _AM2 , D _BM2 ‧‧‧Reading the data set output by the data masker

P _CA ‧‧‧First parity correction code

P _CB ‧‧‧Second parity correction code

D _AW ‧‧‧Information actually stored on the bad page P _A

D _BW ‧‧‧Information actually stored on the bad page P _B

D _1A , D _2A ‧ ‧ sub-data actually stored in the bad page P _A

D _1B , D _2B ‧ ‧ sub-data actually stored in the bad page P _B

Claims (10)

A method for accessing data by using a bad page of a flash memory, the method comprising a writing program for writing a piece of original data of a page size into a flash memory, the flash The memory includes at least a first bad page and a second bad page, wherein the first bad page and the second bad page both comprise a plurality of error bits, wherein the writing process comprises the following steps: using a data separator ( The data separator is divided into a first sub-data and a second sub-data, and the first sub-data and the second sub-data are separately copied to form two copies of the first sub-data and Two copies of the second sub-data; converting one of the two first sub-data and one of the two second sub-data into two dummy data by using a data masker; And forming a first data group and a second data group, wherein the first data group includes one of the two first sub-data and one of the two virtual data, the second data group includes the Two of the two second sub-data plus the two Another one of the virtual data; generating, by the encoder, a first parity correction code according to the first data set, and generating a second parity correction code according to the second data set; and generating the two first sub-data And the first parity correction code is combined to write the first bad page, and the two second sub-data and the second parity correction code are combined and written into the second bad page. The method for accessing data by using a bad page of a flash memory as described in claim 1 further includes a reading process, the steps comprising: dividing the physical storage space on the first bad page into an average a first segment and a second segment; the data masker converts the data content stored in the first segment into the virtual data; using a decoder to store the second segment in accordance with the first parity correction code pair Correcting the content of the data, and restoring the data content stored in the second segment to the first sub-data; dividing the physical storage space on the second bad page into a third segment and a fourth segment; The masker converts the data content stored in the third segment into the virtual data; using the decoder to correct the data content stored in the fourth segment according to the second parity correction code, and storing the data in the fourth segment The data content is restored to the second sub-data; and the first sub-data and the second sub-data obtained by the restoration are combined into the original data by using a data assembler. The method for accessing data by using a bad page of a flash memory as described in claim 2, if the decoder is based on the first parity correction code, the data stored in the second segment cannot be restored to The first sub-data, the reading program further comprises: the data masker determining that the number of the wrong bits in the second segment is greater than the number of the wrong bits in the first segment, and then reselecting The data stored in the second segment is converted into the virtual data, and the data content stored in the first segment is retained; and the decoder stores the data stored in the first segment according to the first parity correction code (parity) The content is corrected, and the data content stored in the first segment is restored to the first sub-data. The method for accessing data by using a bad page of a flash memory as described in claim 2, if the decoder is based on the second parity correction code, the data stored in the fourth segment cannot be restored to the The second sub-data, the reading program further comprises: the data masker determining that the number of the wrong bits in the fourth segment is greater than the number of the wrong bits in the third segment, and then re-selecting to store Converting the data in the fourth segment into the virtual data, and retaining the data content stored in the third segment; and the decoder corrects the data content stored in the third segment according to the second parity correction code, and The content of the data stored in the third paragraph is restored to the second sub-data. A method for accessing data by using a bad page of a flash memory as described in claim 2, which is applied to a flash memory controller, wherein the flash memory controller is electrically connected to the fast Flash memory, and has a flash translation layer (FTL), wherein if the original data needs to be split and stored in the first bad page and the second bad page, the original data will Transfer to the data splitter through the flash memory conversion layer. A method for accessing data by using a bad page of a flash memory as described in claim 5, which is applied to a data processing system, the data processing system including a host, the flash memory controller, a memory technology device (MTD) and the flash memory, wherein the host generates the original data and transmits the original data to the flash memory conversion layer, and the flash memory conversion layer The source data is input to the data separator, and the data separator outputs a data group including the two first sub-data and a data group including the two second sub-data, and transmits the data group to the memory technology device And then written into the flash memory. The method for accessing data by using a bad page of a flash memory as described in claim 6 further includes: selecting a location of the first bad page and the second bad page to be located in the flash memory In the adjacent two storage mates of the same die in the body, and the first bad page and the second bad page have the same displacement on the respective storage matrices. The method for accessing data by using a bad page of a flash memory as described in claim 7, further comprising: providing a parallel instruction to the memory technology device, wherein the two first sub-data and the When the first parity correction code is combined and written into the first bad page, the two second sub-data and the second parity correction code are also combined and written into the second bad page. The method for accessing data by using a bad page of a flash memory as described in claim 1, further comprising: providing a bad page recorder to record the first bad page and the second bad page entity Address. A method for accessing data by using a bad page of a flash memory as described in claim 1, wherein the first bad page has a first spare area, and the second bad page has a And a second spare area, in the writing process, the first parity correction code is written into the first spare area, and the second parity correction code is written into the second spare area.