TW479337B - High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process - Google Patents

High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process Download PDF

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Publication number
TW479337B
TW479337B TW090113447A TW90113447A TW479337B TW 479337 B TW479337 B TW 479337B TW 090113447 A TW090113447 A TW 090113447A TW 90113447 A TW90113447 A TW 90113447A TW 479337 B TW479337 B TW 479337B
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TW
Taiwan
Prior art keywords
chip
substrate
grid array
ball grid
heat sink
Prior art date
Application number
TW090113447A
Other languages
Chinese (zh)
Inventor
Ying-Jie Chen
Jeng-Yuan Lai
Tz-Yi Tian
Original Assignee
Siliconware Precision Industries Co Ltd
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Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW090113447A priority Critical patent/TW479337B/en
Application granted granted Critical
Publication of TW479337B publication Critical patent/TW479337B/en
Priority to US10/251,171 priority patent/US6716676B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

There is provided a high heat dissipation efficiency stacked-die BGA chip package technique for manufacturing BGA package unit with a stacked multi-chip architecture, wherein its middle lower layer chip is electrically coupled to the substrate by flip chip technique, and its upper layer chip is electrically coupled to the substrate by soldering wire technique. The present package technique is characterized in that a heat dissipation block is placed between a lower layer chip and an upper layer chip for contacting with the front face of the substrate, and the heat dissipation block is formed with a threading hole so that the wire in the soldering wire process passes through, from the upper layer chip, the threading hole of the heat dissipation block to bond on the substrate, thereby electrically coupling the upper layer chip to the substrate. Because the heat dissipation block directly contacts with the non-circuit face of the chip, the heat generated by the chip can be dissipated directly via the heat dissipation block, thereby providing a better heat dissipation efficiency. In addition, the heat dissipation block also can be provided as a low voltage grounding plane, so as to effectively promote the electrical function of the chip.

Description

五、發明說明（i ) [發明領域J 有關於—種具有W封裝技術，特別是 me Ban and Λ：，Γ^ [發明背景]y，GA)w封裝結構及製程。 本道晶片封裝技術可用以將二個或二個以上的 :導體晶片同時封裝於同-個封裝單元之中，使得單— ^單元即可提供較—般之單晶片封裝單元更大之操作 :及5己憶谷I。一般之半導體記憶體裝置，例如為快閃 、體裝置’即大多採用多晶片封裝技術來將二個或二個 上之記憶體晶片封裝於I個封裝單元之中，藉以使得 一個封裝單元即可提供數倍之記憶容量。 曰習知技術中常用的一種堆疊式多晶片架構係將下層 曰曰片利用覆晶技術（Flip Chip)電性藕接至基板 (substrate)，並將上層晶片利用銲線技術（Wke B^din幻電 性藕接至基板。以下即配合所附圖式中之第1圖及第2圖， 以圖解方式簡述此種封裝技術。 第1圖即顯示一習知之堆疊式球栅陣列型晶片封裝 結構。如圖所示，此晶片封裝結構包含以下構件：（a)一基 板100，其具有一正面l〇〇a和一背面100b，·（b)一第一晶 片U〇,其具有一電路面ll〇a和一非電路面n〇b，且其 電路面ll〇a係藉由覆晶技術利用婷料凸塊I〗〗而電性竊 接至基板100的正面100a ; (C)—第二晶片12〇，其具有 電路面120a和一非電路面120b，且其非電路面i2〇b 16312 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公沒） 479337 消 2 A7 五、發明說明（2 : 係藉由一黏膠層121而黏貼至第一晶片11〇的非電路面 膽；（d)複數條銲線14〇,其例如為金線，並係從第二晶 片I20的電路面12〇3向下打線至基板100的正面l〇0a, 用以將第二晶片12Q電性藕接至基板⑽；⑷―封裝膠體 15〇,用以包覆二個堆疊之晶片11〇、12〇;以及⑴一球柵 陣列（ballgridarray)16〇，其係植置於基板1〇〇的背面 i〇〇b，用以作為該封裝單元之外部電性連接點。 然而上述之堆疊式球柵陣列型晶片封裝結構的一項 缺點在於其具有不佳的散熱效能。這是由於其中所封裝之 曰曰片110 120並未設置有散熱設施，使得晶片i 1〇、12〇 於實際操作時所產生的熱量會累積於二個晶片110、120 之間。此外，由於下層晶片110所產生的熱量會傳導至上 層晶f120,使得上層晶片120更為易於受到熱應力破壞。 第2圖即顯示一習知之具有散熱效能之堆疊式球柵 陣列型晶片封裝結構。如圖所示，此晶片封裝結構大致與 第1圖所示者相同，其組成構件亦包含：（a)一基板2〇〇，、 其具有一正面200a和一背面200b ; (b)—第一晶片21〇， 其具有一電路面210a和一非電路面21〇b，且其電路面2i〇a 係藉由覆晶技術利用銲料凸塊211而電性藕接至基板2〇〇 的正面200a; (c)—第二晶片22〇,其具有一電路面公以 和一非電路面220b，且其非電路面22〇b係藉由_黏膠層 221而黏貼至第一晶片210的非電路面21〇b ;複數條 銲線240，其係從第二晶片22〇的電路面22〇a向下打線 ，至基板200的正面200a ’用以將第二晶片220電性藕接 本紙尺度適用中國國家標準（CNS)A‘：[規格（210 X 297公沒） 16312 裝 ---訂---------線 (請先閱讀背面之注意事項再填寫本頁) 479337 A7 ---- B7 經濟部智慧財產局員工消費合作社印製V. Description of the invention (i) [Invention field J relates to a kind of W packaging technology, especially me Ban and Λ :, Γ ^ [Background of the invention] y, GA) W packaging structure and manufacturing process. This chip packaging technology can be used to package two or more: conductor chips in the same packaging unit at the same time, so that a single unit can provide a larger operation than a normal single chip packaging unit: and 5 其 忆 谷 I. A general semiconductor memory device is, for example, a flash memory device. Most of them use multi-chip packaging technology to package two or more memory chips in one packaging unit, so that one packaging unit can be used. Provides several times the memory capacity. A stacked multi-chip architecture commonly used in conventional technology is to electrically connect the lower chip to the substrate using flip chip technology, and to use the wire bonding technology (Wke B ^ din The electromagnetism is connected to the substrate. The following is a schematic description of this packaging technology in conjunction with Figures 1 and 2 in the attached drawings. Figure 1 shows a conventional stacked ball grid array chip Packaging structure. As shown in the figure, the chip packaging structure includes the following components: (a) a substrate 100 having a front surface 100a and a back surface 100b, (b) a first chip U0, which has a The circuit surface 110a and a non-circuit surface n0b, and the circuit surface 110a are electrically connected to the front surface 100a of the substrate 100 by flip-chip technology using the bump T1; (C) —Second wafer 120, which has a circuit surface 120a and a non-circuit surface 120b, and its non-circuit surface i2〇b 16312 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public) 479337 2 A7 V. Description of the invention (2: Adhered to the non-circuit surface of the first chip 11 through an adhesive layer 121 (D) a plurality of bonding wires 14o, which are, for example, gold wires, and are wired down from the circuit surface 1203 of the second chip I20 to the front surface 100a of the substrate 100, for the second chip 12Q It is electrically connected to the substrate; ⑷—encapsulating gel 150, which is used to cover two stacked wafers 110, 120; and a ballgrid array 160, which is implanted on the substrate 10. The back surface of 〇 is used as the external electrical connection point of the package unit. However, one of the disadvantages of the above-mentioned stacked ball grid array chip package structure is that it has poor heat dissipation performance. This is due to the fact that The packaged chip 110 120 is not provided with heat dissipation facilities, so that the heat generated by the chips i 10 and 120 during actual operation will be accumulated between the two chips 110 and 120. In addition, the lower layer 110 The generated heat will be conducted to the upper crystal f120, making the upper wafer 120 more susceptible to thermal stress damage. Figure 2 shows a conventional stacked ball grid array chip package structure with heat dissipation performance. As shown in the figure, this The chip package structure is roughly the same as that shown in Figure 1. At the same time, its constituent components also include: (a) a substrate 200, which has a front surface 200a and a back surface 200b; (b) a first wafer 21, which has a circuit surface 210a and a non-circuit surface 21 〇b, and its circuit surface 2i0a is electrically connected to the front surface 200a of the substrate 200 by flip chip technology using the solder bump 211; (c) —the second wafer 22o, which has a circuit surface And a non-circuit surface 220b, and its non-circuit surface 22ob is adhered to the non-circuit surface 21ob of the first chip 210 through the _adhesive layer 221; a plurality of bonding wires 240, which are from the first The circuit surface 22a of the two wafers 22 is wired down to the front surface 200a of the substrate 200 'for electrically connecting the second wafer 220 to the paper. The size of the paper applies to China National Standard (CNS) A': [Specification (210 X 297 (Unknown) 16312 Packing --- Ordering ----------- Line (Please read the notes on the back before filling this page) 479337 A7 ---- B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

五、發明說明（3 ) 至基板200; (e)—封裝膠體250,用以包覆該些晶片210、 220 ;以及（f)一球柵陣列260，其係植置於基板200的背 面200b，用以做作為該封裝單元之外部電性連接點。為 了增加此封裝結構的散熱效能，其解決方法為加裝一散熱 塊230於基板200上。此散熱塊230具有一支撐部231和 一頂部232,且其支撐部231係支撐於基板200的正面200a 上，而頂部232則置於上層晶片220的上方。此設施可使 得二個晶片210、220於實際操作時所產生的熱量首先傳 導至介於第二晶片200與散熱塊230間之封裝樹脂，接著 再經由散熱塊230而發散至周圍環境。第2圖所示之封裝 結構因此較第1圖所示者具有更高之散熱效能。 然而第2圖所示之封裝結構於實際應用上卻至少具 有以下二項缺點。第一項缺點為散熱塊230並未直接接觸 至二個晶片210、220的非電路面220a、220b，晶片產生 的熱量，經由熱阻值高之樹脂，而間接的傳導至散熱塊 230，因此其散熱效能並不高。第二項缺點為兩晶片之背 面沒有一低電位的平面（如接地平面）可供黏置，導致晶片 之電性功能降低。 相關之專利技術例如包括有美國專利第5,726,079號 nTERMALLY ENHANCED FLIP CHIP PACKAGE AND METHOD OF FORMING，’ ；美國專利第 5,909,057 號 "INTEGRATED HEAD SPREADER/STIFFENER WITH APERTURES FOR SEMICONDUCTOR PACKAGE” ；美國 專利第 5,81 5,372 號"PACKAGING MULTIPLE DIES ON A 本紙張尺度適用中國國家標準（CN'S)A4規洛（210 x 297公釐） 16312 (請先閱讀背面之注意事項再^寫本頁) • *裝 士 . 丨線」 479337 A7 B7 五、發明說明（ BALL GRID ARRAY SUBSTRATE” ；等等。 (請先閲讀背面之注意事項再填寫本頁) 美國專利第5,726,〇70號和美國專利第5,909,057號 刀別揭路了一種具有高散熱效能之堆疊式球栅陣列型晶片 封裝技術。然而此二個專利技術並不適用於下層晶片利用 覆晶而上層晶片利甩録線的堆疊式多晶片架構，因此其無 法用來解決上述習知技術之缺點。 美國專利第5,815,372號雖然揭露了一種下層晶片利 用覆晶而上層晶片利用銲線的堆疊式多晶片架構，但由於 其基本架構大致相同於第1圖所示之習知技術，因此其亦 具有不佳之散熱效能。 [發明概述] 鑒於以上所述習知技術之缺點，本發明之主要目的 更疋在於k供種具有同散熱效能之堆疊式球柵陣列型晶 片封裝技術，其可將晶片之熱、量，藉由、散熱塊，直接逸散 熱量。 本發明之另-目的在於提供-種具有高散熱效能之 堆疊式球栅陣列型晶片封裝技術，其可將散熱塊直接接觸 至晶片的非電路面，藉此雨提供晶片之接地平面，而能改 善電性功能。 根據以上所述之目的，本發明即提供了一種新穎之 堆叠式球柵陣列型晶片封裝技術。 、 本，明之堆叠式球柵陣列型晶片封裝技術係用以製 作一堆疊式多晶片架構之球栅陣列型封裝單元，且其中下 層晶片係利用覆晶技術而電性藕接至基板， 規格⑵—— 層曰曰片貝1 16312 A7 五、發明說明（5 ). 係利用鲜線技術而電性藕接至美板。 本發明之堆疊式球柵陣列型晶片封裝技術的特點在 於將-散熱塊安置於下層晶片與上層晶片之間，並接觸至 土板的正面，且該散熱塊形成有複數個穿線孔，用以讓鲜 線程序中的銲線從上層晶片的電路面上穿過此些穿線孔而 打線至基板的正面，用以將上層晶片.電性藕接至基板。 由於散熱塊係直接接觸至晶片的非電路面’因此可 $供較習知技術更高之散熱效能。此外，本發明散熱塊之 a又置，可藉由其分別與晶片之非電路面接觸之結構，提供 該兩晶片一低電位之接地平面，而得有效提昇晶片之電性 功能。 [圖式簡述] 本發明之實質技'術内容及其實施例已用圖解方式詳 細揭露繪製於本說明書所附之圖式之中。此些圖式之内容 簡述如下： 第1圖（習知技術）為一剖面結構示意圖，其中顯示一 習知之堆疊式球柵陣列型晶片封裝結構； 經濟部智慧財產局員工消費合作社印製 第2圖（習知技術）為一剖面結構示意圖，其中顯示一 習知之高散熱放能之堆疊式球栅陣列型晶片封裝結構； 第3A至3D圖為剖面結構示意圖，其中顯示本發明 之堆疊式球柵陣列型晶片封裝技術於製程上的各個步驟，· 弟4圖為一上視結構示意圖，其中顯示本發明之堆 疊式球栅陣列型晶片封裝技術所採用之散熱塊的上視結構 形態； t @ i (CNS)A4 im (210 x 297¾ ) -；~ -*---- 5 16312 A7 B7 五、發明說明（ 您濟部智慧財產局員工消費合作社印製 第5圖為本發明/ L u 一 Θ封裝結構之另一實施例之剖面結構 示意圖；第6圖為本發明& 一 d封裝結構之又一實施例之剖面結構 示意圖； 一第7圖為本發明封裝結構之再一實施例之剖面結構 示意圖；以及 _第8圖為本發明封裝結構之又一實施例之剖面結構 示意圖。[圖式標號說明] 100 基板 100a基板1〇〇的正面 i〇〇b基板100的背面 11〇第一晶片 U〇a第一晶片110的電路面 110b第一晶片11()的非電路面 111 銲料凸塊 120a第二晶片120的電路面 120b第二晶片120的非電路面 121 黏膠層 14Q 150 封裝膠體 16〇 2〇〇基板 20〇b基板200的背面 第 片 銲線 球栅陣列 200a基板200的正面 210 第一晶片 210a第一晶片210的電路面 210b第一晶片210的非電路面 211 銲料凸塊 220 第二晶片 220a第二晶片220的電路面 本紙知尺度適用中國國家標準（CNS)A4規格（21〇 297公釐） 16312 n n —I]__Γ, I I- 一- π ________ _____ I . -- 1 · m 11 n i i —1 一σ,τ i i I m n I I ϋ n 1 (請先閱讀背面之注意事項再填寫本頁) 479337 A7 B7 五、發明說明（7 ) 220b苐·一晶片220的非電路面 221 黏膠層 230 散熱塊 231 散熱塊230的支撑部 232 散熱塊230 的項部 240 銲線 250 封裝膠體 260 球柵陣列 300 基板 300a 基板300 的正面 300b 基板300的背面 305 接地墊 310 第一晶片 310a 苐一晶片 31〇的電路面 310b 苐一晶片 3 1 0的非電路面 311 銲料凸塊 320 第二晶片 320a 第二晶片 320的電路面 320b 弟二晶片 320的非電路面 321 黏膠層 330 散熱塊 331 散熱塊330的支撐部 3 32 散熱塊330 的頂部 335 導電膠 337 外露部 340 鋒線 345 接地線 350 封裝膠體 360 球柵陣列 370 散熱塊 371 散熱塊370 的支撐部 372 散熱塊370的頂部 375 導熱膠 [發明實施例] 以下即配合所附圖式中之第3A至3D圖及第4圖， 詳細揭露說明本發明之堆疊式球栅陣列型晶片封裝技術之 一實施例。 請首先參閱第3A圖，本發明之堆疊式球柵陣列型晶 卜紙張尺度適用中關家標準(CNS)A4規格|_(2K) x 297公;望） (請先閱讀背面之注意事項再本頁) ---------^ ---------線. 經濟部智慧財產局員工消費合作社印製 16312 479337 A7 B7 五、發明說明（ 片封裝技術於製程上的第一徊丰 弟個步驟為預製一球柵陣列型之 基板300 ’其具有一正面3〇 UUa和一背面300b，且其正面 300a.和背面300b均設晋右访把加； 置有複數個電性銲接點及導電跡線 (未顯示）。 接著下一個步驟為將_筮_ • 卜 第一日日片310安置於基板3 00 上，該苐一晶片310具有一 φ ^ 逼路面3 1 〇a和一非電路面 310b，且其電路面31〇a係蕤 、 猎由覆晶技術（Flip Chip)利用 複數個銲料凸塊3 11而電性巍接 电庇_接至基板300的正面3〇〇a。 請接著參閱第3B圖及篥4r ^ 7 口汉弟4圖，下一個步驟將一散熱 塊（headspreader)330 安置於其缸 文1於基板3〇〇上，·該散熱塊33〇 的材質為一高導熱性材料，彳彳 例如為鋼，且其具有一支撐部 3 3 1和一頂部3 3 2 ’且頂部3 3 ?游少士 、1 3 2七成有複數個穿線孔3 3 3。 此散熱塊3 3 0的安置方或在脱甘+ ^ 女置万式係將其支撐部331安置於基板 300的正面300a上，並將 灯貝4 332以導電、導埶之黏 膠321直接壓貼至第一 的 令… 〜 月310的非電路面310b上（亦即 使#頂部3 3 2導熱性地接觸至篥 嗎主弟晶片310的非電路面 310b)。 請接著參閱第3C圖，下—個步驟為將—第二晶片32〇 ^於散熱塊330的頂部332上；該第二半導體晶32〇具 有一具有一電路面3 20a和一非雷牧二 / 不 邪冤路面320b，且其安置方 式係將其非電路面32〇b 導 ^ 以導電導熱之黏膠321黏貼至 散熱塊330的頂部332。第-丰邋獅曰。 系一牛導體晶320安置於定位上 後’接著即進行一銲線程序，葬 μ 斤藉此而將複數條銲線340， 例如為金製銲線，從第二晶Μ + ^一；--: _ 月320的電路面32〇a匕穿過 1氏張尺度家標準（CNS)A4規格^；297公釐 ------- --- 8 (請先閱讀背面之注意事項再填寫本頁) 16312 479337V. Description of the invention (3) to the substrate 200; (e)-encapsulating gel 250 for covering the wafers 210, 220; and (f) a ball grid array 260, which is implanted on the back surface 200b of the substrate 200 Is used as an external electrical connection point of the packaging unit. In order to increase the heat dissipation efficiency of the package structure, a solution is to install a heat sink 230 on the substrate 200. The heat sink 230 has a support portion 231 and a top portion 232. The support portion 231 is supported on the front surface 200 a of the substrate 200, and the top portion 232 is disposed above the upper layer wafer 220. This facility allows the heat generated by the two chips 210, 220 to be transferred to the encapsulating resin between the second chip 200 and the heat sink 230 during the actual operation, and then dissipated to the surrounding environment through the heat sink 230. The package structure shown in Figure 2 therefore has a higher heat dissipation efficiency than that shown in Figure 1. However, the package structure shown in Figure 2 has at least the following two disadvantages in practical applications. The first disadvantage is that the heat sink 230 does not directly contact the non-circuit surfaces 220a and 220b of the two chips 210 and 220. The heat generated by the wafer is indirectly transmitted to the heat sink 230 via a resin with a high thermal resistance value. Its heat dissipation efficiency is not high. The second disadvantage is that there is no low-potential plane (such as a ground plane) on the back of the two chips, which reduces the electrical functions of the chips. Related patent technologies include, for example, U.S. Patent No. 5,726,079, nTERMALLY ENHANCED FLIP CHIP PACKAGE AND METHOD OF FORMING, '; U.S. Patent No. 5,909,057 " INTEGRATED HEAD SPREADER / STIFFENER WITH APERTURES FOR SEMICONDUCTOR PACKAGE "; U.S. Patent No. 5,81 5,372 No. " PACKAGING MULTIPLE DIES ON A The paper size is applicable to the Chinese National Standard (CN'S) A4 gauge (210 x 297 mm) 16312 (Please read the precautions on the back before writing this page) • * Equipment. 丨 Line "479337 A7 B7 V. Description of the invention (BALL GRID ARRAY SUBSTRATE"; etc. (Please read the precautions on the back before filling out this page) US Patent No. 5,726, 〇70 and US Patent No. 5,909,057 A stacked ball grid array chip packaging technology with high heat dissipation efficiency. However, these two patented technologies are not applicable to a stacked multi-chip architecture in which the lower layer chip uses a flip chip and the upper layer chip uses a recording line, so it cannot be used Solve the shortcomings of the above-mentioned conventional technology. Although US Patent No. 5,815,372 discloses a lower-layer wafer advantage The flip-chip and upper-layer chip use a stacked multi-chip architecture of bonding wires, but because its basic architecture is roughly the same as the conventional technology shown in Figure 1, it also has poor heat dissipation performance. [Summary of the Invention] In view of the above The disadvantages of the known technology, the main purpose of the present invention is to provide a stacked ball grid array chip packaging technology with the same heat dissipation performance, which can directly dissipate the heat and quantity of the chip through the heat dissipation block. Another object of the present invention is to provide a stacked ball grid array chip packaging technology with high heat dissipation efficiency, which can directly contact the heat sink to the non-circuit surface of the chip, thereby providing a ground plane for the chip, According to the above-mentioned object, the present invention provides a novel stacked ball grid array chip packaging technology. The present invention provides a stacked ball grid array chip packaging technology which is used to make a Stacked multi-chip structure ball grid array type packaging unit, and the lower layer of the chip is electrically connected to the substrate using flip-chip technology, specification ⑵—— layer Pinch 1 16312 A7 V. Description of the invention (5). It is electrically connected to the US board using fresh wire technology. The stacked ball grid array chip packaging technology of the present invention is characterized in that a heat sink is placed on the lower chip and Between the upper-layer wafers and in contact with the front side of the soil plate, and the heat sink block is formed with a plurality of threading holes to allow the bonding wires in the fresh wire procedure to pass through these threading holes from the circuit surface of the upper-layer chip to the The front side of the substrate is used to electrically connect the upper layer wafer to the substrate. Since the heat-dissipating block is in direct contact with the non-circuit surface of the chip, it can provide higher heat-dissipating performance than the conventional technology. In addition, the a of the heat dissipation block of the present invention is provided, and the low-potential ground plane of the two wafers can be provided by the structures in contact with the non-circuit surfaces of the wafers, thereby effectively improving the electrical functions of the wafers. [Brief Description of the Drawings] The essential technical contents of the present invention and its embodiments have been disclosed in detail in a diagrammatic manner in the drawings attached to this specification. The contents of these drawings are briefly described as follows: Figure 1 (known technology) is a schematic cross-sectional structure diagram showing a conventional stacked ball grid array chip package structure; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 2 (conventional technology) is a schematic cross-sectional structure diagram showing a conventional high-heat-dissipating stacked ball grid array chip package structure; Figures 3A to 3D are schematic cross-sectional structure diagrams showing the stacked type of the present invention Each step in the manufacturing process of the ball grid array chip packaging technology, Figure 4 is a schematic diagram of a top view structure, which shows the top view structure of the heat sink used in the stacked ball grid array chip packaging technology of the present invention; t @ i (CNS) A4 im (210 x 297¾)-; ~-* ---- 5 16312 A7 B7 V. Description of the invention (printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the People's Republic of China. Figure 5 is the invention / L u A schematic cross-sectional structure diagram of another embodiment of a Θ package structure; FIG. 6 is a schematic cross-sectional structure diagram of another embodiment of the & d package structure; FIG. 7 is a schematic diagram of a package structure of the present invention Schematic diagram of a cross-sectional structure of an embodiment; and FIG. 8 is a schematic diagram of a cross-sectional structure of another embodiment of the packaging structure of the present invention. [Illustration of drawing symbols] 100 substrate 100a substrate 100 front side 100 substrate 100 The back surface 110, the first wafer U0a, the circuit surface 110b of the first wafer 110, the non-circuit surface 111 of the first wafer 11 (), the solder bump 120a, the circuit surface 120b of the second wafer 120, and the non-circuit surface 121 of the second wafer 120. Adhesive layer 14Q 150 Encapsulated gel 16200 substrate 200b Back of substrate 200 First piece of wire ball grid array 200a Front surface of substrate 200 First wafer 210a First circuit surface 210b First wafer 210 210b Circuit surface 211 Solder bump 220 The second wafer 220a The circuit surface of the second wafer 220 The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (21〇297 mm) 16312 nn —I] __ Γ, I I- a-π ________ _____ I.-1 · m 11 nii —1 σ, τ ii I mn II ϋ n 1 (Please read the notes on the back before filling out this page) 479337 A7 B7 V. Description of the invention (7) 220b 苐 · Non-circuit surface 221 of a chip 220, adhesive layer 230, heat dissipation 231 Support section of heat sink 230 232 Section of heat sink 230 240 Welding wire 250 Package gel 260 Ball grid array 300 Substrate 300a Front side of substrate 300b 300b Back side of substrate 300 305 Ground pad 310 First wafer 310a One wafer 31 ° Circuit surface 310b Non-circuit surface 311 of the wafer 3 1 0 311 Solder bump 320 Second circuit 320a of the second wafer 320 Circuit surface 320b Second non-circuit surface of the wafer 320 321 Adhesive layer 330 Heat sink 331 Heat sink 330 Support 3 32 Top of heat sink 330 335 Conductive glue 337 Exposed part 340 Front line 345 Ground wire 350 Package gel 360 Ball grid array 370 Heat block 371 Support block of heat block 370 Top of heat block 370 Heat sink 370 [Invention example The following is a detailed description of one embodiment of the stacked ball grid array type chip packaging technology of the present invention in conjunction with the 3A to 3D drawings and 4 drawings in the drawings. Please refer to FIG. 3A first. The stacked ball grid array type crystal cloth paper standard of the present invention is applicable to the Zhongguanjia Standard (CNS) A4 specification | _ (2K) x 297 male; hope) (Please read the precautions on the back before (This page) --------- ^ --------- line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 16312 479337 A7 B7 V. Description of the invention (chip packaging technology on the manufacturing process The first step is to prefabricate a ball grid array type substrate 300 ', which has a front surface 30UUa and a back surface 300b, and the front surface 300a. And the back surface 300b are each provided with a plurality of right and left; Electrical solder joints and conductive traces (not shown). The next step is to place the first day plate 310 on the substrate 3 00. The first wafer 310 has a φ ^ force on the road 3 1 〇a and a non-circuit surface 310b, and its circuit surface 31〇a is based on Flip Chip technology, which uses a plurality of solder bumps 3 11 to electrically connect and shield _ connected to the front surface of the substrate 300 3〇〇a. Please refer to Figure 3B and Figure 4r ^ 7 Han Handi Figure 4, the next step is to place a headspreader 330 in its cylinder 1 on the substrate 300, the material of the heat sink 33 is a highly thermally conductive material, such as steel, and has a support portion 3 3 1 and a top portion 3 3 2 'and a top portion 3 3? You Shaoshi, 1 3 2 Qicheng has a plurality of threading holes 3 3 3. The placement of this heat sink 3 3 0 may be in the Gangan + ^ women's style, and its support portion 331 is placed on the front surface 300a of the substrate 300 And press the light shell 4 332 with conductive, conductive adhesive 321 directly to the first order ... ~ month 310 on the non-circuit surface 310b (even if #Top 3 3 2 thermally contacts the 篥The non-circuit surface 310b of the younger chip 310. Please refer to FIG. 3C. The next step is to place the second chip 32 on the top 332 of the heat sink 330. The second semiconductor chip 32 has A circuit surface 3 20a and a non-lightning animal husbandry / non-evil road pavement 320b are arranged in such a manner that the non-circuit surface 32ob is guided to the top 332 of the heat sink 330 with a conductive adhesive 321. -Feng Lishi said. After a cow conductor crystal 320 is placed in position, a welding wire procedure is performed, and a plurality of welding wires are buried in this way. 340, for example, a gold bonding wire, from the second crystal M + ^ one;-: _ month 320 of the circuit surface 32 〇a dagger through the 1's scale home standard (CNS) A4 specifications ^; 297 mm- ------ --- 8 (Please read the notes on the back before filling this page) 16312 479337

請 先 閱 讀 背 面 之 注 意 事 項 再 填 寫 本 頁 A7 A7 10 五、發明說明（1〇 ). 頂部372，使得於发Please read the notes on the back before filling in this page A7 A7 10 V. Description of the invention (1〇). Top 372

、/、支撐邛371上黏置導埶膠375後，可 導熱地黏置於該安署於苴/ 守…胗 J ,39 h，^ :基板3〇〇上之散熱塊330之頂部 /、頂部372之表面外露於封裝膠體350外， 俾進一 ^幵本發明封裝結構之散熱效能。. 十2廢8圖所示，本發明封裝結構之再一實施例係於 前述各實施例（第8圖係以篦s同& . 33。上之適當位置户二第圖所示結構為例)之散熱塊 置處局。卩延設外露部337,使其最外端之 表面338侍外露於封奘 衣膠體350之外，俾可進一步提昇本 發明封裝結構之散熱效能。 綜而言之，本發明提供了一種具有高散熱效能之堆 疊式球柵陣列型晶片封裝技術。相較於習知技術，本發明 之堆疊式球栅陣列型晶片封裝技術具有以下之優點。亦 即，本發明所採用之I敎 双，、、、塊330的頂部332係直接接觸至 二個晶片310、32G的非電路面31()b、3織，因此可提供 較第2圖所示之習知技術更高之散熱效能m㈣ 所採用之散熱塊330的頂部332係安置於二個晶片31〇、 320之間’因此可提供—低電位之接地平面，而得有效提 昇晶片之電性功能。本發明因此較習知技術具有更佳之進 步性及實用性。 以上所述僅為本發明之較佳實施例而已，並非用以 ^定本發明之實質技術内容的範圍。本發明之實質技術内 容係廣義地定義於下述之申請專利範圍中。任何他人所完 成之技術實體或方法，若是與下述之申請專利範圍所定義 I者為完全相同、或是為^變例如將外露部337 本紙張尺度朝巾關家鮮（CNSM4祕⑵0x297公髮) --------- 16312、 /, After the adhesive 375 is adhered to the support 371, it can be thermally adhered to the security agency at 苴 / 守 ... 胗 J, 39 h, ^: on top of the heat sink 330 on the substrate 300 /, The surface of the top portion 372 is exposed outside the encapsulant 350, which further improves the heat dissipation performance of the package structure of the present invention. As shown in Fig. 12 and Fig. 8, another embodiment of the packaging structure of the present invention is in each of the foregoing embodiments (Fig. 8 shows the appropriate position on the & 33. The structure shown in Fig. 2 is Example) The heat sink is located. (2) Extending the exposed portion 337 so that the outermost surface 338 is exposed outside the sealing gel 350, which can further improve the heat dissipation performance of the packaging structure of the present invention. In summary, the present invention provides a stacked ball grid array type chip packaging technology with high heat dissipation efficiency. Compared with the conventional technology, the stacked ball grid array chip packaging technology of the present invention has the following advantages. That is, the top 332 of the I, D, and B blocks 330 used in the present invention is in direct contact with the non-circuit surfaces 31 () b and 3 of the two wafers 310 and 32G. Shown the higher heat dissipation efficiency of the conventional technology m㈣ The top 332 of the used heat sink 330 is placed between the two wafers 31 and 320. Therefore, a low-level ground plane can be provided, which can effectively improve the electricity of the wafer. Sexual function. Therefore, the present invention has better progress and practicability than the conventional technology. The above are merely preferred embodiments of the present invention, and are not intended to determine the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of patent application described below. Any technical entity or method completed by others, if it is exactly the same as defined in the scope of the patent application below, or it is a ^ change, for example, the exposed part of the paper 337 paper size toward the towel (CNSM4 secret 0x297) ) --------- 16312

5 先 閱 讀 背- 面 之 意· 事 項 再 填 | ί裝 頁I 訂 線 479337 A7 五、發明說明（u ). :成於散熱塊330之其他位置上，或是形成於加設在散熱 L Μ:上之另一散熱塊WO上之適當位置處者，均將被視 為涵蓋於此專利範圍之中。 、 --------訂.-------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ,t、紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 16312 115 First read the back-the meaning of the matter · fill in the matter again | tiling page I Thread 479337 A7 V. Description of the invention (u).: It is formed on other positions of the heat sink 330, or it is formed on the heat sink L Μ : Any other appropriate position on the other heat sink WO will be deemed to be covered by this patent. , -------- Order .-------- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, t and paper standards are applicable to China Standard (CNS) A4 size (210 X 297 mm) 16312 11

Claims (1)

479337479337 ϋ3 1〇%^]ί 第90113447號專利申請案 L — 申請專利範圍修正本 (90年12月17曰） 1· 一種堆疊式球柵陣列型晶片封裝結構，其至少包含以下 構件： (a) —基板’其具有一正面和一背面； (b) —第一晶片，其具有一電路面和一非電路面， 且其電路面係藉由覆晶技術而電性藕接至該基板的正 面； (0 —散熱塊，其具有一支撐部和一頂部，且其頂 部形成有至少一穿線孔；該散熱塊的支撐部係安置於該 基板的正面上，而其頂部則係導熱性地接置至該第一晶 片的非電路面； (d) —第二晶片，其具有一電路面和一非電路面， 且其非電路面係導熱性地接置於該散熱塊的頂部上； (e) 複數條銲線，其係從該第二晶片的電路面上穿 過該散熱塊之頂部上的穿線孔而打線至該基板的正面 上’用以將該第二晶片電性藕接至該基板； 經濟部中央標準局員工福利委員會印製 (f) 一封裝膠體，其包覆住該基板之正面、該第一 晶片、該散熱塊、該第二晶片及該等銲線；以及 (g) 複數個銲球，其次球柵陣列形態植於該基板之 背面上。 2.如申請專利範圍第i項所述之堆疊式球柵陣列型晶片封 裝結構，其中該散熱塊係為銅製。 3·如申請專利範圍第1項所述之堆疊式球栅陣列型晶片封 16312 1 本紙張尺度適用中國國家標準（CNS )A4規格（210X 297公愛) " 裝結構，其中該些銲線係為金製銲線 4·如申請專利範圍第1項所述之堆疊式球柵陣列型晶片封 裝結構’其中，該散熱塊之頂部係以可導電並導熱之黏 膠接置於該第一晶片之非電路面。 5·如申請專利範圍第1項所述之堆疊式球柵陣列型晶片封 裝結構’其中，該第二晶片之非電路面係以可導電並導 熱之黏膠接置於該散熱塊之頂部上。 6·如申請專利範圍第1項所述之堆疊式球柵陣列型晶片封 裝結構’其中，該散熱塊之支撐部係以導電膠黏置於該 基板之正面上所設之接地墊上。 7 ·如申睛專利範圍第1項所述之堆疊式球柵陣列型晶片封 裝結構，其中，該第二晶片之接地銲墊與該散熱塊之頂 部上復銲設有一接地線。 8 ·如申請專利範圍第1項所述之堆疊式球柵陣列型晶片封 裝結構’其中，該散熱塊之頂部上復可導熱地接設有一 具有至少一外露表面之散熱塊。 經濟部中央標準局員工福利委員會印製 9·如申請專利範圍第1或第8項所述之堆疊式球柵陣列型 晶片封裝結構，其中，該散熱塊上復延設有具有外露表 面之外露部。 1〇·—種堆疊式球柵陣列型晶片封裝製程，其至少包含以下 步驟： (1) 預製一基板，其具有一正面和一背面； (2) 將一第一晶片安置於該基板上；該第一晶片具 有一電路面和一非電路面，且其電路面係藉由覆晶技術 而電性藕接至該基板的正面； 本紙張尺度適用中國國家標準（c N S ) A 4規格（210 X 297公釐) 2 16312 479337 (3) 將一散熱塊安置於該基板上；該散熱塊具有一 支撐部和一頂部，且其頂部形成有至少一穿線孔；其中 該散熱塊的支撐部係安置於該基板的正面上，而其頂部 則係導熱性地接置至該第一晶片的非電路面上； (4) 將一第二晶片安置於該散熱塊上；該第二晶片 具有一電路面和一非電路面，且其非電路面係導熱性知 接置至該散熱塊的頂部；以及 (5) 進行一銲線程序’藉此而將複數條銲線從該第 二晶片的電路面上穿過該散熱塊之頂部上的穿線孔而 打線至該基板的正面上，用以將該第二晶片電性藕接3 該基板； (6) 進行一封膠程序，俾包覆住該基板之正面，該 第一晶片、該散熱塊、該第二晶片及該等銲線以及 (7) 進行一植球程序，俾將球栅陣列植置於該基板 之背面上。 1·如申請專利範圍第項所述之堆叠式球柵陣列型晶片 封裝製程，其中步驟（3)所述之散熱塊係為銅製。 經濟部中央標準局員工福利委員會印製 2·如申請專利範圍第1〇項所述之堆疊式球栅陣列型晶片 封裝製程，其中步驊（5)所述之銲線係為金製銲線。 13·如申請專利範圍第1〇項所述之堆疊式球柵陣列型晶片 封裝製程，其甲，該散熱塊之頂部係以可導電並導熱之 黏膠接置於該第一晶片之非電路面。 •如申請專利範圍第10項所述之堆疊式球栅陣列型晶片 封裝製程，其中，該第二晶片之非電路面係以可導電並 接置於該散熱塊之頂部上 規格（雇297 公笼）— 3 16312 479337 ___ H3 15·如申請專利範圍第10項所述之堆疊式球栅陣列型晶片 封裝製程’其中，該散熱塊之支撐部係以導電膠黏置於 該基板之正面上所設之接地墊上。 16·如申請專利範圍第1〇項所述之堆疊式球栅陣列型晶片 封裝製程’其中，該第二晶片之接地銲墊塊與散熱塊之 頂部上復鲜設有一接地線。 17·如申請專利範圍第10項所述之堆疊式球柵陣列型晶片 封裝製程’其中，該散熱塊之頂部上復可導熱地接設有 一具有至少一外露表面之散熱塊。 18·如申請專利範圍第1或第8項所述之堆疊式球栅陣列型 晶片封裝製程，其中，該散熱塊上復延設有具有外露表 面之外露部。 19.一種堆疊式球栅陣列型晶片封裝結構，其至少包含以下 構件： (a) —基板’其具有一正面和一背面； (b) —第一晶片，其具有一電路面和一非電路面， 且其電路面係藉由覆晶技術而電性藕接至該基板的正 面； 經濟部中央標準局員工福利委員會印製 (c) 一第一散熱塊，其具有一支撐部和一頂部，且 其頂部形成有至少一穿線孔；該第一散熱塊的支撐部係 安置於該基板的正面上，而其頂部則係導熱性地接置至 該第一晶片的非電路面； (d) —第二晶片，其具有一電路面和一非電路面， 且其非電路面係導熱性地接置於該散熱塊的頂部上，·ϋ3 1〇% ^] ί Patent Application No. 90113447 L — Amendment of Patent Application Scope (December 17, 1990) 1. A stacked ball grid array chip package structure, which includes at least the following components: (a) —Substrate 'with a front surface and a back surface; (b) —a first wafer with a circuit surface and a non-circuit surface, and the circuit surface of which is electrically connected to the front surface of the substrate by flip-chip technology (0 — heat dissipation block, which has a support portion and a top portion, and at least one threading hole is formed on the top portion; the support portion of the heat dissipation block is disposed on the front surface of the substrate, and the top portion is thermally grounded Placed on the non-circuit surface of the first chip; (d) a second chip having a circuit surface and a non-circuit surface, and the non-circuit surface is thermally connected to the top of the heat sink; e) a plurality of bonding wires, which are routed from the circuit surface of the second chip through the through holes on the top of the heat sink to the front side of the substrate to electrically connect the second chip to The substrate; printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs (f) a packaging gel covering the front surface of the substrate, the first chip, the heat sink, the second chip and the bonding wires; and (g) a plurality of solder balls, followed by a ball grid array On the back surface of the substrate. 2. The stacked ball grid array chip package structure described in item i of the patent application scope, wherein the heat sink is made of copper. 3. The stack described in item 1 of the patent application scope. Type ball grid array chip seal 16312 1 This paper size applies to China National Standard (CNS) A4 specification (210X 297 public love) " mounting structure, where these bonding wires are gold bonding wires. The stacked ball grid array chip package structure according to item 1, wherein the top of the heat dissipation block is placed on the non-circuit surface of the first chip with a conductive and thermally conductive adhesive. The stacked ball grid array chip package structure according to item 1, wherein the non-circuit surface of the second chip is placed on the top of the heat sink with a conductive and thermally conductive adhesive. 6 · If the scope of the patent application The stacked ball grid array type described in item 1 The chip package structure 'wherein the support portion of the heat sink is placed on a ground pad provided on the front surface of the substrate with a conductive adhesive. 7 · A stacked ball grid array chip as described in item 1 of Shenyan's patent scope The package structure, wherein a ground wire is re-soldered on the ground pad of the second chip and the top of the heat sink. 8 · The stacked ball grid array type chip package structure described in the first item of the patent application scope, wherein A heat-dissipating block with at least one exposed surface is connected to the top of the heat-dissipating block. Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs 9 · The stacking type described in item 1 or 8 of the scope of patent application The ball grid array type chip package structure, wherein the heat dissipation block is further provided with an exposed portion having an exposed surface. 1 ·· A stacked ball grid array type wafer packaging process, which includes at least the following steps: (1) prefabricating a substrate having a front surface and a back surface; (2) placing a first wafer on the substrate; The first chip has a circuit surface and a non-circuit surface, and the circuit surface is electrically connected to the front surface of the substrate by a flip-chip technology; the paper size is applicable to the Chinese National Standard (c NS) A 4 specification ( (210 X 297 mm) 2 16312 479337 (3) A heat sink is disposed on the substrate; the heat sink has a support portion and a top portion, and at least one threading hole is formed on the top portion; wherein the support portion of the heat dissipation block Is placed on the front surface of the substrate, and the top is thermally connected to the non-circuit surface of the first wafer; (4) a second wafer is placed on the heat sink; the second wafer has A circuit surface and a non-circuit surface, and the non-circuit surface is thermally conductively connected to the top of the heat sink; and (5) a wire bonding process is performed to thereby remove a plurality of bonding wires from the second chip On the circuit surface through the top of the heat sink A wire is threaded to the front surface of the substrate to electrically connect the second wafer to the substrate; (6) a glue process is performed to cover the front surface of the substrate, the first wafer, the The heat-dissipating block, the second chip and the bonding wires, and (7) perform a ball-planting procedure, and the ball grid array is planted on the back surface of the substrate. 1. The stacked ball grid array type wafer packaging process as described in item 1 of the scope of patent application, wherein the heat dissipation block described in step (3) is made of copper. Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs 2 · The stacked ball grid array chip packaging process as described in item 10 of the patent application scope, in which the bonding wire described in step (5) is a gold bonding wire . 13. According to the stacked ball grid array type chip packaging process described in item 10 of the scope of patent application, the top of the heat sink is connected to the non-circuit of the first chip with a conductive and thermally conductive adhesive. surface. • The stacked ball grid array chip packaging process as described in item 10 of the scope of patent application, wherein the non-circuit surface of the second chip is electrically conductive and placed on the top of the heat sink. Cage) — 3 16312 479337 ___ H3 15 · The stacked ball grid array type chip packaging process described in item 10 of the scope of patent application, wherein the support portion of the heat sink is placed on the front surface of the substrate with conductive adhesive Set on the ground pad. 16. The stacked ball grid array type chip packaging process as described in item 10 of the scope of patent application, wherein a ground line is provided on the top of the ground pad and the heat sink of the second chip. 17. The stacked ball grid array type chip packaging process according to item 10 of the scope of patent application, wherein a heat dissipation block having at least one exposed surface is thermally connected to the top of the heat dissipation block. 18. The stacked ball grid array type chip packaging process according to item 1 or 8 of the scope of application for a patent, wherein the heat sink is further provided with an exposed portion having an exposed surface. 19. A stacked ball grid array type chip packaging structure, comprising at least the following components: (a) a substrate having a front surface and a back surface; (b) a first chip having a circuit surface and a non-circuit Surface, and its circuit surface is electrically connected to the front side of the substrate by flip-chip technology; printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs (c) a first heat sink with a support portion and a top And at least one threading hole is formed on the top thereof; the supporting portion of the first heat sink is disposed on the front surface of the substrate, and the top thereof is thermally connected to the non-circuit surface of the first chip; (d ) — A second chip, which has a circuit surface and a non-circuit surface, and the non-circuit surface is thermally connected to the top of the heat sink, H3 過該散熱塊之頂部上的穿線孔而打線至該基板的正面 上’用以將該第二晶片電性藕接至該基板； (0—第二散熱塊，其具有一支撐部和一頂部，且 其支撐部係導熱地安置於該第一散熱塊之頂部上，而其 頂部具有至少一外露表面； (g) 一封裝膠體，其包覆住該基板之正面，該第一 晶片、該第一散熱塊、該第二晶片、該第二散熱塊、及 該等銲線；以及 (h) 複數個銲球，其次球栅陣列形態植於該基板之 背面上。 2〇·如申請專利範圍第19項之堆疊式球柵陣列型晶片封裝 結構’其中該第一散熱塊及該第二散熱塊係為銅製。 21·如申請專利範圍第19項所述之堆疊式球栅陣列型晶片 封裝結構，其中該些鋒線係為金製銲線。 22·如申請專利範圍第19項所述之堆疊式球栅陣列型晶片 封裝結構，其中，該第一散熱塊之頂部係以可導電並導 熱之黏膠接置於該第一晶片之非電路面。 23·如申請專利範圍第19項所述之堆疊式球柵陣列型晶片 封裝結構，其中，該第二晶片之非電路面係以可導電並 導熱之黏膠接置於該散熱塊之頂部上。 24·如申請專利範圍第19項所述之堆疊式球柵陣列型晶片 封裝結構，其中，該第二散熱塊係以導熱膠黏置於該第 一散熱塊之頂部上。 25·如申請專利範圍第19項所述之堆疊式球柵陣列型晶片 封裝、结構，其中，該第一散熱塊之支撐部係以導電膠黏 紙張尺度適用中國國家標準（C n s ) A 4規格（210 X 297公釐) 5 16312 H3 置於該基板之正面上所設之接地墊上。 •如申請專利範圍第19項所述之堆疊式球柵陣列型晶片 封裝結構’其中，該第二晶片之接地銲墊塊與散熱塊之 頂部上復銲設有一接地線。 27 ·如申請專利範圍第i或第8項所述之堆疊式球柵陣列型 晶片封裝結構，其中，該散熱塊上復延設有具有外露表 面之外露部。H3 is wired to the front surface of the substrate through a through hole on the top of the heat sink block to electrically connect the second chip to the substrate; (0—a second heat sink block having a support portion and a The top portion, and the supporting portion thereof is thermally disposed on the top of the first heat dissipation block, and the top portion has at least one exposed surface; (g) a packaging gel covering the front surface of the substrate, the first chip, The first heat-dissipating block, the second chip, the second heat-dissipating block, and the bonding wires; and (h) a plurality of solder balls, and secondly, a ball grid array shape is planted on the back surface of the substrate. 2．If applied The stacked ball grid array type chip package structure of the item 19 of the patent scope 'wherein the first heat dissipation block and the second heat dissipation block are made of copper. 21 · The stacked ball grid array type described in the item 19 of the patent scope Chip packaging structure, wherein the front lines are gold bonding wires. 22. The stacked ball grid array type chip packaging structure described in item 19 of the scope of patent application, wherein the top of the first heat sink is conductive. And a thermally conductive adhesive is placed on the first The non-circuit surface of the chip. 23. The stacked ball grid array chip package structure as described in item 19 of the patent application scope, wherein the non-circuit surface of the second chip is placed on a conductive and thermally conductive adhesive. 24. The stacked ball grid array type chip packaging structure according to item 19 of the scope of application for patent, wherein the second heat dissipation block is placed on top of the first heat dissipation block with a thermally conductive adhesive. 25. The stacked ball grid array chip package and structure as described in item 19 of the scope of patent application, wherein the support portion of the first heat sink is a conductive adhesive paper scale applicable to Chinese national standards (C ns) A 4 size (210 X 297 mm) 5 16312 H3 is placed on the ground pad provided on the front side of the substrate. • The stacked ball grid array type chip package structure described in item 19 of the patent application scope, wherein, the A ground wire is re-soldered on the top of the ground pad and the heat sink of the second chip. 27. The stacked ball grid array chip package structure described in item i or item 8 of the patent application scope, wherein the heat sink On-block repetition There is an exposed part with an exposed surface. 經濟部中央標準局員工福利委員會印製 本紙張尺度適用中國國家標準（CNS )A4規格（210X 297公楚) 6 16312Printed by the Staff Welfare Committee of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210X 297)
TW090113447A 2001-06-04 2001-06-04 High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process TW479337B (en)

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Publication number Priority date Publication date Assignee Title
TWI419270B (en) * 2011-03-24 2013-12-11 Chipmos Technologies Inc Package on package structure
TWI451543B (en) * 2011-03-07 2014-09-01 Unimicron Technology Corp Package structure, fabrication method thereof and package stacked device thereof
CN104269385A (en) * 2014-10-21 2015-01-07 矽力杰半导体技术(杭州)有限公司 Packaging assembly and manufacturing method of packaging assembly
TWI594258B (en) * 2014-04-01 2017-08-01 美光科技公司 Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
TWI637536B (en) * 2017-02-24 2018-10-01 矽品精密工業股份有限公司 Electronic package structure and the manufacture thereof
US10453820B2 (en) 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451543B (en) * 2011-03-07 2014-09-01 Unimicron Technology Corp Package structure, fabrication method thereof and package stacked device thereof
TWI419270B (en) * 2011-03-24 2013-12-11 Chipmos Technologies Inc Package on package structure
TWI594258B (en) * 2014-04-01 2017-08-01 美光科技公司 Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
CN104269385A (en) * 2014-10-21 2015-01-07 矽力杰半导体技术(杭州)有限公司 Packaging assembly and manufacturing method of packaging assembly
TWI637536B (en) * 2017-02-24 2018-10-01 矽品精密工業股份有限公司 Electronic package structure and the manufacture thereof
US10453820B2 (en) 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
US10867964B2 (en) 2018-02-07 2020-12-15 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
US11955457B2 (en) 2018-02-07 2024-04-09 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same

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