TW466767B - Method for manufacturing ultra-shallow junction metal oxide semiconductor transistor - Google Patents

Abstract

The present invention is related to a kind of method for forming ultra-shallow junction metal oxide semiconductor transistor and contains the following steps. At first, a semiconductor substrate on which the related positions of gate region and source/drain region have been defined is prepared. Then, an ion metal plasma (IMP) deposition method is used to deposit a silicon layer on the source/drain region and the upper surface of gate in a direction perpendicular to semiconductor substrate, in which the silicon layer is not deposited on the sidewall of gate region in this step. An LDD ion implantation is implanted inside the IMP silicon layer and is followed by performing a thermal oxidation process to partially oxidize the IMP silicon layer and the sidewall of gate so as to assure the separation between the gate and source/drain region, and to form the LDD region. After that, the spacer process is conducted. At the same time, the oxide layer on IMP silicon layer is also etched to expose the IMP silicon layer. Heavily doped ion implantation method is used to implant conductive impurities into semiconductor substrate. Self-aligned method is then used to form metal silicide layer on the source/drain region and the upper surface of gate.

Description

4 6 676 7 V. Description of the invention (1) Field of the invention: The present invention relates to the manufacturing process of semiconductors, in particular to a method for manufacturing a super shallow junction metal-oxide semiconductor transistor. Background of the Invention: With the advancement of integrated circuit technology, it has become a trend to have high-density components on wafers, and only in this way can it have full market competitiveness. However, when the component size develops from one micron to sub-micron or smaller, the% characteristics of the component have to face more severe tests, such as the hot carrier effect and the penetrating effect. The challenges that transistors (CMOS) must face as they are reduced in size. Second, parasitic resistances and capacitances must also be reduced in small-sized components. In addition, the limiting factor for small size components is the conductivity of the source / drain region and polycrystalline silicon. For example, the sheet resistance of the diffusion region is 25 ohms /-in 1 micron technology and 50 ohms /-in 0.5 micron technology. To this end, self-aligned metal silicide is formed in the source / drain region and The gate region is often used to solve the problem of resistance value. Not only that, it also provides a clean silicide-to-silicon interface, without the need for additional lithography and etching techniques. Because it is self-aligned. However, the process of forming a metal silicide will consume a part of the silicon layer of the substrate, which is not conducive to the formation of extremely shallow junction components. So generally need to have

V. Description of the invention (2) --------- Ϊ 1 Anomalous gas phase deposits deposited on the source / inverted region to provide a metal lithosphere layer are quite complex vapor deposition: the source region and the gate The traditional method of isolation is to use chemical &. Method to deposit an oxide layer before forming a silicon layer, and these procedures are one of the objectives of the present invention, and therefore will provide—easy-to-implement process steps. Purpose and summary of the invention: ϋ: t: m ::: Improves the problems caused by the formation of metal oxides on ultra-shallow junctions. The method for forming an extremely shallow junction metal-oxide semiconductor transistor of the present invention is a semiconductor substrate having a defined position in a polar region. Next, it is a method similar to sputtering, which is a method of electrolytic deposition.

Will not be deposited on the sidewalls of the idle region. One = sub-m step and not inside the silicon layer. The LDD ion implantation is then implanted on the side of the IMP :: :: ϊ: The oxidation process uses a part of the oxide layer and the gate, and the isolation of the second electrode area. In addition, in this step, "the conductive impurities in the IMP stone layer are introduced into the semiconductor substrate to constitute

4 6676 7 V. Description of the invention (3) Shallow junction. After that, the oxide layer deposited by the chemical vapor deposition method is: 积: 积: ΐ-anisotropic etching method is used to form the oxide layer on the sidewall of the gate electrode, and the oxide layer on the same layer Etching and exposing I MP Shi Xi, and then implanting conductive impurities into the semi-conductor by ion replacement implantation method. The refractory metal layer is then deposited, and a first annealing layer is formed in the source / drain region and the gate region. Then use the etched side; the metal I with two f f ΐ. Finally, another rapid thermal annealing interface is used to form a ti: ti: metal compound layer and activate conductive impurities to form a deeper cost-effective gold-oxygen semi-electric crystal structure. Detailed description of the invention: First, as shown in (2), a gate oxide layer u 0 is firstly formed on a semiconductor substrate 100 with a thickness between 50 and 300 angstroms by a high-temperature thermal oxidation process. It is deposited on the interlayer material doped with conductive impurities, such as a low pressure chemical vapor deposition (LPCVD) layer / f, in an indirect layer material, for example, to 3,000 angstroms. On the oxide layer 110, the typical thickness of the conductor layer 120 is about 1,000. Figure ―'Next coating-photoresist pattern on the resist pattern of the conductor layer 120.> The free electrode region 122, a step of engraving and then melting After the photoresist is not etched, i takes 1 minute and 1 minute, and uses the gate oxide layer 110 as an etch stop layer, and then removes the gate that is not covered by the polycrystalline silicon layer with the method of etch and wetting.

Page 6 46 676 7 V. Description of the invention (4) The electrode_oxide layer 11.0 is exposed to expose the source / on the semiconductor substrate 100; and the electrode region 1 2 4. Afterwards, please refer to FIG. 2, an ion metal plasma deposition method (Ion-Metal-Process; IMP for short) is then used to deposit the IMP stone layer 1 30 in the polycrystalline gate region 1 22 in a vertical semiconductor substrate direction and Source / impulse region 1 2 4 on. The ionic metal plasma deposition method is similar to a sputtering process, in which an ionized silicon material or a refractory metal material is used on the upper surface of a semiconductor substrate. In this step ', no silicon will be deposited on the sidewalls of the polycrystalline gate region 122.丨 The Mp Shixi layer is used as the metal silicide contact area. 1

I Immediately, an n-type or p-type conductive impurity is implanted into the semiconductor substrate 100 in an ion implantation direction as shown by the arrow to form an ion-doped region 14. In a preferred embodiment, η The type impurities may be phosphorus or arsenic ions, and the ρ type impurities may be BF 2 + or boron ions. The choice of conductive impurities depends on the element ηη M 0 S transistor or ρ M 0 S transistor. The energy and dose of the ion implantation are 1 to 30 keV and 1E13 to 5E15 / cm2. Please refer to FIG. 3, a high temperature thermal oxidation process of about 650 to 900 ° C is followed by an 'oxidation process to form A multiple-crystal oxide layer 1 35 is formed on the side wall of the multiple-crystal gate 122 and an IMP oxide layer 145 is formed on the source / drain region 124 and the upper surface of the crystalline gate 1 2 2. The oxidation process will consume a part of the multiple crystal Shi Xi layer and IMP Shi Xi layer. Therefore, using this step will ensure the separation of the complex gate 12 and source / drain region 1 24. In addition, the IMP Shi Xi layer can only be partially oxidized because the remaining The IMP stone layer 130 is used for the metal silicide layer.

Page 7 466767___ V. Description of the invention (5) Outside the ion-doped region 1400 in this step is an impurity diffusion source that can enter the semiconductor substrate 100 through the diffusion in this step to form an LDD region with a shallow junction of 140 people. An insulating layer 150, such as an oxide layer, is fully deposited in a pecVD manner. Of course, the insulating layer 150 may also be a silicon nitride layer. Please turn to Figure 4. The insulating layer 150 is then anisotropically etched so as to form a gap wall 150 on the side wall of the polycrystalline gate 1 2 2. The last names of the insulating layer and the I M P Shi Xi layer are used. The engraving selection stops on I μ p Shi Xi layer 1 3 0 than Qian engraving. Typically, the thickness of the gate barrier wall 150 is about 1000 to 2500 Angstroms. Immediately after that, a high dose of ion implantation was applied. The implantation energy and dose were 20 to 60 keV and -5E14 -1E16 / cm ^, which passed through the IMP stone layer to the semiconductor substrate 100. A metal silicide forms a metal, such as tungsten, titanium, or nickel, and is then deposited on the IMP stone layer 130 by chemical vapor deposition or sputtering. After the first rapid thermal annealing (RTP), it is refractory. The metal reacts with the IMP stone layer to form a metal silicide layer 160. Then, a wet etch such as NΗ40Η, H20, Η20 is performed, and then an unreacted metal layer is etched, for example, on the barrier wall 150. RTP annealing in the first stage is then applied to reduce the resistance value of the metal dream. The RTP annealing temperature in these two stages is higher than that in the first stage. This step also has the function of activating the implanted ions to form a deeper interface 170. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others that do not depart from the disclosure of the present invention

4 6 676 7 V. Description of the invention (6) Equivalent changes or modifications made under the spirit should all be included in the scope of the patent application described below. nil 4 6 676 7 Schematic illustration of the preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figure 1 shows a schematic cross-sectional view of a gate structure formed on a semiconductor substrate . Fig. 2 shows the cross-section of the ion-plasma deposition method in accordance with the method of the present invention to deposit an MP layer on the source / inverter region and the gate region and implant the ion region to form a doped region. FIG. 3 shows that a high temperature thermal oxidation process is performed according to the method of the present invention to form a polycrystalline oxide layer and an MP oxide layer to isolate a gate electrode and to deposit an I MP fragment layer in a source / drain region by an ion metal plasma deposition method. A schematic cross-sectional view of a gate region and a doped region formed by ion implantation. FIG. 4 is a schematic cross-sectional view of applying a non-isotropic etching method according to the present invention to form a spacer and exposing the remaining I SiO 2 layer, and then applying ion implantation in the source / drain region. Fig. 5 is a schematic cross-sectional view of a self-aligned metal silicide process performed by the method of the present invention to form a metal oxide layer.

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Claims (1)

46676 7 VI. Scope of patent application 1 · A method for making metal oxide semiconductors with extremely shallow junctions, the method includes at least the following steps: Provide a semiconductor substrate, the semiconductor substrate has formed a source / drain region and a complex thyristor On top of it; an IMP stone process (Ion_Metai_process; IMP for short) is used to deposit an IMP stone layer on the source / drain region and the upper surface of the complex gate; apply the first ion cloth Planted in all areas. The thermal oxidation process is used to oxidize the IM, the source / drain region, and the polycrystalline silicon gate ^ to form a 1-oxide layer on the side wall of the polycrystalline gate, the thermally oxidized surface, And the polycrystalline silicon layer on the polycrystalline gate and the polycrystalline silicon gate ^ consume a part of the IMP stone layer to form a dielectric layer in all areas; apply an anisotropic etching to Removing the IMP oxide layer; applying a second ion implantation through the remnant region on the sidewall of the complex gate; implanting the source / drain to form a metal layer in all regions; Apply the first thermal annealing process to the top surface of the drain region The polycrystalline gate into the metal silicide layer on the source / removal of the unreacted metal layer. & the upper surface; and, as described in the first patent application, the temperature is about 6 5.0 to 90 ot. ’Wherein the above-mentioned thermal oxidation process 466767_ VI. Application scope of patent 3. For the method of the first scope of patent application, wherein the above-mentioned dielectric layer is selected from a silicon dioxide layer or a silicon nitride layer. 4. The method according to item 1 of the patent application range, wherein the energy and dose of the first ion implantation described above are 1 to 30 k e V and 1 E 1 3 to 5E15 / cm2, respectively. 5. The method of item 1 in the scope of patent application, wherein the energy and dose of the second ion implantation mentioned above are 20 to 60 keV and 5E 1 4 to 1 E1 6 / cm 2 ° 6. If patent is applied The method of the first item, wherein the above-mentioned metal layer is selected from the group consisting of crane, titanium, Ming, and nickel. 7. The method according to item 1 of the scope of patent application, further comprising applying an RTP annealing process after the step of removing the metal layer to stabilize the above-mentioned metal silicide layer. Page 12