TW333713B - The semiconductor device and its producing method - Google Patents

The semiconductor device and its producing method

Info

Publication number
TW333713B
TW333713B TW086111765A TW86111765A TW333713B TW 333713 B TW333713 B TW 333713B TW 086111765 A TW086111765 A TW 086111765A TW 86111765 A TW86111765 A TW 86111765A TW 333713 B TW333713 B TW 333713B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
producing method
compose
trench
features
Prior art date
Application number
TW086111765A
Other languages
Chinese (zh)
Inventor
Hisarou Yoshimura
Original Assignee
Toshiba Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Co Ltd filed Critical Toshiba Co Ltd
Application granted granted Critical
Publication of TW333713B publication Critical patent/TW333713B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0895—Tunnel injectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure

Abstract

A semiconductor device, it is used in MIS structure of semiconductor device. Its features are: Install insulating layer between diffusion layers connected with trench, which is under the gate electrode to compose the device.
TW086111765A 1996-08-20 1997-08-15 The semiconductor device and its producing method TW333713B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21869096 1996-08-20

Publications (1)

Publication Number Publication Date
TW333713B true TW333713B (en) 1998-06-11

Family

ID=16723894

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086111765A TW333713B (en) 1996-08-20 1997-08-15 The semiconductor device and its producing method

Country Status (3)

Country Link
US (1) US6037605A (en)
KR (1) KR19980018751A (en)
TW (1) TW333713B (en)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000065719A (en) 1999-04-08 2000-11-15 김영환 Semiconductor device and fabricating method thereof
US20030235936A1 (en) * 1999-12-16 2003-12-25 Snyder John P. Schottky barrier CMOS device and method
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
WO2002043109A2 (en) * 2000-11-21 2002-05-30 Infineon Technologies Ag Method for producing a planar field effect transistor and a planar field effect transistor
US6566680B1 (en) * 2001-01-30 2003-05-20 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) tunneling junction transistor
CN100359701C (en) * 2001-08-10 2008-01-02 斯平内克半导体股份有限公司 Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate
US20060079059A1 (en) * 2001-08-10 2006-04-13 Snyder John P Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate
US6974737B2 (en) * 2002-05-16 2005-12-13 Spinnaker Semiconductor, Inc. Schottky barrier CMOS fabrication method
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US7176483B2 (en) * 2002-08-12 2007-02-13 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US7902029B2 (en) * 2002-08-12 2011-03-08 Acorn Technologies, Inc. Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
KR100498475B1 (en) * 2003-01-07 2005-07-01 삼성전자주식회사 Mosfet structure and method of fabricating the same
EP1683193A1 (en) * 2003-10-22 2006-07-26 Spinnaker Semiconductor, Inc. Dynamic schottky barrier mosfet device and method of manufacture
US20060091467A1 (en) * 2004-10-29 2006-05-04 Doyle Brian S Resonant tunneling device using metal oxide semiconductor processing
US8008701B2 (en) * 2004-12-22 2011-08-30 Giorgio Servalli Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling and device thus obtained
US7636552B2 (en) * 2005-04-08 2009-12-22 The Boeing Company Point-to-multipoint communications system and method
US7544576B2 (en) * 2005-07-29 2009-06-09 Freescale Semiconductor, Inc. Diffusion barrier for nickel silicides in a semiconductor fabrication process
DE102006030268B4 (en) * 2006-06-30 2008-12-18 Advanced Micro Devices Inc., Sunnyvale Method for forming a semiconductor structure, in particular a FET
KR100771552B1 (en) * 2006-10-31 2007-10-31 주식회사 하이닉스반도체 Mos transistor depressing short channel effect and method of fabricating the same
US8648426B2 (en) * 2010-12-17 2014-02-11 Seagate Technology Llc Tunneling transistors
US20120261740A1 (en) * 2011-04-13 2012-10-18 Peking University Flash memory and method for fabricating the same
US9536945B1 (en) * 2015-07-30 2017-01-03 International Business Machines Corporation MOSFET with ultra low drain leakage
US9991385B2 (en) * 2015-09-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Enhanced volume control by recess profile control
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
DE112017005855T5 (en) 2016-11-18 2019-08-01 Acorn Technologies, Inc. Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713765A (en) * 1980-06-30 1982-01-23 Toshiba Corp Insulated gate type field effect transistor and manufacture thereof
US5834793A (en) * 1985-12-27 1998-11-10 Kabushiki Kaisha Toshiba Semiconductor devices
JPH08274198A (en) * 1995-03-29 1996-10-18 Lg Semicon Co Ltd Eeprom cell and its preparation

Also Published As

Publication number Publication date
KR19980018751A (en) 1998-06-05
US6037605A (en) 2000-03-14

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees