WO2002043109A2 - Method for producing a planar field effect transistor and a planar field effect transistor - Google Patents

Method for producing a planar field effect transistor and a planar field effect transistor Download PDF

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Publication number
WO2002043109A2
WO2002043109A2 PCT/DE2001/004358 DE0104358W WO0243109A2 WO 2002043109 A2 WO2002043109 A2 WO 2002043109A2 DE 0104358 W DE0104358 W DE 0104358W WO 0243109 A2 WO0243109 A2 WO 0243109A2
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Prior art keywords
region
barrier layer
effect transistor
insulating layer
field effect
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PCT/DE2001/004358
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German (de)
French (fr)
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WO2002043109A3 (en
Inventor
Franz Hofmann
Lothar Risch
Wolfgang Roesner
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Infineon Technologies Ag
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Publication of WO2002043109A3 publication Critical patent/WO2002043109A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0895—Tunnel injectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Definitions

  • the invention relates to a method for producing a planar field effect transistor and a planar field effect transistor.
  • a field effect transistor is known from [1].
  • the field effect transistor from [1] is a vertical field effect transistor in which a gate region is arranged perpendicular to the direction of the electron flow between a source region and a drain region.
  • the field effect transistor from [1] has a source region, a drain region, a gate region and a channel region, all regions being made from polysilicon.
  • a first electrically insulating layer made of nitride (first tunnel barrier) is formed between the source region and the channel region.
  • a second electrically insulating layer made of nitride (second tunnel barrier) is formed between the drain region and the channel region.
  • the first electrically insulating layer and the second electrically insulating layer each have a thickness of approximately 2 nm.
  • the channel region in particular is made from monocrystalline silicon.
  • [3] describes a field effect transistor and a manufacturing method for manufacturing the
  • [4] also describes a planar field effect transistor with a barrier layer, the barrier layer between the source region and the channel region and / or between the drain region and the channel region being designed such that no tunneling of electrical charge carriers through the barrier layer into the Substrate is possible.
  • the invention is therefore based on the problem of specifying a field effect transistor, each having an electrically insulating layer between the source region and the channel region or the drain region and the channel region, in which the channel region can be produced from monocrystalline silicon.
  • Forming a gate region on the insulating layer • Form at least one spacer on the insulating
  • barrier layer between the source region and the channel region and / or between the drain region and the channel region in such a way that essentially no diffusion of the doping agents located in the source region and the drain region into the channel region can take place, but it is possible to tunnel electrical charge carriers through the barrier layer into the channel region and into the substrate.
  • planar field effect transistor with ⁇ an electrically conductive substrate, ⁇ a drain region, ® a source region,
  • a channel region between the drain region and the source region "a gate region on the insulating layer, at least one spacer being arranged on the insulating layer, ® an insulating layer between the gate region and the substrate” of a barrier layer next to the gate area and / or under a part of the gate area, ⁇ wherein the barrier layer between the source area and the channel area and / or between the drain area and the channel area is designed such that there is essentially no diffusion of the doping atoms located in the source region and the drain region can take place in the channel region, but tunneling electrical charge carriers through the barrier layer into the channel area and into the substrate is possible.
  • planar field effect transistor is clearly a modification of a known planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in which a thin barrier layer made of a dielectric material is arranged between the source region or drain region and the channel region lying in between ,
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the mobility of the electrical charge carriers in the channel region is improved by up to a factor of 100 and more compared to a channel region which is formed from polycrystalline silicon.
  • barrier layer thickness is understood to mean a barrier layer thickness of preferably less than approximately 2 n, preferably of less than approximately
  • the barrier layer additionally ensures that the doping atoms located in the source and drain regions do not penetrate into the intermediate channel region of the substrate due to the steps required for doping at high temperature diffuse. Such diffusion into the channel region would lead to the doping profiles running between the channel region and the source region or drain region and therefore to a deterioration in the controllability of the channel region which is essential for the switching capability of the transistor.
  • planar arrangement of the planar field-effect transistor according to the invention enables increased flexibility with regard to the structure of the field-effect transistor.
  • the barrier layer As described in detail below, it is possible, depending on the etching method used, the barrier layer
  • the planar field effect transistor according to the invention Compared to the vertical field effect transistor with barrier layers described in [1], in which it is necessary to build up each layer of the transistor by means of a separate process step, it is possible, for example, in the planar field effect transistor according to the invention, to have several components of the transistor, such as barrier layers on both Form sides of the insulating layer and the source region and the drain region on both sides of the insulating layer simultaneously, for example by a single deposition process. As a result, a high degree of uniformity with regard to the thickness and the exact composition of the barrier layer according to the invention and of the source region and the drain region is ensured compared to the prior art.
  • the substrate is etched away isotropically next to and partly below the insulating layer before the barrier layer is formed.
  • the substrate is etched away isotropically next to and partly below the insulating layer before the barrier layer is formed.
  • the barrier layer is preferably formed in a thickness of 1 nm or less.
  • the spacer can be formed from SiO 2 , for example by means of a TEOS, silane oxide, LTO, SACVD, HTO, PECVD or a Dep. / Etch deposition process.
  • the spacer is formed in a thickness of at most 50 nm, preferably in a thickness of at most 10 nm.
  • Barrier layer formed from a dielectric material, preferably from an oxynitride, for example an oxynitride described in [2].
  • Figure 2 is a schematic representation of a second embodiment of the invention in the finished state
  • Figure 3 shows another embodiment of the invention in the finished state.
  • Fig.la to Fig.lc are to be understood as the timing of a manufacturing process of a planar field effect transistor according to the invention.
  • an insulating layer 100 is first formed on a substrate 103.
  • the substrate 103 preferably consists of a material suitable for the construction of a planar field effect transistor, preferably of monocrystalline silicon.
  • the insulating layer 100 also referred to as gate oxide (GOX), consists of an electrically insulating material, such as silicon dioxide, and is formed on the substrate 103, for example, by a process known for the construction of such planar field-effect transistors, such as, for example, by thermal oxidation ,
  • GOX gate oxide
  • the gate region 101 is then formed as a layer of conductive material, such as polysilicon, on the insulating layer 100.
  • the silicon used for this purpose is doped with phosphorus according to this exemplary embodiment.
  • the gate region 101 is formed on the insulating layer 100 in a known manner with the aid of photolithography and anisotropic reactive ion etching.
  • the gate region 101 is formed on the insulating layer 100 in accordance with this exemplary embodiment in such a way that a layer of silicon dioxide is applied to the substrate.
  • a layer of 10 polysilicon is applied to the layer of silicon dioxide, which later forms the insulating layer 100, preferably by means of a deposition process (CVD process) from the gas phase, preferably by means of a low-pressure CVD process.
  • CVD process deposition process
  • the polysilicon layer is doped with L5 phosphorus atoms.
  • TEOS tetraethyl ortho-silicate
  • the later gate area is structured by means of photolithography.
  • the TEOS layer and the layer made of -5 polysilicon are then etched such that an area remains above the insulating layer 100, so that in each case laterally next to the parts of the TEOS layer and the layer made of polysilicon not etched away above the insulating layer 100 Space is formed for spacers 30 formed in further steps.
  • a further TEOS layer is applied over the entire area and the spacers 102 are formed by etching the TEOS layer and the exposed parts of the insulating layer 100 anisotropically over the entire area down to the substrate 103, so that only the spacers 102 remain ,
  • the completed gate complex 100-102 can be seen in Fig.la. This is formed by the insulating layer 100, the gate region 101 and the spacer 102. 5
  • the substrate 103 is etched away isotropically on both sides of this gate complex 100-102, so that an area is located next to as well as under part of the L0 gate complex 100-102 of the substrate 103 is hollowed out.
  • the substrate 103 is isotropic, i.e. Not
  • L5 is anisotropically etched away. In this way it is ensured that there is an undercutting below a part of the insulating layer 100.
  • These etched-away recesses 110 on both sides of the gate complex 100-102 are ultimately called the source region and the drain region
  • a thin, dielectric layer 104 is then applied to the surface of the substrate 103 resulting from the etching away of the substrate 103.
  • This thin, dielectric layer 104 serves as the barrier layer mentioned at the outset, which essentially does not allow the doping atoms located in the source region and the drain region to diffuse into the surrounding substrate 103, and particularly into the channel region 108 lying between them. which barrier layer, however, allows electrical charge carriers to tunnel through themselves.
  • a thermal oxide, a nitride, or a combination of an oxide and a nitride can be used for the barrier layer 104.
  • the entire course of the barrier layer 104 should be formed in a thickness 5 of 2 nm or less, preferably even only in a thickness of 1 nm or less.
  • barrier layer 104 In the case of the barrier layer 104, such a thickness is generally ensured that the charge carriers tunnel out
  • the 10 can take place from the source region and from the drain region, but no diffusion of the dopants from the source region and / or drain region into the substrate 103 or into the channel region lying between the source region and the drain region 108 into it.
  • Fig.lc shows the planar field effect transistor according to this embodiment of the invention in the finished state.
  • FIG. 1c shows two regions 105, 109 which represent the source region 105 and the drain region 109.
  • the polysilicon layer heavily doped with arsenic atoms is then leveled and thus prepared for the next process step.
  • a further electrically insulating layer 106 is deposited above the entire planar field effect transistor. •
  • the further insulating layer 106 may be formed of BPSG (boron
  • FIGS. 1 to C. L5 results in a field-effect transistor 111 as shown in FIG. 1 c, in which the barrier layer 104 is located both next to and under part of the insulating layer 100 is formed.
  • Fig.2 shows as another
  • Embodiment a planar field effect transistor 212 in the finished state, in which the barrier layer 204 only under part of the insulating layer 200, i.e. is not also formed next to the insulating layer 200.
  • the gate complex consisting of the insulating layer 200, the gate region 201 and the spacer 202, is constructed in an analogous manner to that described for Fig.la above. Also
  • the material for the barrier layer 204 is deposited in an analogous manner to that described for Fig.la above.
  • the planar field-effect transistor 212> 5 shown in FIG. 2 has two barriers 204 as well as a source region 205 and a drain region 206 below the insulating layer 200 between the insulating layer 200 and one planar exposed surface 207.
  • One of the two barriers 204 is arranged between the source region 205 and the channel region 203 and between the drain region 206 and the channel region 203.
  • the barriers 204 are generated by means of a thermal oxidation, so that the barriers 204 automatically arise in the form shown in FIG. 2 because the planar exposed surface 207 already consists of the buried oxide of the SOI starting material.
  • This procedure clearly corresponds to the formation of a starting material for an SOI complex (Silicon On Insulator).
  • Field effect transistor 212 has a barrier layer 204 only between the source region 206 and the channel region 203 and between the drain region 205 and the channel region 203.
  • the substrate 209 consists of two divided sections 207 and 208.
  • the substrate region 208 consists of a conductive material, such as silicon
  • the substrate section 207 preferably consists of a non-conductive material, for example an oxide.
  • the nature of the substrate section 207 as a non-conductive material prevents doping atoms in the source region 205 or the drain region 206 from diffusing into the underlying material of the substrate 209 and thus contaminating the channel region 203. In contrast, a diffusion of the doping atoms in the source region 205 or the drain region 206 into the channel region 203 lying in between would be very possible without a barrier layer 204, which is why this
  • Barrier layer 204 is located between the source region 206 or the drain region 205 and the intermediate channel region 203.
  • Substrate 209 is carried out in a simple manner before the gate complex 200-202 is built.
  • the structure is based on a silicon layer 208, on which a non-conductive insulating layer 207 is applied and finally by applying a third layer of silicon on the insulating layer 207. After etching away, this third layer then forms the channel region 203.
  • An electrically insulating layer is applied to the source region 205, the gate complex 200-202 and the drain region 206
  • Layer 210 preferably made of silicon dioxide, is applied, in which, in a further step, contact holes 211 for conductor tracks are etched, which enable contact between the metallic conductor track and the source region or drain region 109 during the subsequent metallization of the planar field effect transistor.
  • FIG. 3 shows a further finished, planar field effect transistor which, based on the method according to the invention, starts from that which has not yet been completed
  • the barrier layer 304 is direct on the Substrate 307 is formed without the substrate 307 being etched away in advance.
  • the barrier layer 304 in FIG. 3 is therefore formed exclusively next to, ie neither exclusively under (cf. FIG. 2) nor under and next to (cf. FIG. 1c) the insulating layer 300.
  • the source region 306 or drain region 305 of the field effect transistor 309 in FIG. 3 can therefore be deposited directly on the barrier layer without the need for a further etching process in advance.
  • Embodiment of the planar field effect transistor 309 according to the invention does not have a channel region which, in contrast to the embodiments in FIG. 1c and in FIG. 2, borders directly on the barrier layer 304. It can be seen from FIG. 3 that the channel region 308 is arranged on both sides at a distance 303 from the respective barrier layers 304. The distance 303 results from the thickness of the spacer 302 that is formed on the insulating layer 300. The regions 303 below the insulating layer 300 lie outside the field generated by the gate region 301, so that when the gate voltage is applied, the conductivity of the regions 303 compared to that of the channel region 308 is directly in the field generated by the gate region 301 is less.
  • controllability of the planar field effect transistor in FIG. 3 depends on the distance 303, a larger distance 303 leading to a deteriorated controllability of the planar field effect transistor 309.
  • the non-conductive spacer 302 formed on the insulating layer 300 is formed as thin as possible by appropriate setting of the deposition method used to form this spacer.
  • the spacer is preferably formed with a thickness of at most 10 nm, so that the distances 303 are small enough to allow diffusion of charge carriers through the less highly conductive regions 303 of the substrate 307 on both sides of the channel region 308 and therefore good controllability of the planar region To ensure field effect transistor.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention relates to a planar field effect transistor comprising a barrier layer that lies adjacent to and/or below part of the gate region. Said barrier layer is configured between the source region and the channel region and/or between the drain region and the channel region in such a way that there is practically no diffusion of the doping atoms from the source region and the drain region into the channel region, but that electric charge carriers can tunnel through the barrier layer.

Description

Beschreibungdescription
Verfahren zum Herstellen eines planaren Feldeffekttransistors und planarer FeldeffekttransistorMethod of manufacturing a planar field effect transistor and planar field effect transistor
Die Erfindung betrifft ein Verfahren zum Herstellen eines planaren Feldeffekttransistors und einen planaren Feldeffekttransistor .The invention relates to a method for producing a planar field effect transistor and a planar field effect transistor.
Ein Feldeffekttransistor ist aus [1] bekannt. Der Feldeffekttransistor aus [1] ist ein vertikaler Feldeffekttransistor, bei dem ein Gate-Bereich senkrecht zur Richtung des Elektronenflusses zwischen einem Source-Bereich und einem Drain-Bereich angeordnet ist. Der Feldeffekttransistor aus [1] weist einen Source-Bereich, einen Drain-Bereich, einen Gate-Bereich sowie einen Kanalbereich auf, wobei alle Bereiche aus Polysilizium hergestellt sind. Zwischen dem Source-Bereich und dem Kanalbereich ist eine erste elektrisch isolierende Schicht aus Nitrid (erste Tunnelbarriere) ausgebildet. Ferner ist zwischen dem Drain-Bereich und dem Kanalbereich eine zweite elektrisch isolierende Schicht aus Nitrid (zweite Tunnelbarriere) ausgebildet. Die erste elektrisch isolierende Schicht und die zweite elektrisch isolierende Schicht weisen jeweils eine Dicke von ungefähr 2 nm auf.A field effect transistor is known from [1]. The field effect transistor from [1] is a vertical field effect transistor in which a gate region is arranged perpendicular to the direction of the electron flow between a source region and a drain region. The field effect transistor from [1] has a source region, a drain region, a gate region and a channel region, all regions being made from polysilicon. A first electrically insulating layer made of nitride (first tunnel barrier) is formed between the source region and the channel region. Furthermore, a second electrically insulating layer made of nitride (second tunnel barrier) is formed between the drain region and the channel region. The first electrically insulating layer and the second electrically insulating layer each have a thickness of approximately 2 nm.
Häufig ist es insbesondere hinsichtlich der elektrischen Eigenschaften des Kanalbereichs wünschenswert, dass insbesondere der Kanalbereich aus monokristallinem Silizium hergestellt wird.With regard to the electrical properties of the channel region, it is frequently desirable that the channel region in particular is made from monocrystalline silicon.
Die Ausbildung eines Kanalbereichs aus monokristallinem Silizium ist bei dem Herstellungsverfahren aus [1] nicht möglich, insbesondere da die Nitridschichten in dem Herstellungsverfahren aus [1] gemeinsam mit polykristallinem Silizium hergestellt werden können. Weiterhin ist eine Übersicht über Oxynitride in [2] zu finden.It is not possible to form a channel region from monocrystalline silicon in the production process from [1], in particular since the nitride layers in the production process from [1] can be produced together with polycrystalline silicon. An overview of oxynitrides can also be found in [2].
[3] beschreibt einen Feldeffekttransistor sowie ein Herstellungsverfahren zum Herstellen des[3] describes a field effect transistor and a manufacturing method for manufacturing the
Feldeffekttransistors, wobei die Source-/Drain-Bereiche als dotierte, monokristalline Siliziumbereiche ausgestaltet sind. Das Herstellungsverfahren gemäß [3] ist relativ aufwendig und somit teuer.Field-effect transistor, the source / drain regions being designed as doped, monocrystalline silicon regions. The manufacturing process according to [3] is relatively complex and therefore expensive.
In [4] ist ferner ein planarer Feldeffekttransistor beschrieben mit einer Barriereschicht, wobei die Barriereschicht zwischen dem Source-Bereich und dem Kanalbereich und/oder zwischen dem Drain-Bereich und dem Kanalbereich derart ausgebildet ist, dass kein Tunneln elektrischer Ladungsträger durch die Barriereschicht in das Substrat möglich ist.[4] also describes a planar field effect transistor with a barrier layer, the barrier layer between the source region and the channel region and / or between the drain region and the channel region being designed such that no tunneling of electrical charge carriers through the barrier layer into the Substrate is possible.
Somit liegt der Erfindung das Problem zugrunde, einen Feldeffekttransistor mit jeweils einer elektrisch isolierenden Schicht zwischen dem Source-Bereich und dem Kanalbereich bzw. dem Drain-Bereich und dem Kanalbereich anzugeben, bei dem der Kanalbereich aus monokristallinem Silizium hergestellt sein kann.The invention is therefore based on the problem of specifying a field effect transistor, each having an electrically insulating layer between the source region and the channel region or the drain region and the channel region, in which the channel region can be produced from monocrystalline silicon.
Das Problem wird gelöst durch ein Verfahrens zum Herstellen eines planaren Feldeffekttransistors und durch einen planaren Feldeffekttransistor mit den Merkmalen gemäß den unabhängigen Patentansprüchen .The problem is solved by a method for producing a planar field-effect transistor and by a planar field-effect transistor with the features according to the independent claims.
Ein Verfahren zum Herstellen eines planaren Feldeffekttransistors weist folgende Schritte auf:A method for producing a planar field effect transistor has the following steps:
• Bilden einer isolierenden Schicht auf einem Substrat;Forming an insulating layer on a substrate;
• Bilden eines Gate-Bereichs auf der isolierenden Schicht; • Bilden mindestens eines Spacers auf der isolierendenForming a gate region on the insulating layer; • Form at least one spacer on the insulating
Schicht; • Bilden einer Barriereschicht neben der isolierenden Schicht und/oder unter einem Teil der isolierenden Schicht;Layer; Forming a barrier layer next to the insulating layer and / or under part of the insulating layer;
• Abscheiden eines Source-Bereichs auf der einen Seite des Gate-Bereichs und Abscheiden eines Drain-Bereichs auf der anderen Seite des Gate-Bereichs und eines Kanalbereichs unterhalb der isolierenden Schicht zwischen dem Source-Bereich und dem Drain-Bereich; und• depositing a source region on one side of the gate region and depositing a drain region on the other side of the gate region and a channel region below the insulating layer between the source region and the drain region; and
• Bilden einer Barriereschicht zwischen dem Source-Bereich und dem Kanalbereich und/oder zwischen dem Drain-Bereich und dem Kanalbereich derart, dass im Wesentlichen kein Diffundieren der sich in dem Source-Bereich und dem Drain-Bereich befindlichen Dotier-Ato e in den Kanalbereich erfolgen kann, jedoch ein Tunneln elektrischer Ladungsträger durch die Barriereschicht in den Kanalbereich und in das Substrat möglich ist.Forming a barrier layer between the source region and the channel region and / or between the drain region and the channel region in such a way that essentially no diffusion of the doping agents located in the source region and the drain region into the channel region can take place, but it is possible to tunnel electrical charge carriers through the barrier layer into the channel region and into the substrate.
Das Problem wird ferner gelöst durch einen planaren Feldeffekttransistor mit β einem elektrisch leitenden Substrat, Ö einem Drain-Bereich, ® einem Source-Bereich,The problem is further solved by a planar field effect transistor with β an electrically conductive substrate, Ö a drain region, ® a source region,
• einem Kanalbereich zwischen dem Drain-Bereich und dem Source-Bereich, « einem Gate-Bereich auf der isolierenden Schicht, wobei auf der isolierenden Schicht mindestens ein Spacer angeordnet ist, ® einer isolierenden Schicht zwischen dem Gate-Bereich und dem Substrat « einer Barriereschicht neben dem Gate-Bereich und/oder unter einem Teil des Gate-Bereichs, β wobei die Barriereschicht zwischen dem Source-Bereich und dem Kanalbereich und/oder zwischen dem Drain-Bereich und dem Kanalbereich derart ausgestaltet ist, dass im wesentlichen kein Diffundieren der sich in dem Source- Bereich und dem Drain-Bereich befindlichen Dotieratome in den Kanalbereich erfolgen kann, jedoch ein Tunneln elektrischer Ladungsträger durch die Barriereschicht in den Kanalbereich und in das Substrat möglich ist.• a channel region between the drain region and the source region, "a gate region on the insulating layer, at least one spacer being arranged on the insulating layer, ® an insulating layer between the gate region and the substrate" of a barrier layer next to the gate area and / or under a part of the gate area, β wherein the barrier layer between the source area and the channel area and / or between the drain area and the channel area is designed such that there is essentially no diffusion of the doping atoms located in the source region and the drain region can take place in the channel region, but tunneling electrical charge carriers through the barrier layer into the channel area and into the substrate is possible.
Bei dem planaren Feldeffekttransistor handelt es sich anschaulich um eine Modifikation eines bekannten planaren MOSFET (Metal Oxide Semiconductor Field Effect Transistor) , bei dem eine dünne Barriereschicht aus einem dielektrischen Material zwischen dem Source-Bereich bzw. Drain-Bereich und dem dazwischen liegenden Kanalbereich angeordnet ist.The planar field effect transistor is clearly a modification of a known planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in which a thin barrier layer made of a dielectric material is arranged between the source region or drain region and the channel region lying in between ,
Insbesondere aufgrund des Vorsehens eines planaren Feldeffekttransistors und der entsprechenden Vorgehensweise beim Herstellen des planaren Feldeffekttransistors wird es nunmehr erstmals möglich, den Kanalbereich aus monokristallinem Silizium herzustellen, was -erheblicheIn particular due to the provision of a planar field-effect transistor and the corresponding procedure for producing the planar field-effect transistor, it is now possible for the first time to produce the channel region from monocrystalline silicon, which is significant
Vorteile in den elektrischen Eigenschaften mit sich bringt. Insbesondere durch die Verwendung von monokristallinem Silizium in dem Kanalbereich wird die Beweglichkeit der elektrischen Ladungsträger in dem Kanalbereich im Vergleich zu einem Kanalbereich, der aus polykristallinem Silizium gebildet wird, um bis zu einem Faktor 100 und mehr verbessert .Brings advantages in electrical properties. In particular, by using monocrystalline silicon in the channel region, the mobility of the electrical charge carriers in the channel region is improved by up to a factor of 100 and more compared to a channel region which is formed from polycrystalline silicon.
Gemäß einer Ausgestaltung der Erfindung ist es somit vorgesehen, den Kanalbereich aus monokristallinem Silizium herzustellen.According to one embodiment of the invention, it is therefore provided to produce the channel region from monocrystalline silicon.
Im Rahmen der Erfindung ist unter dem Ausdruck "dünn" eine Barriereschichtdicke von vorzugsweise weniger als ungefähr 2 n zu verstehen, vorzugsweise von weniger als ungefährIn the context of the invention, the term “thin” is understood to mean a barrier layer thickness of preferably less than approximately 2 n, preferably of less than approximately
1 nm.1 nm.
Gleichzeitig wird zusätzlich durch die Barriereschicht erreicht, dass die sich in den Source- und Drain-Bereichen befindlichen Dotieratome nicht aufgrund der zum Dotieren notwendigen Schritte bei hoher Temperatur in den dazwischenliegenden Kanalbereich des Substrats hinein diffundieren. Ein solches Diffundieren in den Kanalbereich würde zu einem Verlaufen der Dotierprofile zwischen dem Kanalbereich und dem Source-Bereich bzw. Drain-Bereich und daher zu einer Verschlechterung der Steuerbarkeit des für die Schaltfähigkeit des Transistors unerlässlichen Kanalbereichs führen.At the same time, the barrier layer additionally ensures that the doping atoms located in the source and drain regions do not penetrate into the intermediate channel region of the substrate due to the steps required for doping at high temperature diffuse. Such diffusion into the channel region would lead to the doping profiles running between the channel region and the source region or drain region and therefore to a deterioration in the controllability of the channel region which is essential for the switching capability of the transistor.
Des weiteren ermöglicht die planare Anordnung des erfindungsgemäßen planaren Feldeffekttransistors eine erhöhte Flexibilität hinsichtlich des Aufbaus des Feldeffekttransistors .Furthermore, the planar arrangement of the planar field-effect transistor according to the invention enables increased flexibility with regard to the structure of the field-effect transistor.
Beispielsweise ist es, wie untenstehend ausführlich beschrieben, möglich, je nach verwendetem Ätzverfahren die BarriereschichtFor example, as described in detail below, it is possible, depending on the etching method used, the barrier layer
® nur neben der isolierenden Schicht des Gate-Komplexes, ® nur unter der isolierenden Schicht des Gate-Komplexes oder ® neben und unter der isolierenden Schicht des Gate- Komplexes auszubilden.® only next to the insulating layer of the gate complex, ® only under the insulating layer of the gate complex or ® next to and under the insulating layer of the gate complex.
Gegenüber dem in [1] beschriebenen, vertikalen Feldeffekttransistor mit Barriereschichten, bei dem es erforderlich ist, jede Schicht des Transistors mittels eines getrennten Verfahrensschrittes aufzubauen, ist es beispielsweise bei dem erfindungsgemäßen planaren Feldeffekttransistor möglich, mehrere Komponenten des Transistors, wie zum Beispiel Barriereschichten auf beiden Seiten der Isolierschicht sowie den Source-Bereich und den Drain-Bereich auf beiden Seiten der Isolierschicht gleichzeitig, beispielsweise durch ein einziges Abscheideverfahren, zu bilden. Dadurch wird gegenüber dem Stand der Technik ein hohes Maß an Gleichmäßigkeit hinsichtlich der Dicke und der genauen Zusammensetzung der erfindungsgemäßen Barriereschicht sowie des Source-Bereichs und des Drain-Bereichs gewährleistet. Gemäß einer Weiterbildung der Erfindung ist es für den Fall, dass die Barriereschicht neben und unter einem Teil der isolierenden Schicht gebildet werden soll, vorgesehen, das Substrat vor dem Bilden der Barriereschicht neben und teilweise unter der isolierenden Schicht isotrop wegzuätzen.Compared to the vertical field effect transistor with barrier layers described in [1], in which it is necessary to build up each layer of the transistor by means of a separate process step, it is possible, for example, in the planar field effect transistor according to the invention, to have several components of the transistor, such as barrier layers on both Form sides of the insulating layer and the source region and the drain region on both sides of the insulating layer simultaneously, for example by a single deposition process. As a result, a high degree of uniformity with regard to the thickness and the exact composition of the barrier layer according to the invention and of the source region and the drain region is ensured compared to the prior art. According to a further development of the invention, in the event that the barrier layer is to be formed next to and below part of the insulating layer, it is provided that the substrate is etched away isotropically next to and partly below the insulating layer before the barrier layer is formed.
Gemäß einer anderen Weiterbildung der Erfindung ist es für den Fall, dass die Barriereschicht nur unter einem Teil der isolierenden Schicht gebildet werden soll, vorgesehen, das Substrat vor dem Bilden der Barriereschicht neben und teilweise unter der isolierende Schicht isotrop wegzuätzen.According to another development of the invention, in the event that the barrier layer is to be formed only under part of the insulating layer, it is provided that the substrate is etched away isotropically next to and partly below the insulating layer before the barrier layer is formed.
Die Barriereschicht wird vorzugsweise in einer Dicke von 1 nm oder weniger gebildet wird.The barrier layer is preferably formed in a thickness of 1 nm or less.
Der Spacer kann aus Siθ2 gebildet werden, beispielsweise mittels eines TEOS-, Silanoxid-, LTO-, SACVD- , HTO-, PECVD- oder eines Dep . /Etch-Abscheideverfahrens .The spacer can be formed from SiO 2 , for example by means of a TEOS, silane oxide, LTO, SACVD, HTO, PECVD or a Dep. / Etch deposition process.
Gemäß einer Ausgestaltung der Erfindung wird der Spacer in einer Dicke von höchstens 50 nm, vorzugsweise in einer Dicke von höchstens 10 nm, gebildet.According to one embodiment of the invention, the spacer is formed in a thickness of at most 50 nm, preferably in a thickness of at most 10 nm.
Gemäß einer Ausgestaltung der Erfindung wird dieAccording to one embodiment of the invention
Barriereschicht aus einem dielektrischen Material gebildet, vorzugsweise aus einem Oxynitrid, beispielsweise einem in [2] beschriebenen Oxynitrid.Barrier layer formed from a dielectric material, preferably from an oxynitride, for example an oxynitride described in [2].
Gemäß einer weiteren Ausgestaltung der Erfindung wird dieAccording to a further embodiment of the invention, the
Barriereschicht aus SiÜ2 oder Si3N4 gebildet.Barrier layer made of SiÜ2 or Si 3 N4.
Ausführungsbeispiele der Erfindung sind in den Figuren dargestellt und werden im Weiteren näher erläutert.Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.
Es zeigen Figuren la bis lc einen Zeitablauf einesShow it Figures la to lc a timing of one
Herstellungsverfahrens gemäß einem ersten Ausführungsbeispiel der Erfindung,Manufacturing method according to a first embodiment of the invention,
Figur 2 eine schematische Darstellung eines zweiten Ausführungsbeispiels der Erfindung in fertiggestelltem Zustand, undFigure 2 is a schematic representation of a second embodiment of the invention in the finished state, and
Figur 3 ein weiteres Ausführungsbeispiel der Erfindung in fertiggestelltem Zustand.Figure 3 shows another embodiment of the invention in the finished state.
Fig.la bis Fig.lc sind als Zeitablauf eines Herstellungsverfahrens eines erfindungsgemäßen planaren Feldeffekttransistors zu verstehen.Fig.la to Fig.lc are to be understood as the timing of a manufacturing process of a planar field effect transistor according to the invention.
Wie in Fig.la gezeigt ist, wird zunächst auf einem Substrat 103 eine isolierende Schicht 100 gebildet.As shown in FIG. 1, an insulating layer 100 is first formed on a substrate 103.
Das Substrat 103 besteht vorzugsweise aus einem für den Aufbau eines planaren Feldeffekttransistors geeigneten Material, bevorzugt aus monokristallinem Silizium.The substrate 103 preferably consists of a material suitable for the construction of a planar field effect transistor, preferably of monocrystalline silicon.
Die isolierende Schicht 100, auch als Gate-Oxid (GOX) bezeichnet, besteht aus einem elektrisch isolierenden Material, wie beispielsweise Siliziumdioxid, und wird auf dem Substrat 103 beispielsweise durch einen für den Aufbau solcher planaren Feldeffekttransistoren bekannten Vorgang, wie beispielsweise durch thermische Oxidation gebildet.The insulating layer 100, also referred to as gate oxide (GOX), consists of an electrically insulating material, such as silicon dioxide, and is formed on the substrate 103, for example, by a process known for the construction of such planar field-effect transistors, such as, for example, by thermal oxidation ,
Sodann wird der Gate-Bereich 101 als eine Schicht leitfähigen Materials, wie beispielsweise Polysiliziu auf der isolierenden Schicht 100 gebildet. Das für diesen Zweck verwendete Silizium ist gemäß diesem Ausführungsbeispiel mit Phosphor dotiert. Das Bilden des Gate-Bereichs 101 auf der isolierenden Schicht 100 erfolgt in bekannter Weise mit Hilfe von Photolithografie und anisotropem Reaktiven Ionenätzen.The gate region 101 is then formed as a layer of conductive material, such as polysilicon, on the insulating layer 100. The silicon used for this purpose is doped with phosphorus according to this exemplary embodiment. The gate region 101 is formed on the insulating layer 100 in a known manner with the aid of photolithography and anisotropic reactive ion etching.
5 Das Bilden des Gate-Bereichs 101 auf der isolierenden Schicht 100 erfolgt gemäß diesem Ausführungsbeispiel derart, dass eine Schicht aus Siliziumdioxid auf dem Substrat aufgebracht wird. Auf die Schicht aus Siliziumdioxid, die später die isolierende Schicht 100 bildet, wird eine Schicht aus 10 Polysilizium aufgebracht, vorzugsweise mittels eines Abscheideverfahrens (CVD-Verfahrens) aus der Gasphase, vorzugsweise mittels eines Niederdruck-CVD-Verfahrens .5 The gate region 101 is formed on the insulating layer 100 in accordance with this exemplary embodiment in such a way that a layer of silicon dioxide is applied to the substrate. A layer of 10 polysilicon is applied to the layer of silicon dioxide, which later forms the insulating layer 100, preferably by means of a deposition process (CVD process) from the gas phase, preferably by means of a low-pressure CVD process.
In einem weiteren Schritt wird die Polysiliziumschicht mit L5 Phosphoratomen dotiert.In a further step, the polysilicon layer is doped with L5 phosphorus atoms.
Ferner wird auf die Schicht aus Polysilizium in einem weiteren Prozessschritt eine TEOS-Schicht aufgebracht (TEOS: Tetra-Ethyl-Ortho-Silicate) . .0In a further process step, a TEOS layer (TEOS: tetraethyl ortho-silicate) is also applied to the layer of polysilicon. .0
Anschließend wird mittels Fotolithographie der spätere Gate- Bereich strukturiert.Then the later gate area is structured by means of photolithography.
Anschließend werden die TEOS-Schicht und die Schicht aus -5 Polysilizium geätzt derart, dass ein Bereich oberhalb der isolierenden Schicht 100 übrig bleibt, so dass jeweils seitlich neben den nicht weggeätzten Teilen der TEOS-Schicht und der Schicht aus Polysilizium oberhalb der isolierenden Schicht 100 Raum gebildet wird für in weiteren Schritten 30 gebildete Spacer.The TEOS layer and the layer made of -5 polysilicon are then etched such that an area remains above the insulating layer 100, so that in each case laterally next to the parts of the TEOS layer and the layer made of polysilicon not etched away above the insulating layer 100 Space is formed for spacers 30 formed in further steps.
In einem weiteren Schritt wird eine weitere TEOS-Schicht ganzflächig aufgebracht und die Spacer 102 gebildet, indem die TEOS-Schicht sowie die freigelegten Teile der 35 isolierenden Schicht 100 ganzflächig anisotrop bis auf das Substrat 103 zurückgeätzt werden, so dass nur die Spacer 102 bestehen bleiben. Der fertiggestellte Gate-Komplex 100-102 ist aus Fig.la ersichtlich. Dieser wird durch die isolierenden Schicht 100, den Gate-Bereich 101 und den Spacer 102 gebildet. 5In a further step, a further TEOS layer is applied over the entire area and the spacers 102 are formed by etching the TEOS layer and the exposed parts of the insulating layer 100 anisotropically over the entire area down to the substrate 103, so that only the spacers 102 remain , The completed gate complex 100-102 can be seen in Fig.la. This is formed by the insulating layer 100, the gate region 101 and the spacer 102. 5
Nach dem Bilden des fertiggestellten Gate-Komplexes 100-102 wird gemäß eines Ausführungsbeispiels des Verfahrens das Substrat 103 beidseitig dieses Gate-Komplexes 100-102 isotrop weggeätzt, so dass sowohl neben als auch unter einem Teil des L0 Gate-Komplexes 100-102 ein Bereich des Substrats 103 ausgehöhlt wird.After the formation of the completed gate complex 100-102, according to one exemplary embodiment of the method, the substrate 103 is etched away isotropically on both sides of this gate complex 100-102, so that an area is located next to as well as under part of the L0 gate complex 100-102 of the substrate 103 is hollowed out.
Gemäß diesem Ausführungsbeispiel der Erfindung ist es vorgesehen, dass das Substrat 103 isotrop, d.h. nichtAccording to this embodiment of the invention, it is provided that the substrate 103 is isotropic, i.e. Not
L5 anisotrop weggeätzt wird. Auf diese Weise wird gewährleistet, dass es zu einer Unterätzung unterhalb eines Teils der isolierenden Schicht 100 kommt. Diese weggeätzten Aussparungen 110 beidseitig des Gate-Komplexes 100-102 werden letztendlich als der Source-Bereich bzw. der Drain-BereichL5 is anisotropically etched away. In this way it is ensured that there is an undercutting below a part of the insulating layer 100. These etched-away recesses 110 on both sides of the gate complex 100-102 are ultimately called the source region and the drain region
20 des fertiggestellten planaren Feldeffekttransistors 111 dienen.20 of the finished planar field effect transistor 111 are used.
Auf der sich durch das Wegätzen des Substrats 103 ergebende Oberfläche des Substrats 103 wird dann eine dünne, 25 dielektrische Schicht 104 aufgebracht.A thin, dielectric layer 104 is then applied to the surface of the substrate 103 resulting from the etching away of the substrate 103.
Diese dünne, dielektrische Schicht 104 dient als die eingangs erwähnte Barriereschicht, die im Wesentlichen kein Diffundieren der sich in dem Source-Bereich und dem Drain- 30 Bereich befindlichen Dotieratome in das umgebende Substrat 103, und besonders in den dazwischen liegenden Kanalbereich 108 hinein zulässt, welche Barriereschicht jedoch ein Tunneln elektrischer Ladungsträger durch sich selbst ermöglicht.This thin, dielectric layer 104 serves as the barrier layer mentioned at the outset, which essentially does not allow the doping atoms located in the source region and the drain region to diffuse into the surrounding substrate 103, and particularly into the channel region 108 lying between them. which barrier layer, however, allows electrical charge carriers to tunnel through themselves.
35 Beispielsweise kann ein thermisches Oxid, ein Nitrid oder eine Kombination aus einem Oxid und einem Nitrid für die Barriereschicht 104 verwendet werden. Bei dem Abscheiden des für die Barriereschicht 104 verwendeten Materials ist zu beachten, dass die Barriereschicht 104 in ihrem gesamten Verlauf in einer Dicke 5 von 2 nm oder weniger, vorzugsweise sogar nur in einer Dicke von 1 nm oder weniger, gebildet werden sollte.For example, a thermal oxide, a nitride, or a combination of an oxide and a nitride can be used for the barrier layer 104. When depositing the material used for the barrier layer 104, it should be noted that the entire course of the barrier layer 104 should be formed in a thickness 5 of 2 nm or less, preferably even only in a thickness of 1 nm or less.
So wird bei der Barriereschicht 104 allgemein eine derartige Dicke gewährleistet, dass das Tunneln der Ladungsträger ausIn the case of the barrier layer 104, such a thickness is generally ensured that the charge carriers tunnel out
10 dem Source-Bereich und aus dem Drain-Bereich stattfinden kann, während jedoch kein Diffundieren der Dotierstoffe aus dem Source-Bereich und/oder Drain-Bereich in das Substrat 103 oder in den zwischen dem Source-Bereich und dem Drain-Bereich liegenden Kanalbereich 108 hinein erfolgt.10 can take place from the source region and from the drain region, but no diffusion of the dopants from the source region and / or drain region into the substrate 103 or into the channel region lying between the source region and the drain region 108 into it.
L5L5
Fig.lc zeigt den planaren Feldeffekttransistor gemäß diesem Ausführungsbeispiel der Erfindung im fertiggestellten Zustand.Fig.lc shows the planar field effect transistor according to this embodiment of the invention in the finished state.
20 Oberhalb der in Fig.lb aufgebrachten Barriereschichten 104 beidseitig des Gate-Komplexes 100-102 sind aus Fig.lc zwei Bereiche 105, 109 ersichtlich, die den Source-Bereich 105 bzw. den Drain-Bereich 109 darstellen.20 Above the barrier layers 104 applied in FIG. 1b on both sides of the gate complex 100-102, FIG. 1c shows two regions 105, 109 which represent the source region 105 and the drain region 109.
25 Diese Bereiche 105, 109 werden in bekannter Weise durch25 These areas 105, 109 are passed through in a known manner
Abscheiden von Polysilizium, das in der Regel mit Arsenatomen dotiert ist, gebildet. Die Bereiche 105, 109 sind sehr hochDeposition of polysilicon, which is usually doped with arsenic atoms, formed. The areas 105, 109 are very high
21 dotiert, d.h. in der Regel bis zu einer Dichte von 10 As-21 endowed, i.e. usually up to a density of 10 As-
-3 Atome/cm . Aufgrund dieser besonders hohen-3 atoms / cm. Because of this particularly high
30 Dotierkonzentration könnte es sehr leicht zu einem unerwünschten Diffundieren dieser Dotieratome kommen, wenn es keine Barriereschicht 104 gäbe.30 doping concentration, it could very easily lead to an undesirable diffusion of these doping atoms if there were no barrier layer 104.
Mittels bekannter CMP-Verfahren (CMP = Chemical Mechanical 35 Polishing) wird sodann die mit Arsenatomen hochdotierte Polysilizium Schicht geebnet und somit für den nächsten Verfahrensschritt vorbereitet. Oberhalb des gesamten planaren Feldeffekttransistors wird eine weitere elektrisch isolierende Schicht 106 abgeschieden. • Die weitere isolierende Schicht 106 kann aus BPSG (BorUsing known CMP processes (CMP = Chemical Mechanical 35 Polishing), the polysilicon layer heavily doped with arsenic atoms is then leveled and thus prepared for the next process step. A further electrically insulating layer 106 is deposited above the entire planar field effect transistor. • The further insulating layer 106 may be formed of BPSG (boron
5 Phosphor Silikat Glas) bestehen, das manchmal als5 phosphor silicate glass), sometimes called
Zwischenoxid, oder „ZOX" bezeichnet wird. In die weitere isolierende Schicht 106 werden sodann Kontaktlöcher 107 geätzt, die einen Kontakt zwischen der metallischen Leiterbahn und dem Source-Bereich bzw. dem Drain-Bereich 109Intermediate oxide, or “ZOX”. Contact holes 107 are then etched into the further insulating layer 106, which make contact between the metallic conductor track and the source region or the drain region 109
L0 bei der anschließenden Metallisierung des planaren Feldeffekttransistors ermögliche .Enable L0 in the subsequent metallization of the planar field effect transistor.
Das Ausführungsbeispiel des Verfahrens sowie des planaren Feldeffekttransistors 111, das in Fig.la bis Fig.lc L5 dargestellt ist, ergibt einen Feldeffekttransistor 111 wie in Fig.lc gezeigt, bei dem die Barriereschicht 104 sowohl neben als auch unter einem Teil der isolierenden Schicht 100 gebildet wird.The exemplary embodiment of the method and of the planar field-effect transistor 111, which is illustrated in FIGS. 1 to C. L5, results in a field-effect transistor 111 as shown in FIG. 1 c, in which the barrier layer 104 is located both next to and under part of the insulating layer 100 is formed.
.0 Im Gegensatz dazu zeigt Fig.2 als ein weiteresIn contrast, Fig.2 shows as another
Ausführungsbeispiel einen planaren Feldeffekttransistor 212 in fertiggestelltem Zustand, bei dem die Barriereschicht 204 lediglich unter einem Teil der isolierenden Schicht 200, d.h. nicht auch neben der isolierenden Schicht 200, gebildet ist.Embodiment a planar field effect transistor 212 in the finished state, in which the barrier layer 204 only under part of the insulating layer 200, i.e. is not also formed next to the insulating layer 200.
.5.5
Bei diesem Ausführungsbeispiel der Erfindung erfolgt der Aufbau des Gate-Komplexes, bestehend aus der isolierenden Schicht 200, dem Gate-Bereich 201 und dem Spacer 202, in analoger Weise wie für Fig.la obenstehend beschrieben. AuchIn this exemplary embodiment of the invention, the gate complex, consisting of the insulating layer 200, the gate region 201 and the spacer 202, is constructed in an analogous manner to that described for Fig.la above. Also
SO das Abscheiden des Materials für die Barriereschicht 204 erfolgt in analoger Weise wie für Fig.la obenstehend beschrieben.SO the material for the barrier layer 204 is deposited in an analogous manner to that described for Fig.la above.
Der in Fig.2 dargestellte planare Feldeffekttransistor 212 >5 weist zwei Barrieren 204 sowie einen Source-Bereich 205 und einen Drain-Bereich 206 auf unterhalb der isolierenden Schicht 200 zwischen der isolierenden Schicht 200 und einer planaren freigelegten Fläche 207. Jeweils eine der beiden Barrieren 204 ist zwischen dem Source-Bereich 205 und dem Kanalbereich 203 sowie zwischen dem Drain-Bereich 206 und dem Kanalbereich 203 angeordnet.The planar field-effect transistor 212> 5 shown in FIG. 2 has two barriers 204 as well as a source region 205 and a drain region 206 below the insulating layer 200 between the insulating layer 200 and one planar exposed surface 207. One of the two barriers 204 is arranged between the source region 205 and the channel region 203 and between the drain region 206 and the channel region 203.
Gemäß diesem Ausführungsbeispiel werden die Barrieren 204 mittels einer thermischen Oxidation erzeugt, so dass die Barrieren 204 automatisch in der in Fig.2 dargestellten Form entstehen, weil die planare freigelegte Fläche 207 schon aus dem vergrabenen Oxid des SOI-Ausgangsmaterials besteht.According to this exemplary embodiment, the barriers 204 are generated by means of a thermal oxidation, so that the barriers 204 automatically arise in the form shown in FIG. 2 because the planar exposed surface 207 already consists of the buried oxide of the SOI starting material.
Anschaulich entspricht diese Vorgehensweise dem Bilden eines Ausgangsmaterials eines SOI-Komplexes (Silicon On Insulator) .This procedure clearly corresponds to the formation of a starting material for an SOI complex (Silicon On Insulator).
So entsteht im fertiggestellten Zustand des planarenThis creates in the finished state of the planar
Feldeffekttransistors 212 eine Barriereschicht 204 lediglich zwischen dem Source-Bereich 206 und dem Kanalbereich 203 sowie zwischen dem Drain-Bereich 205 und dem Kanalbereich 203.Field effect transistor 212 has a barrier layer 204 only between the source region 206 and the channel region 203 and between the drain region 205 and the channel region 203.
In anderen Worten ausgedrückt bedeutet dies, dass es in diesem Ausführungsbeispiel der Erfindung keine Barriereschicht 204 zwischen dem Source-Bereich 206 bzw. dem Drain-Bereich *205 und dem Substrat 209 gibt.In other words, this means that in this exemplary embodiment of the invention there is no barrier layer 204 between the source region 206 or the drain region * 205 and the substrate 209.
Es ist anzumerken, dass bei diesem Ausführungsbeispiel der Erfindung das Substrat 209 aus zwei unterteilten Abschnitten 207 und 208 besteht. Hierbei besteht der Substrat-Bereich 208 aus einem leitfähigen Material, wie beispielsweise Silizium, und der Substrat-Abschnitt 207 besteht vorzugsweise aus einem nicht leitfähigen Material, beispielsweise einem Oxid.It should be noted that in this embodiment of the invention, the substrate 209 consists of two divided sections 207 and 208. Here, the substrate region 208 consists of a conductive material, such as silicon, and the substrate section 207 preferably consists of a non-conductive material, for example an oxide.
Die Beschaffenheit des Substrat-Abschnitts 207 als nicht leitfähiges Material verhindert, dass Dotieratome in dem Source-Bereich 205 bzw. dem Drain-Bereich 206 in das darunterliegende Material des Substrats 209 hinein diffundieren, und so den Kanalbereich 203 verunreinigen. Im Gegensatz dazu wäre ein Diffundieren der Dotieratome in dem Source-Bereich 205 bzw. dem Drain-Bereich 206 in den dazwischen liegenden Kanalbereich 203 hinein ohne Barriereschicht 204 sehr wohl möglich, weshalb sich dieseThe nature of the substrate section 207 as a non-conductive material prevents doping atoms in the source region 205 or the drain region 206 from diffusing into the underlying material of the substrate 209 and thus contaminating the channel region 203. In contrast, a diffusion of the doping atoms in the source region 205 or the drain region 206 into the channel region 203 lying in between would be very possible without a barrier layer 204, which is why this
Barriereschicht 204 zwischen dem Source-Bereich 206 bzw. dem Drain-Bereich 205 und dem dazwischen liegenden Kanalbereich 203 befindet.Barrier layer 204 is located between the source region 206 or the drain region 205 and the intermediate channel region 203.
Der Aufbau des in Fig.2 dreischichtig ausgestaltetenThe structure of the three-layer design in FIG
Substrats 209 erfolgt in einfacher Weise vor dem Aufbau des Gate-Komplexes 200-202. Der Aufbau erfolgt ausgehend von einer Siliziumschicht 208, worauf eine nicht leitfähige isolierende Schicht 207 aufgebracht wird und schließlich durch das Aufbringen einer dritten Schicht aus Silizium auf der isolierenden Schicht 207. Nach dem Wegätzen bildet diese dritte Schicht dann den Kanalbereich 203.Substrate 209 is carried out in a simple manner before the gate complex 200-202 is built. The structure is based on a silicon layer 208, on which a non-conductive insulating layer 207 is applied and finally by applying a third layer of silicon on the insulating layer 207. After etching away, this third layer then forms the channel region 203.
Auf den Source-Bereich 205, dem Gate-Komplex 200-202 sowie dem Drain-Bereich 206 wird eine elektrisch isolierendeAn electrically insulating layer is applied to the source region 205, the gate complex 200-202 and the drain region 206
Schicht 210, vorzugsweise aus Siliziumdioxid, aufgebracht, in die in einem weiteren Schritt Kontaktlöcher 211 für Leiterbahnen geätzt werden, die einen Kontakt zwischen der metallischen Leiterbahn und dem Source-Bereich bzw. dem Drain-Bereich 109 bei der anschließenden Metallisierung des planaren Feldeffekttransistors ermöglichen.Layer 210, preferably made of silicon dioxide, is applied, in which, in a further step, contact holes 211 for conductor tracks are etched, which enable contact between the metallic conductor track and the source region or drain region 109 during the subsequent metallization of the planar field effect transistor.
Fig.3 zeigt einen weiteren fertiggestellten, planaren Feldeffekttransistor, der mittels des erfindungsgemäßen Verfahrens ausgehend von dem noch nicht fertiggestelltenFIG. 3 shows a further finished, planar field effect transistor which, based on the method according to the invention, starts from that which has not yet been completed
Feldeffekttransistor, der in Fig.la gezeigt ist, hergestellt wird.Field effect transistor shown in Fig.la is manufactured.
Bei der Herstellung des planaren Feldeffekttransistors in Fig.3 wird nach dem Aufbau des Gate-Komplexes 100-102 auf dem Substrat 103 in Fig.la (entspricht Gate-Komplex 300-302 bzw. Substrat 307 in Fig.3) die Barriereschicht 304 direkt auf dem Substrat 307 gebildet, ohne dass das Substrat 307 im Voraus weggeätzt wird. Die Barriereschicht 304 in Fig.3 wird also ausschließlich neben, d.h. weder ausschließlich unter (vgl. Fig.2) noch unter und neben (vgl. Fig.lc) der Isolierschicht 300 gebildet. Der Source-Bereich 306 bzw. Drain-Bereich 305 des Feldeffekttransistors 309 in Fig.3 kann also direkt auf der Barriereschicht abgeschieden werden, ohne dass es im Voraus eines weiteren Ätzverfahrens bedarf.In the manufacture of the planar field effect transistor in FIG. 3, after the gate complex 100-102 has been built up on the substrate 103 in FIG.la (corresponds to the gate complex 300-302 or substrate 307 in FIG. 3), the barrier layer 304 is direct on the Substrate 307 is formed without the substrate 307 being etched away in advance. The barrier layer 304 in FIG. 3 is therefore formed exclusively next to, ie neither exclusively under (cf. FIG. 2) nor under and next to (cf. FIG. 1c) the insulating layer 300. The source region 306 or drain region 305 of the field effect transistor 309 in FIG. 3 can therefore be deposited directly on the barrier layer without the need for a further etching process in advance.
Es ist anzumerken, dass das in Fig.3 gezeigteNote that the one shown in Fig.3
Ausführungsbeispiel des planaren Feldeffekttransistors 309 gemäß der Erfindung keinen Kanalbereich aufweist, welcher im Gegensatz zu den Ausführungsbeispielen in Fig.lc und in Fig.2, unmittelbar an der Barriereschicht 304 grenzt. Aus Fig.3 ist ersichtlich, dass der Kanalbereich 308 beidseitig um den Abstand 303 von den jeweiligen Barriereschichten 304 entfernt angeordnet ist. Der Abstand 303 ergibt sich aus der Dicke des Spacers 302, der auf der isolierenden Schicht 300 gebildet ist. Die Bereiche 303 unterhalb der isolierenden Schicht 300 liegen außerhalb des durch den Gate-Bereich 301 erzeugten Feldes, so dass bei angelegter Gate-Spannung die Leitfähigkeit der Bereiche 303 gegenüber derjenigen des Kanalbereichs 308, der direkt in dem durch den Gate-Bereich 301 erzeugten Feld liegt, geringer ist.Embodiment of the planar field effect transistor 309 according to the invention does not have a channel region which, in contrast to the embodiments in FIG. 1c and in FIG. 2, borders directly on the barrier layer 304. It can be seen from FIG. 3 that the channel region 308 is arranged on both sides at a distance 303 from the respective barrier layers 304. The distance 303 results from the thickness of the spacer 302 that is formed on the insulating layer 300. The regions 303 below the insulating layer 300 lie outside the field generated by the gate region 301, so that when the gate voltage is applied, the conductivity of the regions 303 compared to that of the channel region 308 is directly in the field generated by the gate region 301 is less.
Aus diesem Grund ist die Steuerbarkeit des planaren Feldeffekttransistors in Fig.3 von dem Abstand 303 abhängig, wobei ein größerer Abstand 303 zu einer verschlechterten Steuerbarkeit des planaren Feldeffekttransistors 309 führt.For this reason, the controllability of the planar field effect transistor in FIG. 3 depends on the distance 303, a larger distance 303 leading to a deteriorated controllability of the planar field effect transistor 309.
Bei dem Aufbau des planaren Feldeffekttransistors 309 in Fig.3 ist also verfahrenstechnisch darauf zu achten, dass der auf der isolierenden Schicht 300 gebildete, nicht leitfähige Spacer 302 durch entsprechende Einstellung des zur Bildung dieses Spacers verwendeten Abscheideverfahrens möglichst dünn gebildet wird. Bevorzugt wird der Spacer in einer Dicke von höchstens 10 nm gebildet, so dass die Abstände 303 klein genug sind, um eine Diffusion von Ladungsträgern durch die weniger gut leitfähigen Bereiche 303 des Substrats 307 beidseitig des Kanalbereichs 308 zu ermöglichen und daher eine gute Steuerbarkeit des planaren Feldeffekttransistors zu gewährleisten . In the construction of the planar field effect transistor 309 in FIG. 3, it must be ensured in terms of process engineering that the non-conductive spacer 302 formed on the insulating layer 300 is formed as thin as possible by appropriate setting of the deposition method used to form this spacer. The spacer is preferably formed with a thickness of at most 10 nm, so that the distances 303 are small enough to allow diffusion of charge carriers through the less highly conductive regions 303 of the substrate 307 on both sides of the channel region 308 and therefore good controllability of the planar region To ensure field effect transistor.
In diesem Dokument sind folgende Veröffentlichungen zitiert:The following publications are cited in this document:
[1] T. Kisu, K. Nakazato, Silicon stacked transistor with source and drain tunnel barriers, Proceedings of the 29th European solid-state device research Conference ESSDERC, S. 532, 1999.[1] T. Kisu, K. Nakazato, Silicon stacked transistor with source and drain tunnel barriers, Proceedings of the 29th European solid-state device research Conference ESSDERC, p. 532, 1999.
[2] V.H.C. Watt et al, Ultra-Thin High Quality Oxynitride Formed by NH3 Nitridation and High Pressure 02 Re- oxidation, Proceedings of the 30th European Solid-State Device Research Conference (ESSDERC 2000), Cork, Ireland, 11. - 13. September 2000[2] V.H.C. Watt et al, Ultra-Thin High Quality Oxynitride Formed by NH3 Nitridation and High Pressure 02 Reoxidation, Proceedings of the 30th European Solid-State Device Research Conference (ESSDERC 2000), Cork, Ireland, September 11-13, 2000
[3] DE 42 12 861 C2[3] DE 42 12 861 C2
;4] US 6,091,076 ; 4] US 6,091,076
BezugszeichenlisteLIST OF REFERENCE NUMBERS
100 Isolierende Schicht100 insulating layer
101 Gate-Bereich101 gate area
102 Spacer102 spacers
103 Substrat103 substrate
104 Barriereschicht104 barrier layer
105 Drain- /Source-Bereich105 Drain / source area
106 Isolierende Siliziumdioxidschicht106 Insulating silicon dioxide layer
107 Kontaktlöcher für Leiterbahnen107 contact holes for conductor tracks
108 Kanalbereich108 channel area
109 Source- /Drain-Bereich109 source / drain region
200 Isolierende Schicht200 insulating layer
201 Gate-Bereich 202 Spacer201 gate area 202 spacer
203 Kanalbereich203 channel area
204 Barriereschicht204 barrier layer
205 Drain- /Source-Bereich205 drain / source area
206 Source- /Drain-Bereich206 source / drain region
207 Isolierende Substratschicht 208 Leitende Substratschicht207 Insulating substrate layer 208 Conductive substrate layer
209 Substrat209 substrate
210 Isolierende Siliziumdioxidschicht210 Insulating silicon dioxide layer
211 Kontaktlöcher für Leiterbahne211 contact holes for conductor track
300 Isolierende Schicht300 insulating layer
301 Gate-Bereich 302 Spacer301 gate area 302 spacer
303 Abstand303 distance
304 Barriereschicht304 barrier layer
305 Drain-/Source-Bereich305 drain / source area
306 Source- /Drain-Bereich 307 Substrat306 source / drain region 307 substrate
308 Kanalbereich 308 channel area

Claims

Patentansprüche claims
1. Verfahren zum Herstellen eines planaren Feldeffekttransistors, • bei dem auf einem Substrat eine isolierende Schicht gebildet wird;1. A method for producing a planar field-effect transistor, • in which an insulating layer is formed on a substrate;
• bei dem auf der isolierenden Schicht ein Gate-Bereich gebildet wird;• in which a gate region is formed on the insulating layer;
• bei dem auf der isolierenden Schicht mindestens ein Spacer gebildet wird;• in which at least one spacer is formed on the insulating layer;
• bei dem neben der isolierenden Schicht und/oder unter einem Teil der isolierenden Schicht eine Barriereschicht gebildet wird;• in which a barrier layer is formed next to the insulating layer and / or under part of the insulating layer;
« bei dem auf der einen Seite der isolierenden Schicht ein Source-Bereich abgeschieden wird und auf der anderen Seite der isolierenden Schicht ein Drain-Bereich abgeschieden wird und zwischen dem Source-Bereich und dem Drain-Bereich ein Kanalbereich unterhalb der isolierenden Schicht gebildet wird; und * bei dem die Barriereschicht zwischen dem Source-Bereich und dem Kanalbereich und/oder zwischen dem Drain-Bereich und dem Kanalbereich derart gebildet wird, dass im wesentlichen kein Diffundieren der sich in dem Source- Bereich und dem Drain-Bereich befindlichen Dotieratome in den Kanalbereich erfolgen kann, jedoch ein Tunneln elektrischer Ladungsträger durch die Barriereschicht in den Kanalbereich und in das Substrat möglich ist.«In which a source region is deposited on one side of the insulating layer and a drain region is deposited on the other side of the insulating layer and a channel region is formed below the insulating layer between the source region and the drain region; and * in which the barrier layer is formed between the source region and the channel region and / or between the drain region and the channel region in such a way that essentially no diffusion of the doping atoms located in the source region and the drain region into the Channel area can take place, but a tunneling of electrical charge carriers through the barrier layer into the channel area and into the substrate is possible.
2. Verfahren gemäß Anspruch 1, bei dem für den Fall, dass die Barriereschicht neben und unter einem Teil der isolierenden Schicht gebildet werden soll, das Substrat vor dem Bilden der Barriereschicht neben und teilweise unter der isolierenden Schicht isotrop weggeätzt wird.2. The method of claim 1, wherein in the event that the barrier layer is to be formed next to and under a part of the insulating layer, the substrate is isotropically etched away next to and partly below the insulating layer before the barrier layer is formed.
3. Verfahren gemäß Anspruch 1 , bei dem die Barriereschicht in einer Dicke von 2 nm oder weniger gebildet wird.3. The method according to claim 1, in which the barrier layer is formed in a thickness of 2 nm or less.
4. Verfahren gemäß einem der Ansprüche 1 bis 3, bei dem der Spacer aus Siθ2 gebildet wird, das mittels eines TEOS-, Silanoxid-, LTO-, SACVD- , HTO-, PECVD- oder Dep./Etch- Abscheideverfahrens gebildet wird.4. The method according to any one of claims 1 to 3, wherein the spacer is formed from SiO 2, which is formed by means of a TEOS, silane oxide, LTO, SACVD, HTO, PECVD or Dep./Etch deposition process.
5. Verfahren gemäß Anspruch 4, bei dem der Spacer in einer Dicke von höchstens 50 nm gebildet wird,5. The method according to claim 4, in which the spacer is formed in a thickness of at most 50 nm,
6. Verfahren gemäß einem der Ansprüche 1 bis 5, bei dem die Barriereschicht aus einem dielektrischen Material gebildet wird.6. The method according to any one of claims 1 to 5, wherein the barrier layer is formed from a dielectric material.
7. Verfahren gemäß Anspruch 6, bei dem die Barriereschicht aus einem Oxynitrid gebildet wird.7. The method of claim 6, wherein the barrier layer is formed from an oxynitride.
8. Verfahren gemäß Anspruch 6, bei dem die Barriereschicht aus Siθ2 oder Si3N4 gebildet wird.8. The method according to claim 6, wherein the barrier layer is formed from SiO 2 or Si3N4.
9. Planarer Feldeffekttransistor, mit9. Planar field effect transistor, with
© einem elektrisch leitenden Substrat, © einem abgeschiedenen Drain-Bereich, © einem abgeschiedenen Source-Bereich, β einem Kanalbereich zwischen dem Drain-Bereich und dem Source-Bereich,© an electrically conductive substrate, © a deposited drain region, © a deposited source region, β a channel region between the drain region and the source region,
« einem Gate-Bereich auf der isolierenden Schicht, wobei auf dem Gate-Bereich und auf der isolierenden Schicht mindestens ein Spacer angeordnet ist, « einer isolierenden Schicht zwischen dem Gate-Bereich und dem Substrat"A gate region on the insulating layer, at least one spacer being arranged on the gate region and on the insulating layer," an insulating layer between the gate region and the substrate
© einer Barriereschicht neben dem Gate-Bereich und/oder unter einem Teil des Gate-Bereichs, • wobei die Barriereschicht zwischen dem Source-Bereich und dem Kanalbereich und/oder zwischen dem Drain-Bereich und dem Kanalbereich derart ausgestaltet ist, dass im wesentlichen kein Diffundieren der sich in dem Source- Bereich und dem Drain-Bereich befindlichen Dotieratomen in den Kanalbereich erfolgen kann, jedoch ein Tunneln elektrischer Ladungsträger durch die Barriereschicht in den Kanalbereich und in das Substrat möglich ist.© a barrier layer next to the gate area and / or under part of the gate area, • The barrier layer between the source region and the channel region and / or between the drain region and the channel region is designed such that there is essentially no diffusion of the doping atoms located in the source region and the drain region into the channel region can, however, tunneling of electrical charge carriers through the barrier layer into the channel region and into the substrate is possible.
10. Planarer Feldeffekttransistor gemäß Anspruch 9, bei dem die Barriereschicht dielektrisches Material aufweist.10. A planar field effect transistor according to claim 9, wherein the barrier layer comprises dielectric material.
11. Planarer Feldeffekttransistor gemäß Anspruch 9, bei dem die Barriereschicht Oxynitrid aufweist.11. A planar field effect transistor according to claim 9, wherein the barrier layer comprises oxynitride.
12. Planarer Feldeffekttransistor gemäß Anspruch 10, bei dem die Barriereschicht Siθ2 oder Si3N4 aufweist.12. A planar field effect transistor as claimed in claim 10, in which the barrier layer has SiO 2 or Si3N4.
13. Planarer Feldeffekttransistor gemäß einem der Ansprüche 9 bis 12, bei dem die Dicke der Barriereschicht höchstens 2 nm beträgt.13. Planar field effect transistor according to one of claims 9 to 12, wherein the thickness of the barrier layer is at most 2 nm.
14. Planarer Feldeffekttransistor gemäß einem der Ansprüche 9 bis 12, bei dem die Dicke der Barriereschicht höchstens 1 nm beträgt.14. Planar field effect transistor according to one of claims 9 to 12, wherein the thickness of the barrier layer is at most 1 nm.
15. Planarer Feldeffekttransistor gemäß einem der Ansprüche 9 bis 14, bei dem der Spacer Siθ2 aufweist.15. Planar field effect transistor according to one of claims 9 to 14, in which the spacer has SiO 2.
16. Planarer Feldeffekttransistor gemäß einem der Ansprüche 9 bis 15, bei dem die Barriereschicht neben dem Gate-Bereich liegt, wobei die Dicke des Spacers höchstens 50 nm beträgt. 16. Planar field effect transistor according to one of claims 9 to 15, in which the barrier layer is adjacent to the gate region, the thickness of the spacer being at most 50 nm.
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