TW202107288A - Information processing method, apparatus, electronic device and storage medium - Google Patents

Abstract

In examples of the present disclosure, an information processing method, apparatus, electronic device and storage medium are provided. According to the method, CPU obtains data to be processed, allocates a virtual storage space for the data to be processed, and stores the data to be processed in the virtual storage space. CPU sends data processing instruction carrying information of the virtual storage space to a DSP, the instruction being configured to indicate the DSP to obtain the data to be processed from the virtual storage space corresponding to the information and process the data to be processed.

Description

Information processing method, device, electronic equipment and recording medium

The present invention relates to the field of computer technology, in particular to information processing methods, devices, electronic equipment and recording media.

With the continuous development of computer technology, more and more data need to be processed. When processing data, it generally requires a central processing unit (CPU) and a digital signal processor (digital signal processor, DSP) to work together to complete. However, the DSP cannot directly access the memory space on the CPU, and the CPU also cannot directly access the space opened up by the DSP. At present, in the process of data processing through the neural network model, the CPU calls the DSP once for each operation, which makes the scheduling overhead of the DSP relatively large.

The embodiments of the present invention provide information processing methods, devices, electronic equipment, and recording media.

A first aspect provides an information processing method, including: a CPU obtains data to be processed; allocating virtual storage space for the data to be processed; storing the data to be processed in the virtual storage space; sending and carrying the virtual storage to the DSP A data processing instruction for spatial information, where the data processing instruction is used by the DSP to obtain the to-be-processed data from a virtual storage space corresponding to the information and process the to-be-processed data.

As a possible implementation manner, the virtual storage space corresponds to the first buffer space in the buffer of the electronic device; the storing the to-be-processed data in the virtual storage space includes: a CPU transfers the to-be-processed data to the virtual storage space. Storing in the first buffer space; the DSP obtaining the to-be-processed data from the virtual storage space corresponding to the information includes: the DSP obtaining the to-be-processed data from the first buffer space corresponding to the information.

As a possible implementation manner, the allocating virtual storage space for the to-be-processed data includes: requesting a buffer space from the buffer of the electronic device based on the size of the storage space required by the to-be-processed data; The location indication information of the first buffer space returned by the device's buffer determines the physical storage location of the virtual storage space.

As a possible implementation manner, the data to be processed includes at least one array, and each array includes data of the same type. The method further includes: determining the storage space required by each array in the at least one array; The size of the storage space required by each array in the at least one array determines the size of the storage space required by the data to be processed.

As a possible implementation manner, the method further includes: determining the offset of each array in the at least one array in the virtual storage space according to the size of the storage space required by each array in the at least one array the amount.

As a possible implementation manner, the method further includes: determining the size of the storage space required for the data to be processed based on the data volume of the data to be processed and the result data volume corresponding to the data to be processed.

As a possible implementation manner, based on the size of the storage space required by the to-be-processed data, applying for a buffer space from the buffer of the electronic device includes: sending a buffer for applying for buffer space to the buffer of the electronic device A request, the request carrying information about the size of the storage space required by the data to be processed; receiving position indication information from the buffer, the position indication information being used to indicate the base address of the first buffer space.

As a possible implementation manner, the data to be processed are network parameters and input data of the network layer in the neural network.

The second aspect provides another information processing method, including: DSP receives a data processing instruction from a CPU, the data processing instruction carries information in a virtual storage space; acquiring data to be processed from a virtual storage space corresponding to the information; The pending data is processed.

As a possible implementation manner, the virtual storage space corresponding to the information corresponds to the first cache space in the register of the electronic device; and the obtaining the to-be-processed data from the virtual storage space corresponding to the information includes: The corresponding first buffer space acquires the data to be processed.

As a possible implementation manner, the method further includes: storing the processing result of the to-be-processed data in a first buffer space corresponding to the information.

As a possible implementation manner, the data to be processed are network parameters and input data of the network layer in the neural network.

A third aspect provides an information processing device, including: an acquisition unit for acquiring data to be processed; an allocation unit for allocating virtual storage space for the data to be processed; and a storage unit for storing the data to be processed To the virtual storage space; a sending unit for sending a data processing instruction carrying information of the virtual storage space to the DSP, and the data processing instruction is used by the DSP to obtain the information from the virtual storage space corresponding to the information The data to be processed and the data to be processed are processed.

A fourth aspect provides another information processing device, including: a receiving unit for receiving a data processing instruction from a CPU, the data processing instruction carrying information in a virtual storage space; and an acquiring unit for obtaining information from the virtual storage corresponding to the information The space obtains the data to be processed; the processing unit is used to process the data to be processed.

A fifth aspect provides an information processing device, including a processor and a storage device, the storage device is used to store computer-readable instructions, and the processor is used to call the computer-readable instructions stored in the storage device to execute as in the first aspect Or the information processing method provided by any of the possible implementations in the first aspect.

A sixth aspect provides an information processing device, including a processor and a storage device, the storage device is used to store computer-readable instructions, and the processor is used to call the computer-readable instructions stored in the storage device to execute as in the second aspect Or the information processing method provided by any of the possible implementations in the second aspect.

A seventh aspect provides an electronic device, including the information processing device provided in the fifth aspect and the information processing device provided in the sixth aspect, or the information processing device provided in the third aspect and the information processing device provided in the fourth aspect.

An eighth aspect provides a computer-readable recording medium. The computer-readable recording medium stores a computer program. The computer program includes a program code that, when executed by a processor, causes the processor to execute the first aspect or the first aspect. An information processing method provided in any possible implementation manner in one aspect, or an information processing method provided in a second aspect or any possible implementation manner in the second aspect.

A ninth aspect provides a computer program product, which is used to execute the information processing method provided in the first aspect or any one of the possible implementations of the first aspect, or any one of the second aspect or the second aspect at runtime Information processing methods provided by possible implementations.

In the embodiment of the present invention, the CPU obtains the data to be processed, allocates virtual storage space for the data to be processed, stores the data to be processed in the virtual storage space, and sends a data processing instruction carrying information of the virtual storage space to the DSP. The data processing instruction is used for The DSP obtains the data to be processed from the virtual storage space corresponding to the information and processes the data to be processed. In this way, the CPU can send data corresponding to multiple operations to the DSP at one time through the virtual storage space, thereby reducing DSP scheduling overhead and improving information processing efficiency.

The embodiments of the present invention provide information processing methods, devices, electronic equipment, and recording media for improving data processing efficiency. Detailed descriptions are given below.

At present, in the data processing of neural network models, DSP (for example, hexagon) is widely used, which has the advantages of high computing performance and low power consumption. However, the use of DSP has many issues that require additional consideration.

For example, the DSP cannot directly access the memory space on the CPU. Similarly, the CPU cannot directly access the space opened up by the DSP. When the DSP and the CPU need to exchange data, the address space needs to be allocated through the ION buffer (ION Buffer). For example, when the CPU needs to call the DSP, through the Fast Remote Procedure Call (Fast Remote Procedure Call, FastRPC) mechanism, only the data to be transferred by the CPU to the DSP for this call is mapped to the address space allocated by the ION Buffer. However, the number of address spaces that can be mapped by a single DSP call is limited, and if a block of address space is not mapped in this call, even if the address space has been mapped before, the DSP cannot access the address space correctly. Data in address space.

In the case that both the DSP and the CPU are applied to the data processing of the neural network model, the DSP needs to be called once for each operation in the neural network model. Therefore, when the depth of the neural network model is deep, the CPU cannot transfer all the data required for data processing through a single call to the DSP, but has to call the DSP multiple times. However, repeatedly calling the DSP will bring a very large overhead. In addition, the address space mapped on the ION Buffer may be different each time the DSP is called, and the DSP cannot correctly access the data in the address space that should be mapped for the last call.

In view of this, the present invention proposes an information processing method that can be applied to neural network models. According to this method, a virtual storage space can be maintained by the CPU. The virtual storage space stores information (for example, weight parameters and input data) required by the DSP to execute the data processing of the neural network model, and the virtual storage space can be used by the DSP shared. In this way, the CPU can transfer all the data required by the DSP for data processing of the entire neural network model to the DSP through only one or a limited number of calls, thereby minimizing the overhead caused by the DSP call.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an electronic device applied in an embodiment of the present invention. As shown in FIG. 1, the electronic device may include a CPU 101, a DSP 102, and a buffer 103. The CPU 101 is configured to receive operation instructions carrying data, and schedule the DSP 102 based on the received operation instructions. The DSP 102 is used to process data in response to the scheduling of the CPU 101. The buffer 103 is used for buffering data. Optionally, the buffer 103 may be an ION buffer, or other buffers or storage modules that can be accessed by the CPU and DSP.

Please refer to FIG. 2. FIG. 2 is a schematic flowchart of an information processing method according to an embodiment of the present invention. This method can be applied to the electronic device shown in FIG. 1. Among them, the information processing method is described from the perspective of the CPU. As shown in Figure 2, the information processing method may include the following steps.

201. Obtain data to be processed.

The CPU can obtain the running instruction carrying the data to be processed, and can schedule the DSP based on the running instruction. The running instruction may be input by the user, generated by the electronic device to which the CPU belongs, or sent by other electronic devices or servers. The data to be processed can be the network parameters and input data of the network layer in the neural network, and the number of layers of the network layer is greater than one. The data to be processed can also be other data processed by the DSP alone or data that need to be processed by the CPU and the DSP together.

202. Allocate virtual storage space for the data to be processed.

After the CPU obtains the data to be processed, it allocates virtual storage space for the data to be processed. A cache space can be applied to the electronic device cache based on the size of the storage space required by the data to be processed, and then the physical storage location corresponding to the virtual storage space can be determined based on the location indication information of the first cache space returned by the electronic device cache. Among them, the electronic device cache refers to the cache in the electronic device to which the CPU belongs, and the cache can be accessed by the CPU and DSP. The buffer can be an ION buffer or other buffers that can be accessed by the CPU and DSP.

The CPU may first send a request for applying for cache space (for example, an application instruction) to the cache in the electronic device, and the request may carry information on the size of the storage space required for the data to be processed. After the buffer receives the request from the CPU, the first buffer space can be selected from the free buffer space of the buffer, the size of the first buffer space is equal to the storage space required by the data to be processed, and the location indication is allocated for the first buffer space Information, such as an indicator pointing to the first buffer space, then returns the position indication information to the CPU. After the CPU receives the position indication information of the first buffer space from the register, it can create a virtual storage space based on the storage space required by the data to be processed, allocate a base address for the virtual storage space, and create a virtual storage space. The corresponding relationship between the base address and the position indication information. Wherein, the creation of the virtual storage space based on the size of the storage space required by the data to be processed and the allocation of the base address for the virtual storage space may also be created before sending the request for applying for the buffer space to the buffer in the electronic device. Before sending the request for applying for cache space to the cache in the electronic device, the request is also acceptable if the virtual storage space has been created based on the size of the storage space required for the data to be processed and the base address is allocated for the virtual storage space. Carry the base address of the virtual storage space. At this time, the register can establish the corresponding relationship between the position indication information and the base address of the virtual storage space. After the CPU receives the position indication information indicating the first cache space from the register, the corresponding relationship between the base address of the virtual storage space and the position indication information may not be established. Wherein, the position indication information of the first cache space is used to indicate the base address of the first cache space. It can be seen that the virtual storage space can make the data to be processed including multiple operations correspond to a position indication information in the register, such as an index. In this way, data including multiple operations can be shared to the DSP at one time through the virtual storage space, thereby improving the efficiency of information processing. In addition, because the first cache space is applied for based on the storage space required for the data to be processed, it is possible to apply for a suitable cache space, that is, it will not cause a waste of cache space due to the application of too much cache space, nor Because too little cache space is requested, the data to be processed cannot be cached.

203. Store the to-be-processed data in the virtual storage space.

After the CPU allocates the virtual storage space for the data to be processed, the data to be processed can be stored in the virtual storage space, that is, the data to be processed is stored in the first cache space corresponding to the virtual storage space.

204. Send a data processing instruction carrying information of the virtual storage space to the DSP.

After the CPU stores the data to be processed in the virtual storage space, it can send data processing instructions carrying the information of the virtual storage space to the DSP, so that the DSP can obtain the data to be processed from the virtual storage space corresponding to the information in the virtual storage space and process the data to be processed . The CPU can call the preset library to send data processing instructions carrying information of the virtual storage space to the DSP. The default library is a library specifically used to call DSP, such as FastRPC. The information of the virtual storage space may include the base address of the virtual storage space.

In the information processing method described in Figure 2, the CPU can share the data of multiple operations to the DSP at one time through the virtual storage space. In this process, only one DSP scheduling can be performed, thereby reducing the DSP scheduling overhead and improving the information. Processing efficiency.

Please refer to FIG. 3, which is a schematic flowchart of another information processing method according to an embodiment of the present invention. Among them, the information processing method is described from the perspective of the CPU. As shown in FIG. 3, the information processing method may include the following steps.

301. Obtain data to be processed.

Among them, step 301 is the same as step 201. For detailed description, please refer to step 201, which will not be repeated here.

302. Determine the size of storage space required for the data to be processed.

After the CPU obtains the data to be processed, it can determine the amount of storage space required for the data to be processed. In some embodiments, the storage space required by each array in at least one array included in the data to be processed may be determined first, and then the data to be processed can be determined based on the storage space required by each array in the at least one array The required storage space size, that is, the sum of the storage space required by each array in at least one array can be determined as the storage space required for the data to be processed. Among them, each array includes the same type of data.

In some embodiments, the amount of storage space required for the data to be processed can also be determined based on the data volume of the data to be processed and the result data volume corresponding to the data to be processed (ie, the data volume of the result data corresponding to the data to be processed), that is, The sum of the amount of data to be processed and the amount of result data corresponding to the data to be processed can be determined as the storage space required for the data to be processed. The amount of result data can be predetermined according to the processing parameters involved in the data to be processed.

In some embodiments, the amount of data in each array and the amount of result data corresponding to each array in the at least one array included in the data to be processed may also be determined first, and then based on the amount of data in each array and each array in the at least one array. The amount of result data corresponding to the array determines the storage space required for each array in at least one array. That is, first calculate the storage space required for the data included in each array and the storage space required for the result corresponding to the data included in the array, and then the storage storage space required for the data included in each array and the array include The sum of the storage space required for the results corresponding to the data of the data is the storage space required for each array.

303. Allocate virtual storage space for the data to be processed according to the size of the storage space required by the data to be processed.

Wherein, step 303 is the same as step 202. For detailed description, please refer to step 202, which will not be repeated here. In addition, the CPU may also determine the offset of each array in the at least one array in the virtual storage space according to the size of the storage space required by each array in the at least one array. Then, data can be written in the virtual storage space according to the base address and offset.

304. Store the to-be-processed data in the virtual storage space.

Wherein, step 304 is the same as step 203. For detailed description, please refer to step 203, which will not be repeated here.

305. Send a data processing instruction carrying information of the virtual storage space to the DSP.

Wherein, step 305 is the same as step 204. For detailed description, please refer to step 204, which will not be repeated here.

In the information processing method described in FIG. 3, the CPU can send data including multiple operations to the DSP at one time through the virtual storage space, thereby reducing the DSP scheduling overhead and improving the efficiency of information processing.

Please refer to FIG. 4, which is a schematic flowchart of another information processing method according to an embodiment of the present invention. Among them, the information processing method is described from the perspective of DSP. As shown in FIG. 4, the information processing method may include the following steps.

401. Receive a data processing instruction from the CPU.

After the CPU sends a data processing instruction carrying information of the virtual storage space to the DSP, the DSP receives the data processing instruction from the CPU. Both the CPU and the DSP have the authority to access the virtual storage space corresponding to the information in the virtual storage space.

402. Obtain the data to be processed from the virtual storage space corresponding to the information in the virtual storage space.

After receiving the data processing instruction from the CPU, the DSP obtains the data to be processed from the virtual storage space corresponding to the information in the virtual storage space. The virtual storage space corresponding to the information in the virtual storage space corresponds to the first cache space in the cache of the electronic device, and both the CPU and the DSP have the authority to access the cache of the electronic device. Therefore, the DSP obtains the data to be processed from the first buffer space corresponding to the information in the virtual storage space. In the case that the corresponding relationship between the position indication information of the first cache space and the base address of the virtual storage space is established by the CPU, the DSP can first obtain the position indication information corresponding to the information of the virtual storage space, and then correspond to the position indication information To obtain the data to be processed in the first buffer space. In the case that the corresponding relationship between the position indication information of the first buffer space and the base address of the virtual storage space is established by the buffer, the DSP can directly send the data acquisition request carrying the information of the virtual storage space to the buffer, and the buffer After receiving the data acquisition request from the DSP, obtain the position indication information corresponding to the information of the virtual storage space according to the information of the virtual storage space and the corresponding relationship between the position indication information and the information of the virtual storage space, and obtain the position indication information corresponding to the information of the position indication information from the position indication information corresponding to the position indication information. A buffer space acquires the data to be processed, and then returns the data to be processed to the DSP.

403. Process the data to be processed.

After the DSP obtains the data to be processed from the virtual storage space corresponding to the information in the virtual storage space, the data to be processed is processed. The processing of the data to be processed may include convolution processing, and may also include other processing such as full connection processing.

404. Store the processing result of the to-be-processed data in a first buffer space corresponding to the information in the virtual storage space.

After the DSP processes the data to be processed, the processing result of the data to be processed can be stored in the first buffer space corresponding to the information in the virtual storage space. A storage instruction can be sent to the register, and the storage instruction carries the processing result and the information of the virtual storage space. After the buffer receives the storage instruction from the DSP, it stores the processing result in the first buffer space.

After the DSP stores the processing result of the data to be processed in the first buffer space corresponding to the information in the virtual storage space, it can send a processing completion response message to the CPU so that the CPU can obtain the processing result from the buffer, thereby clearing the buffer in the buffer in time space.

In the information processing method described in FIG. 4, the DSP can obtain and process data from the virtual storage space at one time through the information in the virtual storage space, thereby improving the efficiency of data processing.

Please refer to FIG. 5, which is a schematic flowchart of another information processing method according to an embodiment of the present invention. Among them, the information processing method is described from the perspective of CPU and DSP. As shown in FIG. 5, the information processing method may include the following steps.

501. The CPU obtains data to be processed.

Wherein, step 501 is the same as step 201. For detailed description, please refer to step 201, which will not be repeated here.

502. The CPU determines the size of the storage space required for the data to be processed.

Among them, step 502 is the same as step 302. For detailed description, please refer to step 302, which will not be repeated here.

503. The CPU sends a request for applying for cache space to the cache.

After the CPU determines the size of the storage space required for the data to be processed, it can send a request for applying for cache space to the register. The request carries information about the size of the storage space required for the data to be processed.

504. The buffer sends location indication information of the first buffer space to the CPU.

After receiving the request from the CPU, the buffer selects the first buffer space from the free buffer space according to the size of the storage space corresponding to the information, and then sends the position indication information of the first buffer space to the CPU. For example, sending an indicator to the CPU to indicate the base address of the first cache space.

505. The CPU determines a physical storage address corresponding to the virtual storage space based on the location indication information.

After determining the storage space required for the data to be processed, the CPU can allocate virtual storage space for the data to be processed according to the storage space required for the data to be processed, such as the offset of the data in the virtual storage space. Wherein, the offset can be the offset of the data of each array in the virtual storage space, or the offset of the data of each array and its corresponding result data. The offset is determined relative to the base address of the virtual storage space. For other related descriptions, reference may be made to the above-mentioned embodiment.

After receiving the location indication information from the register, the physical storage address corresponding to the virtual storage space can be determined based on the location indication information, that is, the base address of the virtual storage space is determined, so as to determine the actual storage location of the data to be processed.

506. The CPU stores the to-be-processed data in the virtual storage space, that is, in the first buffer space indicated by the position indication information.

Wherein, step 506 is similar to step 203. For detailed description, please refer to step 203, which will not be repeated here.

507. The CPU sends a data processing instruction carrying information of the virtual storage space to the DSP.

Correspondingly, the DSP receives data processing instructions from the CPU.

Wherein, step 507 is the same as step 204. For detailed description, please refer to step 204, which will not be repeated here.

Wherein, the data processing instruction received by the DSP from the CPU is the same as step 401. For detailed description, please refer to step 401, which is not repeated here.

508. The DSP obtains the data to be processed from the first buffer space corresponding to the information in the virtual storage space.

Wherein, step 508 is similar to step 402. For detailed description, please refer to step 402, which will not be repeated here.

509. The DSP processes the data to be processed.

Among them, step 509 is the same as step 403. For detailed description, please refer to step 403, which will not be repeated here.

510. The DSP stores the processing result of the data to be processed in the first buffer space corresponding to the information in the virtual storage space.

Wherein, step 510 is the same as step 404. For detailed description, please refer to step 404, which will not be repeated here.

In some embodiments of the present invention, the CPU is responsible for analyzing the neural network model and calculating the space required by each array related to the data processing of the neural network model. The CPU applies for space (ie, virtual storage space) from a virtual heap according to the calculated space size. The result returned by applying for space here is not a usual indicator, but an offset relative to the base address of the heap. After the space application is completed, the CPU counts the total amount of space required, and allocates space corresponding to the total size on the ION Buffer to obtain the actual base address. Then, the CPU writes the relevant parameters and data required to run the neural network model into the virtual storage space that is applied for, that is, the space that corresponds to the virtual space allocated on the ION Buffer and the specific write address It can be calculated by base address and offset. Then, the CPU initiates a FastRPC call, and passes this virtual storage space to the DSP through FastRPC. In this way, both the CPU and the DSP can share the virtual storage space. Then, the DSP can parse the data in the ION Buffer according to the address information of the virtual storage space, and start the calculation, store the calculation result in the corresponding location of the space, and return it to the CPU.

In this way, only one FastRPC call is made in the entire data processing process, and only an array related to the virtual storage space is passed in this call, thereby minimizing additional extras while meeting the requirements of the FastRPC call Overhead.

Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of an information processing apparatus according to an embodiment of the present invention. As shown in FIG. 6, the information processing device may include: an acquiring unit 601 for acquiring data to be processed; an allocating unit 602 for allocating virtual storage space for the data to be processed; and a storage unit 603 for storing the data to be processed To the virtual storage space; the sending unit 604 is used to send a data processing instruction carrying information of the virtual storage space to the DSP. The data processing instruction is used by the DSP to obtain the data to be processed from the virtual storage space corresponding to the information in the virtual storage space and the data to be processed To process.

In some embodiments, the virtual storage space corresponds to the first buffer space in the buffer of the electronic device; the storage unit 603 is specifically configured to store the data to be processed in the first buffer space; the DSP corresponds to the information from the virtual storage space Obtaining the data to be processed by the virtual storage space includes: the DSP acquires the data to be processed from the first buffer space corresponding to the information in the virtual storage space.

In some embodiments, the allocating unit 602 is specifically configured to: apply for a buffer space from the buffer of the electronic device based on the size of the storage space required by the data to be processed; and to indicate information based on the location of the first buffer space returned by the buffer of the electronic device To determine the physical storage location of the virtual storage space.

In some embodiments, the data to be processed includes at least one array, and each array includes data of the same type. The information processing device may further include: a determining unit 605 configured to determine the data of each array in the at least one array. The required storage space size is determined based on the storage space required by each array in the at least one array.

In some embodiments, the determining unit 605 is further configured to determine the offset of each array in the at least one array in the virtual storage space according to the size of the storage space required by each array in the at least one array.

In some embodiments, the determining unit 605 is configured to determine the amount of storage space required for the data to be processed based on the data volume of the data to be processed and the result data volume corresponding to the data to be processed.

In some embodiments, the allocating unit 602 applies for buffer space from the buffer of the electronic device based on the size of the storage space required by the data to be processed, including: sending a request for applying for buffer space to the buffer of the electronic device, and the request carries the buffer to be processed. Information on the size of storage space required for processing data; receiving position indication information from the register, and the position indication information is used to indicate the base address of the first cache space.

In some embodiments, the data to be processed are network parameters and input data of the network layer in the neural network.

This embodiment may correspond to the description of the method embodiment in the embodiment of the application, and the above and other operations and/or functions of each unit are used to implement the corresponding processes in each method in FIG. 2 and FIG. 3 respectively. For the sake of brevity, it is not here. Go into details again.

Please refer to FIG. 7, which is a schematic structural diagram of another information processing device provided by an embodiment of the present invention. As shown in FIG. 7, the information processing device may include: a receiving unit 701 for receiving data processing instructions from the CPU, the data processing instructions carrying information in the virtual storage space; an acquiring unit 702, for corresponding information from the virtual storage space The virtual storage space of ”obtains the data to be processed; the processing unit 703 is used to process the data to be processed.

In some embodiments, the virtual storage space corresponding to the information in the virtual storage space corresponds to the first cache space in the register of the electronic device; the obtaining unit 702 is specifically configured to obtain the first cache space corresponding to the information in the virtual storage space Pending data.

In some embodiments, the information processing apparatus may further include: a storage unit 704, configured to store the processing result of the data to be processed in the first buffer space corresponding to the information in the virtual storage space.

In some embodiments, the data to be processed are network parameters and input data of the network layer in the neural network.

This embodiment may correspond to the description of the method embodiment in the embodiment of the present application, and the above and other operations and/or functions of each unit are used to implement the corresponding process in each method in FIG. 4, and are not repeated here for brevity.

Please refer to FIG. 8. FIG. 8 is a schematic structural diagram of another information processing device according to an embodiment of the present invention. The information processing device can implement various functions of the CPU in the electronic device shown in FIG. 1. As shown in FIG. 8, the information processing device may include: at least one processor 801, such as a CPU, a transceiver 802, and at least one bus 803. The bus 803 is used to realize the connection and communication between these components.

In some embodiments, the processor 801 is used to perform the following operations: obtain data to be processed; allocate virtual storage space for the data to be processed; store the data to be processed in the virtual storage space; The data processing instructions of the information in the storage space are used by the DSP to obtain the data to be processed from the virtual storage space corresponding to the information in the virtual storage space and process the data to be processed.

In some embodiments, the virtual storage space corresponds to the first cache space in the electronic device cache; the processor 801 storing the to-be-processed data in the virtual storage space includes: storing the to-be-processed data in the first cache space; and the DSP from the virtual storage Obtaining the data to be processed by the virtual storage space corresponding to the information of the space includes: the DSP acquires the data to be processed from the first buffer space corresponding to the information of the virtual storage space.

In some embodiments, the processor 801 allocating virtual storage space for the data to be processed includes: requesting a buffer space from the buffer of the electronic device based on the storage space required by the data to be processed; The location indication information of the cache space determines the physical storage location of the virtual storage space.

In some embodiments, the data to be processed includes at least one array, and each array includes data of the same type. The processor 801 is further configured to perform the following operations: determine the storage space required by each array in the at least one array; Based on the storage space required by each array in the at least one array, the storage space required by the data to be processed is determined.

In some embodiments, the processor 801 is further configured to perform the following operations: determine the deviation of each array in the at least one array in the virtual storage space according to the size of the storage space required by each array in the at least one array. Shift.

In some embodiments, the processor 801 is further configured to perform the following operations: based on the data volume of the data to be processed and the result data volume corresponding to the data to be processed, determine the size of the storage space required for the data to be processed.

In some embodiments, the processor 801 applies for cache space from the cache of the electronic device based on the size of the storage space required by the data to be processed includes: sending a request for applying for cache space to the cache of the electronic device, and the request carries Information on the size of the storage space required for the data to be processed; receiving position indication information from the buffer, and the position indication information is used to indicate the base address of the first buffer space.

In some embodiments, the data to be processed are network parameters and input data of the network layer in the neural network.

Among them, step 201-step 203, step 301-step 304, and step 501-step 504 can be executed by the processor 801 in the CPU, and step 204, step 305, and step 505 can be executed by the transceiver 802 in the CPU.

The acquisition unit 601, the distribution unit 602, the storage unit 603, and the determination unit 605 can be implemented by the processor 801 in the CPU, and the sending unit 604 can be implemented by the transceiver 802 in the CPU.

The above-mentioned information processing device can also be used to execute various methods executed in the foregoing method embodiments, and details are not described herein again.

In other embodiments, the information processing apparatus can implement various functions of the DSP in the electronic device shown in FIG. 1. Wherein: the transceiver 802 is used to receive data processing instructions from the CPU, and the data processing instructions carry information in the virtual storage space; the processor 801 is used to perform the following operations: obtain the data to be processed from the virtual storage space corresponding to the information in the virtual storage space ; Process the data to be processed.

In some embodiments, the virtual storage space corresponding to the information in the virtual storage space corresponds to the first cache space in the register of the electronic device; the processor 801 obtaining the data to be processed from the virtual storage space corresponding to the information in the virtual storage space includes: Obtain the to-be-processed data from the first cache space corresponding to the information in the virtual storage space.

In some embodiments, the processor 801 is further configured to perform the following operations: store the processing result of the data to be processed in the first buffer space corresponding to the information in the virtual storage space.

In some embodiments, the data to be processed are network parameters and input data of the network layer in the neural network.

Among them, steps 402 to 404 and steps 506 to 508 can be executed by the processor 801, and the steps of receiving data processing instructions in step 204, step 305, and step 505 and step 401 can be executed by the transceiver 802.

Among them, the acquiring unit 702, the processing unit 703, and the storage unit 704 may be implemented by the processor 801, and the receiving unit 701 may be implemented by the transceiver 802.

The above-mentioned information processing device can also be used to execute various methods executed in the foregoing method embodiments, and details are not described herein again.

In some embodiments, a computer-readable recording medium is provided, and the computer-readable recording medium is used to store an application program, and the application program is used to execute the information processing method of FIGS. 2 to 4 during operation.

In some embodiments, an application program is provided, and the application program is used to execute the information processing method of FIG. 2 to FIG. 4 at runtime.

Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above-mentioned embodiments can be completed by programming related hardware. The program can be stored in a computer-readable storage device. The storage device can include: portable Disk, ROM, RAM, floppy disk or CD-ROM, etc.

101: CPU 102: DSP 103: buffer 201~204,301~305,401~404,501~510: steps 601, 702: acquisition unit 602: Allocation Unit 603,704: storage unit 604: sending unit 605: Determine Unit 701: receiving unit 703: Processing Unit 801: processor 802: Transceiver 803: Bus

Fig. 1 is a schematic diagram of an electronic device provided by an embodiment of the present invention. FIG. 2 is a schematic flowchart of an information processing method provided by an embodiment of the present invention. FIG. 3 is a schematic flowchart of another information processing method provided by an embodiment of the present invention. FIG. 4 is a schematic flowchart of yet another information processing method provided by an embodiment of the present invention. FIG. 5 is a schematic flowchart of yet another information processing method provided by an embodiment of the present invention. FIG. 6 is a schematic structural diagram of an information processing device provided by an embodiment of the present invention. FIG. 7 is a schematic structural diagram of another information processing device provided by an embodiment of the present invention. FIG. 8 is a schematic structural diagram of another information processing device provided by an embodiment of the present invention.

201~204: Steps

Claims (17)

An information processing method, including: The central processing unit (CPU) obtains the data to be processed; Allocating virtual storage space for the to-be-processed data; Storing the to-be-processed data in the virtual storage space; Send a data processing instruction carrying information of the virtual storage space to a digital signal processor (DSP), where the data processing instruction is used by the DSP to obtain the to-be-processed data from the virtual storage space corresponding to the information and perform State the data to be processed for processing. The method according to claim 1, wherein the virtual storage space corresponds to the first buffer space in the buffer of the electronic device to which the CPU belongs; The step of storing the to-be-processed data in the virtual storage space includes: Storing the data to be processed in the first buffer space by the CPU; The step of obtaining the data to be processed by the DSP from the virtual storage space corresponding to the information includes: The DSP obtains the to-be-processed data from the first buffer space corresponding to the information. The method according to claim 2, wherein the step of allocating the virtual storage space for the to-be-processed data includes: Based on the size of the storage space required by the to-be-processed data, apply for a buffer space from the buffer of the electronic device; The physical storage location of the virtual storage space is determined based on the location indication information of the first buffer space returned by the buffer of the electronic device. The method according to claim 3, wherein the step of applying for the buffer space from the buffer of the electronic device based on the size of the storage space required by the data to be processed includes: Sending a request for applying for a buffer space to the buffer of the electronic device, the request carrying information about the size of the storage space required for the data to be processed; Receiving position indication information from the buffer, where the position indication information is used to indicate the base address of the first buffer space. The method according to any one of Claims 1 to 3, wherein the data to be processed includes at least one array, and each array includes data of the same type, and the method further includes: Determining the size of storage space required by each array in the at least one array; Based on the storage space required by each array in the at least one array, the storage space required by the to-be-processed data is determined. The method according to claim 5, wherein the method further includes: Determine the offset of each array in the at least one array in the virtual storage space according to the size of the storage space required by each array in the at least one array. The method according to any one of claims 1 to 3, wherein the method further comprises: Based on the data volume of the data to be processed and the result data volume corresponding to the data to be processed, the size of the storage space required for the data to be processed is determined. The method according to any one of claim items 1-7, wherein the data to be processed includes network parameters and input data of the target network layer in the neural network model. An information processing method, including: A digital signal processor (DSP) receives data processing instructions from a central processing unit (CPU), and the data processing instructions carry information in the virtual storage space; Obtain the to-be-processed data from the virtual storage space corresponding to the information; The processing operation indicated by the data processing instruction is performed on the data to be processed. The method according to claim 9, wherein the virtual storage space corresponding to the information corresponds to the first buffer space in the buffer of the electronic device to which the CPU belongs; The operation of obtaining to-be-processed data from the virtual storage space corresponding to the information includes: Obtain the data to be processed from the first buffer space corresponding to the information. The method according to claim 9 or 10, wherein the method further includes: The processing result of the to-be-processed data is stored in the first buffer space corresponding to the information. The method according to any one of claims 9-11, wherein the data to be processed are network parameters and input data of the target network layer in the neural network model. An information processing device includes: The obtaining unit is used to obtain the data to be processed; An allocation unit for allocating virtual storage space for the to-be-processed data; A storage unit for storing the to-be-processed data in the virtual storage space; The sending unit is configured to send a data processing instruction carrying information of the virtual storage space to a digital signal processor (DSP), and the data processing instruction is used by the DSP to obtain the waiting information from the virtual storage space corresponding to the information. Process the data and process the to-be-processed data. An information processing device includes: The receiving unit is configured to receive a data processing instruction from a central processing unit (CPU), the data processing instruction carrying information of the virtual storage space; The obtaining unit is used to obtain the data to be processed from the virtual storage space corresponding to the information; The processing unit is used to process the data to be processed. An information processing device includes a processor and a storage device, the storage device is used to store computer instructions, and the processor is used to call the computer instructions stored in the storage device to execute any one of claims 1-12 Information processing methods. An electronic device includes the information processing device described in claim 13 and the information processing device described in claim 14. A computer-readable recording medium, the computer-readable recording medium stores a computer program, and when the computer program is executed by a processor, the information processing method according to any one of claim items 1-12 is realized.

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