CN105335309B - A kind of data transmission method and computer - Google Patents
A kind of data transmission method and computer Download PDFInfo
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- CN105335309B CN105335309B CN201410240221.6A CN201410240221A CN105335309B CN 105335309 B CN105335309 B CN 105335309B CN 201410240221 A CN201410240221 A CN 201410240221A CN 105335309 B CN105335309 B CN 105335309B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The embodiment of the invention discloses a kind of data transmission method and computers, are related to field of computer technology, it is possible to reduce CPU, bus resource and memory source occupy, and then can improve data transmission efficiency.Concrete scheme is：DMA data access request is sent to CPU by the first component after the DMA data access request for receiving the mark comprising data to be read；CPU obtains the memory address information of data to be read according to the mark of data to be read after receiving DMA data access request；The memory address information of data to be read is sent to the first component by CPU；The first component obtains data to be read according to the memory address information of data to be read by DDA engines from second component.During the present invention carries out immediate data transmission for the first equipment and the second equipment.
Description
Technical field
The present invention relates to field of computer technology more particularly to a kind of data transmission methods and computer.
Background technology
Web application refer to the language development supported using browser, run on it is on various browsers and internet,
It may be done to the application of a few specific function.During the use of Web applications, exist between disk and network interface card a large amount of
Using data transmission, data flow direction includes the application data transmission from disk to network interface card, or answering from network interface card to disk
Use data transmission.Wherein, central processing unit (Central Processing Unit, CPU) carries out applying number in disk and network interface card
The function of forwarding and encapsulated data packet is played during according to transmission.
Specifically, by taking process of the application data by disk transfers to network interface card as an example, will apply data by disk transfers extremely
During network interface card, CPU needs read data to be read from disk in kernel mode, by data copy to be read to kernel
In address space buffer area 1 (first time data copy), then also need to data to be read from kernel address space buffer area
It copies user address space buffer area (second of data copy) to, then data to be read is copied from user address space buffer area
It, then can be empty from kernel address by data to be read in shellfish to kernel address space buffer area 2 (third time data copy)
Between buffer area 2 be transmitted to network interface card.
In above-mentioned data transmission procedure, the number that CPU carries out data copy is more, largely occupies cpu bus resource
And memory source, data transmission it is less efficient.
Invention content
The embodiment of the present invention provides a kind of data transmission method and computer, it is possible to reduce cpu bus resource and interior
Resource occupation is deposited, and then data transmission efficiency can be improved.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that：
The embodiment of the present invention in a first aspect, provide a kind of data transmission method, the method is applied in computer, institute
It includes central processor CPU, memory, the first component and second component to state computer, is drawn configured with DDA in the first component
It holds up, the method includes：
The first component receives direct memory access DMA data access request, and the DMA data access request includes waiting for
Read the mark of data；
The DMA data access request is sent to the CPU by the first component；
The CPU is after receiving the DMA data access request, according to the acquisition of the mark of the data to be read
The memory address information of data to be read；The memory address information of the data to be read is used to indicate in the memory for protecting
Deposit the address of the transport addresses information of the data to be read, the transport addresses informations of the data to be read is used to indicate described
Address in second component for preserving the data to be read；
The memory address information of the data to be read is sent to the first component by the CPU；
The first component is by the DDA engines, according to the memory address information of the data to be read, from described
The data to be read are obtained in two components.
With reference to first aspect, in one possible implementation, the memory include the first virtual buffer unit and
Second virtual buffer unit, wherein the read-write mode of the first virtual buffer unit is corresponding with the second component, and described
The read-write mode of two virtual buffer units is corresponding with the first component, and the method further includes：
The CPU sends the address of the first virtual buffer unit after receiving the DMA data access request
With the mark of the data to be read to the second component；
The second component is according to the mark of the address and the data to be read of the first virtual buffer unit, by institute
The first virtual buffer unit is written in the transport addresses information for stating data to be read；
The CPU reads the transport addresses information of the data to be read from the first virtual buffer unit, and will
The second virtual buffer unit is written in the transport addresses information of the data to be read；
The memory address information of the data to be read is sent to the first component by the CPU, including：
The address of the second virtual buffer unit is sent to the first component by the CPU.
With reference to first aspect with above-mentioned possible realization method, in alternatively possible realization method, described first
Part is by the DDA engines, and according to the memory address information of the data to be read, described wait for is obtained from the second component
Data are read, including：
The first component is obtained according to the address of the second virtual buffer unit from the second virtual buffer unit
Obtain the transport addresses information of the data to be read；
The first component is by the DDA engines, according to the instruction of the transport addresses information of the data to be read, from
The data to be read are read in the second component.
With reference to first aspect with above-mentioned possible realization method, in alternatively possible realization method, described by institute
The transport addresses information for stating data to be read is written before the second virtual buffer unit, and the method further includes：
The CPU is that the transport addresses information for the data to be read being stored in the first virtual buffer unit adds
Add descriptor, to generate descriptor message, wherein the descriptor is used to identify the transmission address letter of the data to be read
Breath；
The second virtual buffer unit is written in the transport addresses information of the data to be read by the CPU, including：
The second virtual buffer unit is written in the descriptor message by the CPU.
With reference to first aspect with above-mentioned possible realization method, in alternatively possible realization method, described first
Part is network interface card, and the second component is disk；
Alternatively, the first component is the disk, the second component is the network interface card.
The second aspect of the embodiment of the present invention also provides a kind of computer, including：Central processor CPU, memory, first
Component and second component are configured with DDA engines in the first component；
The first component, for receiving direct memory access DMA data access request, the DMA data access request
Include the mark of data to be read；The DMA data access request is sent to the CPU；
The CPU, for after receiving the DMA data access request, being obtained according to the mark of the data to be read
Take the memory address information of the data to be read；The memory address information of the data to be read is used to indicate in the memory
Address for the transport addresses information for preserving the data to be read, the transport addresses information of the data to be read is for referring to
Show the address for preserving the data to be read in the second component；The memory address information of the data to be read is sent out
It send to the first component；
The first component is additionally operable to receive the memory address information of the data to be read, by the DDA engines,
According to the memory address information of the data to be read received from the CPU, described continue is obtained from the second component
Access evidence.
In conjunction with second aspect, in one possible implementation, the memory include the first virtual buffer unit and
Second virtual buffer unit, wherein the read-write mode of the first virtual buffer unit is corresponding with the second component, and described
The read-write mode of two virtual buffer units is corresponding with the first component；
The CPU is additionally operable to after receiving the DMA data access request, by the first virtual buffer unit
The mark of address and the data to be read is sent to the second component；
The second component is used for the mark of the address and the data to be read according to the first virtual buffer unit
Know, the first virtual buffer unit is written into the transport addresses information of the data to be read；
The CPU is additionally operable to read the transmission address letter of the data to be read from the first virtual buffer unit
Breath, and the second virtual buffer unit is written into the transport addresses information of the data to be read；It is virtual slow by described second
The address for rushing unit is sent to the first component.
In conjunction with second aspect and above-mentioned possible realization method, in alternatively possible realization method, described first
Part is additionally operable to the address according to the second virtual buffer unit, and described continue is obtained from the second virtual buffer unit
The transport addresses information for evidence of fetching；By the DDA engines, according to the instruction of the transport addresses information of the data to be read,
The data to be read are read from the second component.
In conjunction with second aspect and above-mentioned possible realization method, in alternatively possible realization method, the CPU, also
For for be stored in the data to be read in the first virtual buffer unit transport addresses information add descriptor, with
Generate descriptor message；The second virtual buffer unit is written into the descriptor message；
Wherein, the descriptor is used to identify the transport addresses information of the data to be read.
In conjunction with second aspect and above-mentioned possible realization method, in alternatively possible realization method, described first
Part is network interface card, and the second component is disk；
Alternatively, the first component is the disk, the second component is the network interface card.
Data transmission method and computer provided in an embodiment of the present invention, the first component include data to be read receiving
Mark DMA data access request after, DMA data access request is sent to CPU；CPU receive DMA data access ask
After asking, the memory address information of data to be read is obtained according to the mark of data to be read；The memory address of data to be read is believed
Breath is used to indicate the address of the transport addresses information for preserving data to be read in memory, the transmission address letter of data to be read
Breath is used to indicate the address for preserving data to be read in second component；CPU sends out the memory address information of data to be read
It send to the first component；The first component is obtained according to the memory address information of data to be read from second component by DDA engines
Obtain data to be read.
With in the prior art, cpu bus resource caused by a large amount of Data Migration and memory provide in data transmission procedure
Source occupy it is larger compares, by this programme, CPU is during the first component and second component carry out data transmission, only the
One component and second component provide the forwarding capability of the storage address of data to be transmitted, do not transmit data to be transmitted directly, can
To reduce the data volume of transmission, and then cpu bus resource and memory source occupancy can be reduced, and then data biography can be improved
Defeated efficiency.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention without having to pay creative labor, may be used also for those of ordinary skill in the art
With obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of data transmission method flow chart in the embodiment of the present invention 1；
Fig. 2 is a kind of data transmission method flow chart in the embodiment of the present invention 2；
Fig. 3 is a kind of composition schematic diagram of computer in the embodiment of the present invention 3；
Fig. 4 is the composition schematic diagram of another computer in the embodiment of the present invention 3.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In addition, the terms " system " and " network " are often used interchangeably herein.The terms " and/
Or ", only a kind of incidence relation of description affiliated partner, indicates may exist three kinds of relationships, for example, A and/or B, it can be with table
Show：Individualism A exists simultaneously A and B, these three situations of individualism B.In addition, character "/" herein, typicallys represent front and back
Affiliated partner is a kind of relationship of "or".
Computer in the embodiment of the present invention can be PC (Personal Computer, PC), server, put down
Any one electronic computer product such as plate computer or mobile phone, the embodiment of the present invention do not limit the computer concrete form
System.
Specifically, the computer in the embodiment of the present invention may include central processing unit (Central Processing
Unit, CPU), memory, the first component and second component, be configured with DDA engines in the first component.Wherein, the embodiment of the present invention has
Body can be applied to during data to be read are transmitted to the first component by second component, i.e., the embodiment of the present invention specifically can be with
During data to be read being directly read applied to the first component from second component.
In the first scene of the embodiment of the present invention, the first component in the embodiment of the present invention can be in computer
Disk, second component can be the network interface card in computer, i.e. the embodiment of the present invention specifically can be applied to the disk in computer
During directly reading data to be read from the network interface card in the computer.
In second of scene of the embodiment of the present invention, the first component in the embodiment of the present invention can be in computer
Network interface card, second component can be the disk in computer, i.e. the embodiment of the present invention specifically can be applied to the network interface card in computer
During directly reading data to be read from the disk in the computer.
Embodiment 1
The embodiment of the present invention provides a kind of data transmission method, can be applied in computer, the computer include CPU,
Memory, the first component and second component, access configured with direct equipment in the first component (Direct Device Access,
DDA) engine；The embodiment of the present invention can be applied during first component transmission data direct to second component, such as Fig. 1 institutes
Show, which includes：
S101, the first component receive direct memory access (direct memory access, DMA) data access request,
DMA data access request includes the mark of data to be read.
Illustratively, the first component in the embodiment of the present invention is the disk in computer, and second component is in computer
Network interface card；Alternatively, the first component is the network interface card in computer, second component is the disk in computer.
DMA data access request is sent to CPU by S102, the first component.
Wherein, DMA data access request can be forwarded to by the first component after receiving DMA data access request
CPU, so that CPU is with obtaining the memory of data to be read according to the mark for the data to be read for including in DMA data access request
Location information, that is, execute S103：
S103, CPU obtain data to be read after receiving DMA data access request, according to the mark of data to be read
Memory address information.
Wherein, the memory address information of data to be read is used to indicate the transmission for preserving data to be read in memory
The address of location information, the transport addresses information of data to be read are used to indicate the ground in second component for preserving data to be read
Location.
Illustratively, the memory in the embodiment of the present invention may include the first virtual buffer unit and the second virtual buffer list
Member.Wherein, the read-write mode of the first virtual buffer unit is corresponding with second component, the read-write mode of the second virtual buffer unit with
The first component corresponds to.
Wherein, it is used in the second virtual buffer unit that the memory address information of data to be read is specifically used in instruction memory
In the address for the transport addresses information for preserving data to be read, i.e., the transport addresses information of data to be read preserves in memory
In second virtual buffer unit.
It should be noted that the transport addresses information of the data to be read preserved in the second virtual buffer unit is that CPU exists
After receiving the DMA data access request, instruction second component is empty by the transport addresses information write-in first of data to be read
Quasi- buffer cell, then the transport addresses information of data to be read will be from the first virtual buffer unit the second virtual buffer list of write-in
Member.
The memory address information of data to be read is sent to the first component by S104, CPU.
Wherein, CPU can will be used to indicate the address for the transport addresses information for being used to preserve data to be read in memory
Memory address information is sent to the first component, so that the first component can be by DDA engines, according to the memory of data to be read
Location information directly obtains data to be read from second component.
S105, the first component are obtained according to the memory address information of data to be read from second component by DDA engines
Obtain data to be read.
Illustratively, since the memory address information of data to be read is used to indicate in memory for preserving data to be read
Transport addresses information address, therefore, the first component can be according to the instruction of the memory address information of data to be read, from meter
The transport addresses information of data to be read is read in the memory of calculation machine；Since the transport addresses information of data to be read is used to indicate
Address in second component for preserving data to be read, and DDA engines have the computer for directly operating same CPU controls
The function of the memory of other component, therefore the first component can be by configuring the DDA engines in the first component, according to continuing
The instruction of the transport addresses information for evidence of fetching, directly reads data to be read from second component.
It should be noted that the first component and second component (i.e. disk and network interface card) in the embodiment of the present invention all can be
The external equipment for itself having processor function in computer.Processor in disk can be similar to the CPU in computer,
For the arithmetic core and control core of disk, disk can be controlled and read from the memory of computer or data are written, and controlled
It prepares the DDA engines set in disk and directly reads data to be read from network interface card；Processor in network interface card can be similar to meter
CPU in calculation machine is the arithmetic core and control core of network interface card, can control network interface card and read or write from the memory of computer
Enter data, and controls DDA engine of the configuration in network interface card and directly read data to be read from disk.
Data transmission method provided in an embodiment of the present invention, the first component are receiving the mark comprising data to be read
After DMA data access request, DMA data access request is sent to CPU；CPU is after receiving DMA data access request, root
The memory address information of data to be read is obtained according to the mark of data to be read；The memory address information of data to be read is for referring to
Show the address of the transport addresses information in memory for preserving data to be read, the transport addresses information of data to be read is for referring to
Show the address for preserving data to be read in second component；The memory address information of data to be read is sent to first by CPU
Component；The first component is obtained to be read by DDA engines according to the memory address information of data to be read from second component
Data.
With in the prior art, cpu bus resource caused by a large amount of Data Migration and memory provide in data transmission procedure
Source occupy it is larger compares, by this programme, CPU is during the first component and second component carry out data transmission, only the
One component and second component provide the forwarding capability of the storage address of data to be transmitted, do not transmit data to be transmitted directly, can
To reduce the data volume of transmission, and then cpu bus resource and memory source occupancy can be reduced, and then data biography can be improved
Defeated efficiency.
Embodiment 2
The embodiment of the present invention provides a kind of data transmission method, can be applied in computer, the computer include CPU,
Memory, the first component and second component include the first virtual buffer unit and the second virtual buffer unit, the first component in memory
In be configured with DDA engines；The embodiment of the present invention can be applied during first component transmission data direct to second component,
As shown in Fig. 2, the data transmission method includes：
S201, the first component receive DMA data access request, and DMA data access request includes the mark of data to be read.
Illustratively, in the first application scenarios of the embodiment of the present invention, the first component can be the magnetic in computer
Disk, second component can be the network interface card in computer.
In the first application scenarios, the first component receives DMA data access request and is specifically as follows：Disk reception comes from
The DMA system call request of application program, the DMA system call request be used to indicate disk from network interface card read network interface card in preserve
The data (data i.e. to be read) from network side.
In second of application scenarios of the embodiment of the present invention, the first component can be computer in network interface card, second
Part can be the disk in computer.
In second of application scenarios, the first component receives DMA data access request and is specifically as follows：Network interface card reception comes from
The DMA system call request of application program, the DMA system call request are used to indicate network interface card and are preserved from reading disk in disk
, the data (data i.e. to be read) to be passed for transporting to network side.
DMA data access request is sent to CPU by S202, the first component.
Wherein, the DMA data access request of the mark comprising data to be read can be sent to CPU by the first component, with
From the location information preserved in disk for obtaining data to be read from CPU.
It should be noted that CPU after receiving DMA data access request, can indicate that second component will be used to indicate
The transport addresses information of address in second component for preserving data to be read is stored in the memory of computer, in order to
CPU can notify the memory address letter for being used to indicate the address in memory for preserving the transport addresses information to the first component
Breath, in order to which the first component can read data to be read according to the memory address information of data to be read from second component.
Specifically, the method for the embodiment of the present invention can also include：
S203, CPU send and continue after receiving DMA data access request, by the address of the first virtual buffer unit
The mark for evidence of fetching is to second component.
Wherein, the first virtual buffer unit in the embodiment of the present invention is the pseudo- buffer cell in main memory, and first is empty
The read-write mode of quasi- buffer cell is corresponding with second component, i.e. the reading of the read-write mode and second component of the first virtual buffer unit
WriteMode corresponds to.
It should be noted that the first virtual buffer unit can be CPU after receiving DMA data access request, configuration
Pseudo- buffer cell corresponding with the read-write mode of second component in computer hosting.
S204, second component are according to the mark of the address and data to be read of the first virtual buffer unit, and will continue access
According to transport addresses information be written the first virtual buffer unit.
Wherein, CPU sends the address transmission of the first virtual buffer unit and the mark of data to be read to second component, uses
Transport addresses information (the biography of data to be read of data to be read is obtained according to the mark of data to be read in instruction second component
Defeated address information is used to indicate the address for preserving data to be read in second component), then according to the first virtual buffer list
The first virtual buffer unit is written in the transport addresses information of data to be read by the address of member.
It should be noted that since the read-write mode of the first virtual buffer unit is corresponding with the read-write mode of second component,
Therefore, can directly the first virtual buffer unit be written in the transport addresses information of data to be read by second component.
Illustratively, in the first application scenarios of the embodiment of the present invention, second component can be the net in computer
Card, the read-write mode of the first virtual buffer unit are corresponding with the read-write mode of network interface card in computer.
In second of application scenarios of the embodiment of the present invention, second component can be the disk in computer, and first is empty
The read-write mode of quasi- buffer cell is corresponding with the read-write mode of disk in computer.
S205, CPU are the transport addresses information addition description for the data to be read being stored in the first virtual buffer unit
Symbol, to generate descriptor message.
Wherein, descriptor is used to identify the transport addresses information of data to be read.
In the first application scenarios of the embodiment of the present invention, the first component can be computer in disk, second
Part can be the network interface card in computer.
In the first application scenarios, CPU is the transmission of the data to be read being stored in the first virtual buffer unit
Location information addition descriptor is block descriptor.Wherein, block descriptor is used to identify the transport addresses information of data to be read, for
The first component (disk) identifies the transport addresses information of data to be read.
In second of application scenarios of the embodiment of the present invention, the first component can be computer in network interface card, second
Part can be the disk in computer.
In second of application scenarios, CPU is the transmission of the data to be read being stored in the first virtual buffer unit
Location information addition descriptor is Socket socket descriptors.Wherein, Socket socket descriptors are for identifying access of continuing
According to transport addresses information, the transport addresses information of data to be read is identified for the first component (network interface card).
S206, CPU read descriptor message from the first virtual buffer unit, and descriptor message write-in second is virtual
Buffer cell.
Wherein, the second virtual buffer unit in the embodiment of the present invention is the pseudo- buffer cell in main memory, and second is empty
The read-write mode of quasi- buffer cell is corresponding with the first component, i.e. the reading of the read-write mode and the first component of the second virtual buffer unit
WriteMode corresponds to.
It should be noted that the second virtual buffer unit can be CPU after receiving DMA data access request, configuration
Pseudo- buffer cell corresponding with the read-write mode of the first component in computer hosting；Alternatively, the second virtual buffer unit can
CPU is thought after detecting that the first virtual buffer unit is written in the transport addresses information of data to be read by second component, configuration
Pseudo- buffer cell corresponding with the read-write mode of the first component in computer hosting.
The address of second virtual buffer unit is sent to the first component by S207, CPU.
Wherein, the address of the second virtual buffer unit can be sent to the first component by CPU, in order to which the first component can be with
According to the address of the second virtual buffer unit, the transport addresses information of data to be read is obtained from the second virtual buffer unit,
And then data to be read are directly read from second component according to the transport addresses information of data to be read.
S208, the first component are continued according to the address of the second virtual buffer unit from the second virtual buffer unit
The transport addresses information for evidence of fetching.
Specifically, the first component can be according to the address of the second virtual buffer unit, in the second virtual buffer unit
The descriptor message for being added to descriptor is searched, descriptor message is then parsed to obtain data to be read according to the descriptor
Transport addresses information.
Wherein, the first component can be determined according to descriptor：In the data preserved in second virtual buffer unit, which
Data are descriptor message.
S209, the first component are by DDA engines, according to the instruction of the transport addresses information of data to be read, from second
Data to be read are read in part.
Wherein, the first component can then initiate DDA requests, control after the transport addresses information for getting data to be read
DDA engines processed carry out the other equipment (second component) in same bus domain according to the transport addresses information of data to be read
DDA memories are moved, i.e., data to be read are read from second component.
It should be noted that in computer systems, the CPU and external equipment of computer are (in such as embodiment of the present invention
The first component and second component) between be connected by bus (at present the mainstream bus of computer-internal be PCIe), that is, pass through one
Each external equipment in a bus system control computer.The first component and second component in the embodiment of the present invention is by calculating
The CPU of machine is controlled by the same bus system, i.e., the first component in the embodiment of the present invention and second component belong to same
One bus domain possesses identical bus domain addresses space, and therefore, the DDA engines of the first component can be known by the bus domain
Do not start the second component for there are DDA data-transformation facilities not equally, second component is then stored according to the direction of data to be read
In address directly and second component communication read data to be read from second component.
Illustratively, the first component reads the address of second component, this address can be used as bus domain addresses space (such as
PCIe domain addresses space) mapping, can also be equipment private room.
It should be noted that the DDA data-transformation facilities of the first component or second component are specifically as follows the first component
Or be provided in advance in second component dedicated for carrying out the register of the DDA data transmissions in the embodiment of the present invention, this is posted
Storage supports to possess the mutual access between the equipment (first component and second component) in identical bus domain addresses space.
Data transmission method provided in an embodiment of the present invention, the first component are receiving the mark comprising data to be read
After DMA data access request, DMA data access request is sent to CPU；CPU is after receiving DMA data access request, root
The memory address information of data to be read is obtained according to the mark of data to be read；The memory address information of data to be read is for referring to
Show the address of the transport addresses information in memory for preserving data to be read, the transport addresses information of data to be read is for referring to
Show the address for preserving data to be read in second component；The memory address information of data to be read is sent to first by CPU
Component；The first component is obtained to be read by DDA engines according to the memory address information of data to be read from second component
Data.
With in the prior art, cpu bus resource caused by a large amount of Data Migration and memory provide in data transmission procedure
Source occupy it is larger compares, by this programme, CPU is during the first component and second component carry out data transmission, only the
One component and second component provide the forwarding capability of the storage address of data to be transmitted, do not transmit data to be transmitted directly, can
To reduce the data volume of transmission, and then cpu bus resource and memory source occupancy can be reduced, and then data biography can be improved
Defeated efficiency.
Embodiment 3
Another embodiment of the present invention provides a kind of computer, as shown in figure 3, the computer includes：Central processing unit
CPU31, memory 32, the first component 33 and second component 34 are configured with DDA engines in the first component 33.
The first component 33, for receiving direct memory access DMA data access request, the DMA data access is asked
Seek the mark for including data to be read；The DMA data access request is sent to the CPU31.
The CPU31, for after receiving the DMA data access request, according to the mark of the data to be read
Obtain the memory address information of the data to be read；The memory address information of the data to be read is used to indicate the memory
The transport addresses information of the address of transport addresses information in 32 for preserving the data to be read, the data to be read is used
In the address for indicating to be used to preserve the data to be read in the second component 34；By the memory address of the data to be read
Information is sent to the first component 33.
The first component 33 is additionally operable to receive the memory address information of the data to be read, be drawn by the DDA
It holds up, according to the memory address information of the data to be read received from the CPU31, institute is obtained from the second component 34
State data to be read.
Further, as shown in figure 4, the memory 32 includes the first virtual buffer unit 321 and the second virtual buffer
Unit 322, wherein the read-write mode of the first virtual buffer unit 321 is corresponding with the second component 34, and described second is empty
The read-write mode of quasi- buffer cell 322 is corresponding with the first component 33.
The CPU31 is additionally operable to after receiving the DMA data access request, by the first virtual buffer unit
Address and the marks of the data to be read be sent to the second component 34.
The second component 34 is used for the address according to the first virtual buffer unit 321 and the data to be read
Mark, the first virtual buffer unit 321 is written into the transport addresses informations of the data to be read.
The CPU31 is additionally operable to the transmission of the data to be read is read from the first virtual buffer unit 321
Location information, and the second virtual buffer unit 322 is written into the transport addresses information of the data to be read；By described second
The address of virtual buffer unit 322 is sent to the first component 33.
Further, the first component 33 is additionally operable to the address according to the second virtual buffer unit 322, from institute
State the transport addresses information that the data to be read are obtained in the second virtual buffer unit 322；By the DDA engines, according to
The data to be read are read in the instruction of the transport addresses information of the data to be read from the second component 34.
Further, the CPU31 is additionally operable to continue described in being stored in the first virtual buffer unit 321
The transport addresses information for evidence of fetching adds descriptor, to generate descriptor message；The descriptor message is written described second
Virtual buffer unit 322.
Wherein, the descriptor is used to identify the transport addresses information of the data to be read.
Further, in a kind of application scenarios of the embodiment of the present invention, the first component 33 be network interface card, described second
Component 34 is disk.
Optionally, in another application scenarios of the embodiment of the present invention, the first component 33 is the disk, described
Second component 34 is the network interface card.
Computer provided in an embodiment of the present invention, the first component is in the DMA numbers for receiving the mark comprising data to be read
After access request, DMA data access request is sent to CPU；CPU is after receiving DMA data access request, according to continuing
The mark for evidence of fetching obtains the memory address information of data to be read；The memory address information of data to be read is used to indicate memory
In transport addresses information for preserving data to be read address, the transport addresses information of data to be read is used to indicate second
Address in component for preserving data to be read；The memory address information of data to be read is sent to the first component by CPU；The
One component obtains data to be read according to the memory address information of data to be read by DDA engines from second component.
With in the prior art, cpu bus resource caused by a large amount of Data Migration and memory provide in data transmission procedure
Source occupy it is larger compares, by this programme, CPU is during the first component and second component carry out data transmission, only the
One component and second component provide the forwarding capability of the storage address of data to be transmitted, do not transmit data to be transmitted directly, can
To reduce the data volume of transmission, and then cpu bus resource and memory source occupancy can be reduced, and then data biography can be improved
Defeated efficiency.
Through the above description of the embodiments, it is apparent to those skilled in the art that, for description
It is convenienct and succinct, only the example of the division of the above functional modules, in practical application, can as needed and will be upper
It states function distribution to be completed by different function modules, i.e., the internal structure of device is divided into different function modules, to complete
All or part of function described above.The specific work process of the system, apparatus, and unit of foregoing description, before can referring to
The corresponding process in embodiment of the method is stated, details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the module or
The division of unit, only a kind of division of logic function, formula that in actual implementation, there may be another division manner, such as multiple units
Or component can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute
Display or the mutual coupling, direct-coupling or communication connection discussed can be by some interfaces, device or unit
INDIRECT COUPLING or communication connection can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it can also
It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.Above-mentioned integrated list
The form that hardware had both may be used in member is realized, can also be realized in the form of SFU software functional unit.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can be stored in a computer read/write memory medium.Based on this understanding, technical scheme of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
It is each that equipment (can be personal computer, server or the second equipment etc.) or processor (processor) execute the present invention
The all or part of step of embodiment the method.And storage medium above-mentioned includes：USB flash disk, mobile hard disk, read-only memory
(ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD
Etc. the various media that can store program code.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of data transmission method, which is characterized in that the method is applied in computer, and the computer includes centre
Device CPU, memory, the first component and second component are managed, direct equipment is configured in the first component and accesses DDA engines, it is described
Method includes：
The first component receives direct memory access DMA data access request, and the DMA data access request includes to be read
The mark of data；
The DMA data access request is sent to the CPU by the first component；
The CPU continues after receiving the DMA data access request according to described in the acquisition of the mark of the data to be read
The memory address information for evidence of fetching；The memory address information of the data to be read is used to indicate in the memory for preserving institute
The address of the transport addresses information of data to be read is stated, the transport addresses information of the data to be read is used to indicate described second
Address in component for preserving the data to be read；
The memory address information of the data to be read is sent to the first component by the CPU；
The first component is by the DDA engines, according to the memory address information of the data to be read, from described second
The data to be read are obtained in part.
2. according to the method described in claim 1, it is characterized in that, the memory includes the first virtual buffer unit and second
Virtual buffer unit, wherein the read-write mode of the first virtual buffer unit is corresponding with the second component, and described second is empty
The read-write mode of quasi- buffer cell is corresponding with the first component, and the method further includes：
The CPU by the address of the first virtual buffer unit and described is waited for after receiving the DMA data access request
The mark for reading data is sent to the second component；
The second component is waited for according to the mark of the address and the data to be read of the first virtual buffer unit by described
The first virtual buffer unit is written in the transport addresses information for reading data；
The CPU reads the transport addresses information of the data to be read from the first virtual buffer unit, and will be described
The second virtual buffer unit is written in the transport addresses information of data to be read；
The memory address information of the data to be read is sent to the first component by the CPU, including：
The address of the second virtual buffer unit is sent to the first component by the CPU.
3. according to the method described in claim 2, it is characterized in that, the first component by the DDA engines, according to described
The memory address information of data to be read obtains the data to be read from the second component, including：
The first component obtains institute according to the address of the second virtual buffer unit from the second virtual buffer unit
State the transport addresses information of data to be read；
The first component is by the DDA engines, according to the instruction of the transport addresses information of the data to be read, from described
The data to be read are read in second component.
4. according to the method described in claim 2, it is characterized in that, in the transport addresses information by the data to be read
It is written before the second virtual buffer unit, the method further includes：
The CPU is that the transport addresses information addition for the data to be read being stored in the first virtual buffer unit is retouched
Symbol is stated, to generate descriptor message, wherein the descriptor is used to identify the transport addresses information of the data to be read；
The second virtual buffer unit is written in the transport addresses information of the data to be read by the CPU, including：
The second virtual buffer unit is written in the descriptor message by the CPU.
5. method according to any one of claim 1-3, which is characterized in that the first component is network interface card, described the
Two components are disk；
Alternatively, the first component is the disk, the second component is the network interface card.
6. a kind of computer, which is characterized in that including：Central processor CPU, memory, the first component and second component, described
In one component DDA engines are accessed configured with direct equipment；
The first component, for receiving direct memory access DMA data access request, the DMA data access request includes
The mark of data to be read；The DMA data access request is sent to the CPU；
The CPU, for after receiving the DMA data access request, institute to be obtained according to the mark of the data to be read
State the memory address information of data to be read；The memory address information of the data to be read, which is used to indicate in the memory, to be used for
The address of the transport addresses information of the data to be read is preserved, the transport addresses information of the data to be read is used to indicate institute
State the address for preserving the data to be read in second component；The memory address information of the data to be read is sent to
The first component；
The first component is additionally operable to receive the memory address information of the data to be read, by the DDA engines, according to
The memory address information of the data to be read received from the CPU obtains the access of continuing from the second component
According to.
7. computer according to claim 6, which is characterized in that the memory includes the first virtual buffer unit and
Two virtual buffer units, wherein the read-write mode of the first virtual buffer unit is corresponding with the second component, and described second
The read-write mode of virtual buffer unit is corresponding with the first component；
The CPU is additionally operable to after receiving the DMA data access request, by the address of the first virtual buffer unit
It is sent to the second component with the mark of the data to be read；
The second component is used for the mark of the address and the data to be read according to the first virtual buffer unit, will
The first virtual buffer unit is written in the transport addresses information of the data to be read；
The CPU is additionally operable to read the transport addresses information of the data to be read from the first virtual buffer unit, and
The second virtual buffer unit is written into the transport addresses information of the data to be read；By the second virtual buffer unit
Address be sent to the first component.
8. computer according to claim 7, which is characterized in that the first component is additionally operable to empty according to described second
The address of quasi- buffer cell, obtains the transport addresses information of the data to be read from the second virtual buffer unit；It is logical
The DDA engines are crossed, according to the instruction of the transport addresses information of the data to be read, from the second component described in reading
Data to be read.
9. computer according to claim 7, which is characterized in that the CPU is additionally operable to virtual to be stored in described first
The transport addresses information of the data to be read in buffer cell adds descriptor, to generate descriptor message；It is retouched described
It states symbol message and the second virtual buffer unit is written；
Wherein, the descriptor is used to identify the transport addresses information of the data to be read.
10. according to the computer described in any one of claim 6-8, which is characterized in that the first component is network interface card, described
Second component is disk；
Alternatively, the first component is the disk, the second component is the network interface card.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410240221.6A CN105335309B (en) | 2014-05-30 | 2014-05-30 | A kind of data transmission method and computer |
| PCT/CN2015/072670 WO2015180513A1 (en) | 2014-05-30 | 2015-02-10 | Data transmission method and computer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410240221.6A CN105335309B (en) | 2014-05-30 | 2014-05-30 | A kind of data transmission method and computer |
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| CN105335309B true CN105335309B (en) | 2018-09-11 |
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| WO2017177400A1 (en) * | 2016-04-13 | 2017-10-19 | 华为技术有限公司 | Data processing method and system |
| CN108363670B (en) | 2017-01-26 | 2020-07-14 | 华为技术有限公司 | Data transmission method, device, equipment and system |
| CN106844245B (en) * | 2017-02-17 | 2019-11-12 | 北京腾凌科技有限公司 | Data transmission method and device |
| CN110286995B (en) * | 2018-03-19 | 2022-02-25 | 北京兆易创新科技股份有限公司 | Data reading and writing method and device |
| CN109660455B (en) * | 2018-12-25 | 2021-06-22 | 中国南方电网有限责任公司 | Machine patrol data storage method, device, system, gateway equipment and storage medium |
| CN111107019A (en) * | 2019-12-29 | 2020-05-05 | 浪潮电子信息产业股份有限公司 | Data transmission method, device, equipment and computer readable storage medium |
| CN113688072B (en) * | 2020-05-19 | 2024-03-26 | 华为技术有限公司 | Data processing method and device |
| CN114090273A (en) * | 2020-07-30 | 2022-02-25 | 华为技术有限公司 | Method and device for interprocess communication and computer storage medium |
| CN114302394B (en) * | 2021-11-19 | 2023-11-03 | 深圳震有科技股份有限公司 | Network direct memory access method and system under 5G UPF |
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| US20100125695A1 (en) * | 2008-11-15 | 2010-05-20 | Nanostar Corporation | Non-volatile memory storage system |
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| CN103793342B (en) * | 2012-11-02 | 2017-02-08 | 中兴通讯股份有限公司 | Multichannel direct memory access (DMA) controller |
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| US4400778A (en) * | 1979-11-05 | 1983-08-23 | Litton Resources Systems, Inc. | Large-volume, high-speed data processor |
| CN1794214A (en) * | 2005-12-22 | 2006-06-28 | 北京中星微电子有限公司 | Method of direct storage access for non-volatibility storage and its device |
| CN101136817A (en) * | 2006-09-20 | 2008-03-05 | 中兴通讯股份有限公司 | Data transmission control method of ethernet chip |
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| CN105335309A (en) | 2016-02-17 |
| WO2015180513A1 (en) | 2015-12-03 |
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