TW202002504A - Operational amplifier device with enhanced output voltage response capable of making output voltage more rapidly achieving stable voltage value to enhance output voltage response - Google Patents
Operational amplifier device with enhanced output voltage response capable of making output voltage more rapidly achieving stable voltage value to enhance output voltage response Download PDFInfo
- Publication number
- TW202002504A TW202002504A TW107119682A TW107119682A TW202002504A TW 202002504 A TW202002504 A TW 202002504A TW 107119682 A TW107119682 A TW 107119682A TW 107119682 A TW107119682 A TW 107119682A TW 202002504 A TW202002504 A TW 202002504A
- Authority
- TW
- Taiwan
- Prior art keywords
- operational amplifier
- voltage
- terminal
- resistor
- electrically connected
- Prior art date
Links
- 230000004044 response Effects 0.000 title claims description 10
- 230000003321 amplification Effects 0.000 claims description 27
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 27
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 230000000630 rising effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Landscapes
- Amplifiers (AREA)
Abstract
Description
本發明是有關於一種運算放大裝置,特別是指一種具提升輸出電壓響應之運算放大裝置。The invention relates to an operational amplifier device, in particular to an operational amplifier device with improved output voltage response.
參閱圖1,習知運算放大裝置1用來將一輸入電壓vi進行放大,以產生一輸出電壓vo。然而,該輸出電壓vo會受一電阻器11及一電容器12的一時間常數τ影響,而造成該輸出電壓vo的一電壓值要經過一延遲時間後才會到達一穩定電壓值。Referring to FIG. 1, the conventional
舉例來說,當電阻器11、13各自的一電阻值為10k歐姆,該電容器12的一電容值為0.01u法拉時,根據該運算放大裝置1所得之模擬結果如圖2所示。從圖2可得知,當該輸入電壓vi由0V上升至5V時,該輸出電壓vo會延遲約500us才由0V上升至5V(即,該延遲時間約為500us,該穩定電壓值為5V)。因此,如何設計出可縮短該延遲時間以提升該輸出電壓vo響應之運算放大裝置為相關業者所致力的目標之一。For example, when a resistance value of each of the
因此,本發明的目的,即在提供一種可提升輸出電壓響應的運算放大裝置。Therefore, the object of the present invention is to provide an operational amplifier device that can improve the output voltage response.
於是,本發明運算放大裝置包含一放大單元、一電流補償單元,及一運算放大單元。Therefore, the operational amplification device of the present invention includes an amplification unit, a current compensation unit, and an operational amplification unit.
該放大單元接收一輸出電壓,並將該輸出電壓放大以產生一放大電壓。The amplifier unit receives an output voltage and amplifies the output voltage to generate an amplified voltage.
該電流補償單元用於接收一輸入電壓,且電連接該放大單元以接收該放大電壓,並根據該放大電壓及該輸入電壓調整並產生一補償電流。The current compensation unit is used to receive an input voltage, and is electrically connected to the amplification unit to receive the amplified voltage, and adjusts and generates a compensation current according to the amplified voltage and the input voltage.
該運算放大單元用於接收該輸入電壓,且電連接該放大單元及該電流補償單元,接收來自該電流補償單元的該補償電流,並根據該輸入電壓及該補償電流調整並產生該輸出電壓,且將該輸出電壓輸出至該放大單元,該輸出電壓上升的速度相關於該補償電流的一電流值。The operational amplifier unit is used to receive the input voltage, and is electrically connected to the amplifier unit and the current compensation unit, receives the compensation current from the current compensation unit, and adjusts and generates the output voltage according to the input voltage and the compensation current, And the output voltage is output to the amplifying unit, and the rising speed of the output voltage is related to a current value of the compensation current.
本發明的功效在於:藉由該電流補償單元產生該補償電流並傳輸至該運算放大單元進行補償,使得該輸出電壓得以較快到達一穩定電壓值,進而達到提升該運算放大裝置之該輸出電壓響應的目的。The effect of the present invention is that the compensation current is generated by the current compensation unit and transmitted to the operational amplifier unit for compensation, so that the output voltage can reach a stable voltage value faster, and then the output voltage of the operational amplifier device can be improved The purpose of the response.
在本發明被詳細描述的前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same number.
參閱圖3與圖4,本發明運算放大裝置的一第一實施例,包含一放大單元2、一電流補償單元3,及一運算放大單元4。Referring to FIGS. 3 and 4, a first embodiment of the operational amplification device of the present invention includes an
該放大單元2具有彼此相配合接收一輸出電壓Vo的一非反相輸入端201及一反相輸入端202,且將該輸出電壓Vo放大以產生一放大電壓Va。在本實施例中,該放大單元2包括第一至第三運算放大器20、21、22,第一及第二電阻器23、24、一增益電阻器25,及第三至第六電阻器26、27、28、29。該放大單元2為一儀表放大單元,但不限於此。The amplifying
該第一運算放大器20具有一電連接該放大單元2之該非反相輸入端201的第一非反相輸入端、一第一反相輸入端,及一第一輸出端。該第一電阻器23電連接在該第一運算放大器20之該第一反相輸入端與該第一輸出端間。該第二運算放大器21具有一電連接該放大單元2之該反相輸入端202的第二非反相輸入端、一第二反相輸入端,及一第二輸出端。該第二電阻器24電連接在該第二運算放大器21之該第二反相輸入端與該第二輸出端間。該增益電阻器25電連接在該第一運算放大器20的該第一反相輸入端與該第二運算放大器21的該第二反相輸入端間。在本實施例中,該增益電阻器25為一可變電阻器,但不限於此。該第三電阻器26具有一電連接該第一運算放大器20之該第一輸出端的第一端,及一第二端。該第四電阻器27電連接在該第三電阻器26的該第二端與地間。該第五電阻器28具有一電連接該第二運算放大器21之該第二輸出端的第一端,及一第二端。該第三運算放大器22具有一電連接該第三電阻器26的該第二端的第三非反相輸入端、一電連接該第五電阻器28的該第二端的第三反相輸入端,及一輸出該放大電壓Va的第三輸出端。該第六電阻器29電連接在該第三運算放大器22之該第三反相輸入端與該第三輸出端間。The first
該電流補償單元3用於接收一輸入電壓Vi,且電連接該放大單元2之該第三運算放大器22的該第三輸出端以接收該放大電壓Va,並根據該放大電壓Va及該輸入電壓Vi調整並產生一補償電流Ic。在本實施例中,該電流補償單元3包括一運算放大電路31,及一電壓電流轉換電路32。The
該運算放大電路31用於接收該輸入電壓Vi,且電連接該第三運算放大器22的該第三輸出端以接收該放大電壓Va,並將該放大電壓Va減該輸入電壓Vi以產生一誤差電壓Ve。在本實施例中,該運算放大電路31包括第一至第四電阻器311~314,及一運算放大器315。The
該第一電阻器311具有一用於接收該輸入電壓Vi的第一端,及一第二端。該第二電阻器312具有一電連接該第三運算放大器22的該第三輸出端以接收該放大電壓Va的第一端,及一第二端。該第三電阻器313電連接在該第二電阻器312的該第二端與地間。該運算放大器315具有一電連接該第一電阻器311之該第二端的反相輸入端、一電連接該第二電阻器312之該第二端的非反相輸入端,及一輸出該誤差電壓Ve的輸出端。該第四電阻器314電連接在該運算放大器315的該反相輸入端與該輸出端間。The
該電壓電流轉換電路32電連接該運算放大電路31之該運算放大器315的該輸出端以接收該誤差電壓Ve,並根據該誤差電壓Ve產生該補償電流Ic。在本實施例中,該電壓電流轉換電路32包括第一至第四電阻器321、322、323、324,及一運算放大器325。The voltage-
該第一電阻器321具有一接地的第一端,及一第二端。該第二電阻器322具有一電連接該運算放大器315的該輸出端以接收該誤差電壓Ve的第一端,及一第二端。該運算放大器325具有一電連接該第一電阻器321之該第二端的反相輸入端、一電連接該第二電阻器322之該第二端的非反相輸入端,及一輸出端。該第三電阻器323電連接在該運算放大器325的該反相輸入端與該輸出端間。該第四電阻器324電連接在該運算放大器325的該非反相輸入端與該輸出端間。該第四電阻器324、該運算放大器325的該非反相輸入端及該第二電阻器322之該第二端間的一共同接點N1提供該補償電流Ic。The
該運算放大單元4用於接收該輸入電壓Vi,且電連接該放大單元2之該非反相輸入端201與該反相輸入端202,並電連接該電流補償單元3之該共同接點N1以接收該補償電流Ic。該運算放大單元4根據該輸入電壓Vi及該補償電流Ic調整並產生該輸出電壓Vo,且將該輸出電壓Vo輸出至該放大單元2之該非反相輸入端201與該反相輸入端202。在本實施例中,該運算放大單元4包括一運算放大器41、第一及第二電阻器42、43,及一電容器44。The
該運算放大器41具有一用於接收該輸入電壓Vi的非反相輸入端、一反相輸入端,及一輸出端。該第一電阻器42電連接在該運算放大器41之該反相輸入端及該輸出端間。該第二電阻器43電連接在該運算放大器41之該反相輸入端與地間。該電容器44具有一電連接該運算放大器41之該輸出端與該放大單元2之該非反相輸入端201的第一端,及一第二端。該電容器44的該第二端電連接該電流補償單元3的該共同接點N1以接收該補償電流Ic,且電連接該運算放大器41之該反相輸入端與該放大單元2之該反相輸入端202。該電容器44的一跨壓作為該輸出電壓Vo。The
需說明的是,由於本實施例該運算放大裝置藉由該電流補償單元3產生該補償電流Ic並傳輸至該電容器44,以補償該輸出電壓Vo受該第一電阻器42及該電容器44的一時間常數τ影響而延遲上升至一穩定電壓值的問題,使得該輸出電壓Vo得以較快到達該穩定電壓值,進而達到提升該運算放大裝置之該輸出電壓Vo響應的目的。It should be noted that, in this embodiment, the operational amplifier device generates the compensation current Ic through the
參閱圖5,其為例如,將該增益電阻器25移除(即,該等第一及第二電阻器23、24間開路),該電容器44的一電容值設為0.01u法拉,該等第一與第二電阻器42、43、該等第一至第四電阻器311~314、該等第三至第六電阻器26~29,及該等第一與第三電阻器321、323各自的一電阻值設為10k歐姆,該等第一與第二電阻器23、24,及該等第二與第四電阻器322、324各自的一電阻值設為5k歐姆為例時,該實施例的該輸入電壓Vi及該輸出電壓Vo各自對時間的變化。Referring to FIG. 5, for example, the
從圖5可得知,當該輸入電壓Vi由0V上升至5V時,該輸出電壓Vo僅延遲約100us即由0V上升至5V,相較於習知圖2中的一輸入電壓vi由0V上升至5V時,相對應的一輸出電壓vo會延遲約500us才上升至5V而言,該實施例之該運算放大裝置確實可縮短該輸出電壓Vo到達該穩定電壓值(即,5V)的一延遲時間(由習知約500us縮短至約100us),進而達到提升該輸出電壓Vo響應之功效。It can be seen from FIG. 5 that when the input voltage Vi rises from 0V to 5V, the output voltage Vo only rises by about 100us, that is, rises from 0V to 5V, which is increased from 0V compared to an input voltage vi in FIG. 2. When it reaches 5V, the corresponding output voltage vo will delay about 500us before it rises to 5V. The operational amplifier of this embodiment can really shorten a delay when the output voltage Vo reaches the stable voltage value (ie, 5V) Time (from the conventional reduction of about 500us to about 100us), and then to achieve the effect of improving the output voltage Vo response.
參閱圖6,本發明運算放大裝置的一第二實施例為該第一實施例的修改,二者不同之處在於: 1. 該電流補償單元3還包括一非反相放大電路33。該非反相放大電路33用於接收該輸入電壓Vi,並將該輸入電壓Vi放大以產生一調整電壓Vad。該非反相放大電路33包括一運算放大器331,及第一與第二可變電阻器332、333。該運算放大器331具有一用於接收該輸入電壓Vi的非反相輸入端、一反相輸入端,及一輸出該調整電壓Vad的輸出端。該第一可變電阻器332電連接在該運算放大器331之該反相輸入端與地間。該第二可變電阻器333電連接在該運算放大器331之該反相輸入端與該輸出端間。 2. 該運算放大電路31之該第一電阻器311的該第一端是電連接該非反相放大電路33之該運算放大器331的該輸出端以接收該調整電壓Vad,以致該運算放大電路31是將該放大電壓Va減該調整電壓Vad來產生該誤差電壓Ve,而不是將該放大電壓Va減該輸入電壓Vi來產生該誤差電壓Ve。Referring to FIG. 6, a second embodiment of the operational amplifier device of the present invention is a modification of the first embodiment. The difference between the two is as follows: 1. The
如此一來,由於該增益電阻器25及該等第一與第二可變電阻器332、333皆為可變電阻器,因此藉由調整該增益電阻器25及該等第一與第二可變電阻器332、333各自的一電阻值即可改變相對應的該放大單元2及該非反相放大電路33各自的一增益,使得該補償電流Ic隨著該放大單元2及該非反相放大電路33各自的該增益的改變而變化。舉例來說,當該放大單元2及該非反相放大電路33各自的該增益皆變大K倍時(K≧2),該運算放大電路31所產生的該誤差電壓Ve的電壓值增加,進而該電壓電流轉換電路32根據該誤差電壓Ve所產生的該補償電流Ic的電流值也隨之增加,如此更可快速縮短該輸出電壓Vo到達該穩定電壓值時所需的該延遲時間。簡言之,該輸出電壓Vo上升的速度相關於該補償電流Ic的電流值。In this way, since the
綜上所述,藉由該電流補償單元3產生該補償電流Ic並傳輸至該電容器44,可縮短該輸出電壓Vo到達該穩定電壓值時所需的該延遲時間,如此一來,達到提升本實施例該運算放大裝置之該輸出電壓Vo響應的目的。In summary, by generating the compensation current Ic and transmitting it to the
惟以上所述者,僅為本發明的實施例而已,當不能以此限定本發明實施的範圍,凡是依本發明申請專利範圍及專利說明書內容所作的簡單的等效變化與修飾,皆仍屬本發明專利涵蓋的範圍內。However, the above are only examples of the present invention, and the scope of implementation of the present invention cannot be limited by this, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still classified as Within the scope of the invention patent.
2‧‧‧放大單元20‧‧‧第一運算放大器21‧‧‧第二運算放大器22‧‧‧第三運算放大器23‧‧‧第一電阻器24‧‧‧第二電阻器25‧‧‧增益電阻器26~29‧‧‧第三至第六電阻器201‧‧‧非反相輸入端202‧‧‧反相輸入端3‧‧‧電流補償單元31‧‧‧運算放大電路311~314‧‧‧第一至第四電阻器315‧‧‧運算放大器32‧‧‧電壓電流轉換電路321~324‧‧‧第一至第四電阻器325‧‧‧運算放大器33‧‧‧非反相放大電路331‧‧‧運算放大器332‧‧‧第一可變電阻器333‧‧‧第二可變電阻器4‧‧‧運算放大單元41‧‧‧運算放大器42、43‧‧‧第一及第二電阻器44‧‧‧電容器Ic‧‧‧補償電流N1‧‧‧共同接點Va‧‧‧放大電壓Vad‧‧‧調整電壓Ve‧‧‧誤差電壓Vi‧‧‧輸入電壓Vo‧‧‧輸出電壓
2‧‧‧
本發明的其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是一電路圖,說明習知運算放大裝置; 圖2是一模擬圖,說明該習知運算放大裝置的一輸入電壓及一輸出電壓各自對時間的變化; 圖3是一電路圖,說明本發明運算放大裝置之一第一實施例; 圖4是一電路圖,說明該第一實施例之該運算放大裝置的一放大單元; 圖5是一模擬圖,說明該實施例的一輸入電壓及一輸出電壓各自對時間的變化;及 圖6是一電路方塊圖,說明本發明運算放大裝置之一第二實施例。Other features and functions of the present invention will be clearly presented in the embodiment with reference to the drawings, in which: FIG. 1 is a circuit diagram illustrating a conventional operation amplification device; FIG. 2 is a simulation diagram illustrating the conventional operation amplification The changes of an input voltage and an output voltage of the device with respect to time respectively; FIG. 3 is a circuit diagram illustrating a first embodiment of the operational amplification device of the present invention; FIG. 4 is a circuit diagram illustrating the operational amplification of the first embodiment An amplification unit of the device; FIG. 5 is a simulation diagram illustrating the change of an input voltage and an output voltage of the embodiment with respect to time; and FIG. 6 is a circuit block diagram illustrating a second of the operational amplification device of the present invention. Examples.
2‧‧‧放大單元 2‧‧‧Amplification unit
20‧‧‧第一運算放大器 20‧‧‧The first operational amplifier
21‧‧‧第二運算放大器 21‧‧‧ Second operational amplifier
22‧‧‧第三運算放大器 22‧‧‧The third operational amplifier
23‧‧‧第一電阻器 23‧‧‧ First resistor
24‧‧‧第二電阻器 24‧‧‧Second resistor
25‧‧‧增益電阻器 25‧‧‧Gain resistor
26~29‧‧‧第三至第六電阻器 26~29‧‧‧ Third to sixth resistors
201‧‧‧非反相輸入端 201‧‧‧Non-inverting input
202‧‧‧反相輸入端 202‧‧‧Inverting input
3‧‧‧電流補償單元 3‧‧‧Current compensation unit
31‧‧‧運算放大電路 31‧‧‧Operation amplifier circuit
311~314‧‧‧第一至第四電阻器 311~314‧‧‧ First to fourth resistors
315‧‧‧運算放大器 315‧‧‧Operational amplifier
32‧‧‧電壓電流轉換電路 32‧‧‧Voltage current conversion circuit
321~324‧‧‧第一至第四電阻器 321~324‧‧‧ First to fourth resistors
325‧‧‧運算放大器 325‧‧‧Operational amplifier
4‧‧‧運算放大單元 4‧‧‧Amplification unit
41‧‧‧運算放大器 41‧‧‧Operational amplifier
42、43‧‧‧第一及第二電阻器 42, 43‧‧‧ First and second resistors
44‧‧‧電容器 44‧‧‧Capacitor
Ic‧‧‧補償電流 Ic‧‧‧Compensation current
N1‧‧‧共同接點 N1‧‧‧ common contact
Va‧‧‧放大電壓 Va‧‧‧amplified voltage
Ve‧‧‧誤差電壓 Ve‧‧‧Error voltage
Vi‧‧‧輸入電壓 Vi‧‧‧Input voltage
Vo‧‧‧輸出電壓 Vo‧‧‧ output voltage
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107119682A TWI660575B (en) | 2018-06-07 | 2018-06-07 | Operational amplifier device with improved output voltage response |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107119682A TWI660575B (en) | 2018-06-07 | 2018-06-07 | Operational amplifier device with improved output voltage response |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI660575B TWI660575B (en) | 2019-05-21 |
TW202002504A true TW202002504A (en) | 2020-01-01 |
Family
ID=67349080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107119682A TWI660575B (en) | 2018-06-07 | 2018-06-07 | Operational amplifier device with improved output voltage response |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI660575B (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5315164A (en) * | 1993-05-26 | 1994-05-24 | Nec America, Inc. | Adaptive clock duty cycle controller |
US6504409B1 (en) * | 2001-04-17 | 2003-01-07 | K-Tek Corporation | Controller for generating a periodic signal with an adjustable duty cycle |
US7337239B2 (en) * | 2002-11-19 | 2008-02-26 | Microsoft Corporation | Atomic message division |
-
2018
- 2018-06-07 TW TW107119682A patent/TWI660575B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI660575B (en) | 2019-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9595931B2 (en) | Two differential amplifier configuration | |
US8487686B2 (en) | Active guarding for reduction of resistive and capacitive signal loading with adjustable control of compensation level | |
JP6744695B2 (en) | Active shunt ammeter | |
US8305113B1 (en) | Intra-pair skew cancellation technique for differential signaling | |
TW200947855A (en) | Capacitance multiplier circuit | |
RU2427071C1 (en) | Broadband amplifier | |
JP5454366B2 (en) | Power amplifier module and portable information terminal | |
US7893746B1 (en) | High speed intra-pair de-skew circuit | |
TWI660575B (en) | Operational amplifier device with improved output voltage response | |
JP6555959B2 (en) | Voltage regulator | |
JP2015097312A (en) | Microphone and microphone device | |
TWI559682B (en) | Driving circuit, driving apparatus, and method for adjusting output impedance to match transmission line impedance by current adjusting | |
TW202005268A (en) | Operational amplifier device with improved output voltage response including a signal adjustment unit and an operational amplifier unit | |
TWI607624B (en) | Driver | |
US9871495B2 (en) | Thermal compensation for amplifiers | |
JP4839572B2 (en) | Input circuit | |
JP6512826B2 (en) | Differential amplifier | |
KR101360648B1 (en) | Instrumentation amplifier using second generation current-conveyer | |
US11171620B2 (en) | Interface circuit and corresponding method | |
KR20120140550A (en) | Variable-gain amplifier and receiver including the same | |
JP6986066B2 (en) | Noise removal circuit | |
TWI641216B (en) | Dual-mode signal amplifying circuit of signal receiver | |
KR101811614B1 (en) | Compensation circuit for differential signal and controlling method thereof | |
TW201608825A (en) | Method and apparatus for gain enhancement of differential amplifier | |
JP2009031223A (en) | Compensating circuit, probe system, probe system kit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |