TW201941314A - Manufacturing method for semiconductor device, and adhesive film - Google Patents

Manufacturing method for semiconductor device, and adhesive film Download PDF

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Publication number
TW201941314A
TW201941314A TW108103596A TW108103596A TW201941314A TW 201941314 A TW201941314 A TW 201941314A TW 108103596 A TW108103596 A TW 108103596A TW 108103596 A TW108103596 A TW 108103596A TW 201941314 A TW201941314 A TW 201941314A
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film
semiconductor wafer
semiconductor
adhesive
adhesive film
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TW108103596A
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Chinese (zh)
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TWI791751B (en
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國土由衣
山本和弘
谷口紘平
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日商日立化成股份有限公司
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00Layered products comprising a layer of synthetic resin
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00Adhesives based on unspecified macromolecular compounds
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00Adhesives in the form of films or foils
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00Adhesives in the form of films or foils
    • C09J7/30Adhesives in the form of films or foils characterised by the adhesive composition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Adhesive Tapes (AREA)
  • Dicing (AREA)
  • Laminated Bodies (AREA)

Abstract

Disclosed is a manufacturing method for a semiconductor device, the method comprising a step for preparing a semiconductor wafer that has an adhesive film in which the adhesive film and a semiconductor wafer are provided in the stated order on a self-adhesive film, a dicing step for dicing the semiconductor wafer that has the adhesive-film and obtaining semiconductor chips that have the adhesive film, and a compression-bonding step for compression-bonding the semiconductor chips that have the adhesive film to a semiconductor substrate. The adhesive film includes a first film and a second film in the stated order from the self-adhesive film, the second film having a 80 DEG C shear viscosity that differs from that of the first film, and the 80 DEG C shear viscosity of the second film being 500 Pa.s or greater.

Description

半導體裝置的製造方法及接著膜Manufacturing method of semiconductor device and adhesive film

本發明是有關於一種導體裝置的製造方法及接著膜。The present invention relates to a method for manufacturing a conductor device and an adhesive film.

先前,於半導體晶片與半導體基板的接合中,主要使用銀糊。但是,隨著近年來半導體晶片的小型化及積體化,對於所使用的半導體基板亦開始要求小型化及細密化。另一方面,於使用銀糊的情況下,有時會出現起因於糊的露出或半導體晶片的斜度的於打線接合(wire bonding)時產生的不良、膜厚控制困難、產生空隙等問題。Previously, a silver paste was mainly used for bonding a semiconductor wafer and a semiconductor substrate. However, with the recent miniaturization and integration of semiconductor wafers, miniaturization and miniaturization of the semiconductor substrates used have also begun to be required. On the other hand, when a silver paste is used, problems such as defects in wire bonding caused by exposure of the paste or the inclination of the semiconductor wafer, difficulty in controlling film thickness, and generation of voids may occur.

因此,近年來一直使用用以接合半導體晶片與半導體基板的接著膜(例如參照專利文獻1)。於使用包括切割帶(dicing tape)及積層於切割帶上的接著膜的接著膜情況下,藉由於半導體晶圓的背面貼附接著膜,並藉由切割來使半導體晶圓單片化,而可獲得帶有接著膜的半導體晶片。所獲得的帶有接著膜的半導體晶片可經由接著膜而貼附於半導體基板,並藉由熱壓接而接合。
[現有技術文獻]
[專利文獻]
Therefore, an adhesive film for bonding a semiconductor wafer and a semiconductor substrate has been used in recent years (for example, refer to Patent Document 1). In the case of using an adhesive film including a dicing tape and an adhesive film laminated on the dicing tape, the semiconductor wafer is singulated by attaching the adhesive film to the back surface of the semiconductor wafer and singulating the semiconductor wafer. A semiconductor wafer with an adhesive film can be obtained. The obtained semiconductor wafer with an adhesive film can be attached to a semiconductor substrate via an adhesive film, and can be joined by thermocompression bonding.
[Prior Art Literature]
[Patent Literature]

專利文獻1:日本專利特開2007-053240號公報Patent Document 1: Japanese Patent Laid-Open No. 2007-053240

[發明所欲解決之課題]
然而,隨著半導體晶片的小型化及積體化,當使接著膜硬化時,存在半導體裝置的半導體基板發生翹曲的情況。若半導體基板發生翹曲,則例如於密封步驟中,有半導體晶片自密封材露出,產生電氣不良之虞。
[Problems to be Solved by the Invention]
However, with the miniaturization and integration of semiconductor wafers, when the adhesive film is hardened, the semiconductor substrate of the semiconductor device may be warped. If the semiconductor substrate is warped, for example, in the sealing step, the semiconductor wafer may be exposed from the sealing material, which may cause electrical failure.

另外,於使用作為導線埋入型接著膜的導線上膜(Film Over Wire,FOW)或作為晶片埋入型接著膜的晶片上膜(Film Over Die,FOD)的情況下,進而有半導體基板的翹曲增大的傾向。另外,對於該些接著膜,要求埋入導線、控制器晶片等,因而帶有接著膜的半導體晶片亦存在發生翹曲的情況。In addition, when using a film over wire (FOW) as a wire-embedded adhesive film or a film over die (FOD) as a wafer-embedded adhesive film, there are further semiconductor substrates. Warp tends to increase. In addition, for these adhesive films, it is required to embed wires, a controller wafer, and the like, so semiconductor wafers with adhesive films may also warp.

本發明是鑒於此種情況而成,主要目的在於提供一種能夠抑制半導體基板的翹曲的半導體裝置的製造方法。This invention is made in view of such a situation, The main objective is to provide the manufacturing method of the semiconductor device which can suppress the curvature of a semiconductor substrate.

[解決課題之手段]
本發明的一方面提供一種半導體裝置的製造方法,其包括:準備帶有接著膜的半導體晶圓的步驟,所述帶有接著膜的半導體晶圓於黏著膜上依序具有接著膜及半導體晶圓;切割步驟,切割帶有接著膜的半導體晶圓,而獲得帶有接著膜的半導體晶片;以及壓接步驟,將帶有接著膜的半導體晶片壓接於半導體基板;且自黏著膜起,接著膜依序包含第一膜及80℃下的剪切黏度與第一膜不同的第二膜,第二膜的80℃下的剪切黏度為500 Pa·s以上。根據此種半導體裝置的製造方法,能夠抑制半導體基板的翹曲。
[Means for solving problems]
An aspect of the present invention provides a method for manufacturing a semiconductor device, including the step of preparing a semiconductor wafer with an adhesive film, the semiconductor wafer with an adhesive film sequentially having an adhesive film and a semiconductor crystal on an adhesive film. Round; cutting step, dicing a semiconductor wafer with an adhesive film to obtain a semiconductor wafer with an adhesive film; and a crimping step, crimping the semiconductor wafer with an adhesive film to a semiconductor substrate; and from the adhesive film, Then, the film sequentially includes a first film and a second film having a shear viscosity different from that of the first film at 80 ° C. The shear viscosity of the second film at 80 ° C. is 500 Pa · s or more. According to the method of manufacturing such a semiconductor device, it is possible to suppress warpage of the semiconductor substrate.

第二膜的厚度可為3 μm~150 μm。第二膜的硬化後的150℃下的儲存彈性係數可為1000 MPa以下。The thickness of the second film may be 3 μm to 150 μm. The storage elastic coefficient at 150 ° C. of the second film after curing may be 1000 MPa or less.

半導體裝置可為藉由將第一半導體晶片經由第一導線而以打線接合的方式連接於半導體基板上,並且於第一半導體晶片上,經由接著膜而壓接第二半導體晶片,從而將第一導線的至少一部分埋入接著膜中而成的導線埋入型的半導體裝置;亦可為將第一導線及第一半導體晶片埋入接著膜中而成的晶片埋入型的半導體裝置。此種半導體裝置中,不僅能夠抑制半導體基板的翹曲,亦能夠抑制帶有接著膜的半導體晶片(第二半導體晶片)的翹曲。The semiconductor device can be connected to the semiconductor substrate by wire bonding via a first wire, and the first semiconductor wafer can be crimped to the second semiconductor wafer via a bonding film, thereby bonding the first semiconductor wafer to the first semiconductor wafer. A lead-embedded semiconductor device in which at least a part of the lead is buried in the adhesive film; or a wafer-embedded semiconductor device in which the first lead and the first semiconductor wafer are embedded in the adhesive film. In such a semiconductor device, it is possible to suppress warpage of not only the semiconductor substrate but also the semiconductor wafer (second semiconductor wafer) with an adhesive film.

另一方面中,本發明提供一種接著膜,其包括第一膜及第二膜,所述第二膜積層於第一膜上,且80℃下的剪切黏度與第一膜不同,第二膜的80℃下的剪切黏度為500 Pa·s以上。In another aspect, the present invention provides an adhesive film including a first film and a second film, the second film is laminated on the first film, and the shear viscosity at 80 ° C. is different from that of the first film, and the second The shear viscosity of the film at 80 ° C was 500 Pa · s or more.

第二膜的厚度可為3 μm~150 μm。第二膜的硬化後的150℃下的儲存彈性係數可為1000 MPa以下。The thickness of the second film may be 3 μm to 150 μm. The storage elastic coefficient at 150 ° C. of the second film after curing may be 1000 MPa or less.

所述接著膜可為於第一半導體晶片經由第一導線而以打線接合的方式連接於半導體基板上,並且於第一半導體晶片上壓接第二半導體晶片而成的半導體裝置中,用於壓接第二半導體晶片並且埋入第一導線的至少一部分者(即FOW用途);亦可為用於埋入第一導線及第一半導體晶片者(即FOD用途)。The adhesive film may be used in a semiconductor device in which a first semiconductor wafer is connected to a semiconductor substrate by wire bonding via a first wire, and a second semiconductor wafer is crimped to the first semiconductor wafer. Connected to the second semiconductor wafer and buried at least a part of the first wire (that is, FOW use); it can also be used to embed the first wire and the first semiconductor wafer (that is, FOD use).

[發明的效果]
根據本發明,可提供一種能夠抑制半導體基板的翹曲的半導體裝置的製造方法。若干形態的製造方法能夠實現亦抑制帶有接著膜的半導體晶片的翹曲。另外,根據本發明,可提供一種此種製造方法中可使用的接著膜。
[Effect of the invention]
According to the present invention, a method for manufacturing a semiconductor device capable of suppressing warpage of a semiconductor substrate can be provided. The manufacturing method of several forms can implement | achieve also suppressing the curvature of the semiconductor wafer with an adhesive film. Moreover, according to this invention, the adhesive film which can be used for such a manufacturing method can be provided.

以下,適當參照圖式來對本發明的實施形態進行說明。但,本發明並不限定於以下的實施形態。Hereinafter, embodiments of the present invention will be described with appropriate reference to the drawings. However, the present invention is not limited to the following embodiments.

本說明書中,(甲基)丙烯酸是指丙烯酸或與其對應的甲基丙烯酸。關於(甲基)丙烯醯基等其他的類似表述亦同樣。In this specification, (meth) acrylic acid means acrylic acid or a corresponding methacrylic acid. The same applies to other similar expressions such as (meth) acrylfluorenyl.

<半導體裝置的製造方法>
[準備步驟]
於本步驟中,準備作為切割對象的帶有接著膜的半導體晶圓。
<Method for Manufacturing Semiconductor Device>
[Preparation steps]
In this step, a semiconductor wafer with an adhesive film as a cutting target is prepared.

對接著膜的製作方法的一例進行說明。首先,於基材膜1、基材膜4a及基材膜4b上分別塗佈獨立的黏著劑、第一接著劑及第二接著劑,製作包括基材膜1及黏著膜2的膜100(圖1)、包括基材膜4a及第一膜3a的膜110(圖2(a))、及包括基材膜4b及第二膜3b的膜120(圖2(b))。其後,自膜110及膜120剝去基材膜4a及基材膜4b,並將第一膜3a及第二膜3b貼合,而製作接著膜130(圖2(c))。繼而,可以成為黏著膜2、第一膜3a及第二膜3b的順序的方式積層於膜100,從而獲得包括基材膜1、黏著膜2及接著膜130的接著片200(圖3)。接著片200亦可藉由於膜100(圖1)上塗佈第一接著劑清漆,繼而塗佈第二接著劑清漆的方法進行製作。再者,有時將自接著片200去除了基材膜1者稱為切割-黏晶一體型接著膜140。其後,可藉由於接著膜130上貼附半導體晶圓A而獲得帶有接著膜的半導體晶圓300(圖4)。即,以所述方式獲得的帶有接著膜的半導體晶圓300可稱為於黏著膜上依序包括接著膜及半導體晶圓的積層體。An example of a method for producing an adhesive film will be described. First, an independent adhesive, a first adhesive, and a second adhesive are coated on the substrate film 1, the substrate film 4a, and the substrate film 4b, respectively, to prepare a film 100 including the substrate film 1 and the adhesive film 2 ( Fig. 1), a film 110 including a base film 4a and a first film 3a (Fig. 2 (a)), and a film 120 including a base film 4b and a second film 3b (Fig. 2 (b)). Then, the base film 4a and the base film 4b are peeled from the films 110 and 120, and the 1st film 3a and the 2nd film 3b are bonded together, and the adhesive film 130 is produced (FIG.2 (c)). Then, the film 100 can be laminated in the order of the adhesive film 2, the first film 3a, and the second film 3b in order to obtain an adhesive sheet 200 including the base film 1, the adhesive film 2, and the adhesive film 130 (FIG. 3). The adhesive sheet 200 can also be produced by coating the first adhesive varnish on the film 100 (FIG. 1) and then applying the second adhesive varnish. Note that the substrate film 1 from which the self-adhesive sheet 200 is removed may be referred to as a cut-bond-integrated adhesive film 140 in some cases. Thereafter, a semiconductor wafer 300 with an adhesive film can be obtained by attaching the semiconductor wafer A to the adhesive film 130 (FIG. 4). That is, the semiconductor wafer 300 with an adhesive film obtained in this manner may be referred to as a laminated body including the adhesive film and the semiconductor wafer in this order on the adhesive film.

作為基材膜1、基材膜4a及基材膜4b,例如可列舉:聚四氟乙烯膜、聚對苯二甲酸乙二酯膜、聚乙烯膜、聚丙烯膜、聚甲基戊烯膜、聚醯亞胺膜等塑膠膜等。對於基材膜,視需要亦可進行底塗塗佈、紫外線(ultraviolet,UV)處理、電暈放電處理、研磨處理、蝕刻處理等表面處理。Examples of the base film 1, the base film 4a, and the base film 4b include a polytetrafluoroethylene film, a polyethylene terephthalate film, a polyethylene film, a polypropylene film, and a polymethylpentene film. , Polyimide film and other plastic films. For the base film, surface treatments such as primer coating, ultraviolet (UV) treatment, corona discharge treatment, polishing treatment, and etching treatment may be performed as necessary.

黏著膜2可由感壓型或紫外線硬化型的黏著劑形成。黏著膜2的厚度可根據所製造的半導體裝置的形狀、尺寸而適當設定,較佳為1 μm~100 μm,更佳為5 μm~70 μm,進而佳為10 μm~40 μm。The adhesive film 2 may be formed of a pressure-sensitive adhesive or an ultraviolet-curable adhesive. The thickness of the adhesive film 2 can be appropriately set according to the shape and size of the semiconductor device to be manufactured, and is preferably 1 μm to 100 μm, more preferably 5 μm to 70 μm, and even more preferably 10 μm to 40 μm.

(接著膜)
接著膜130包括第一膜3a及積層於第一膜3a上的80℃下的剪切黏度與第一膜3a不同的第二膜。另外,第二膜3b的80℃下的剪切黏度為500 Pa·s以上。
(Then film)
The next film 130 includes a first film 3a and a second film laminated on the first film 3a with a shear viscosity at 80 ° C. different from that of the first film 3a. The shear viscosity at 80 ° C of the second film 3b is 500 Pa · s or more.

第一膜3a及第二膜3b均為熱硬化性,可由經過半硬化(B階段)狀態且於硬化處理後可成完全硬化物(C階段)狀態的第一接著劑及第二接著劑形成。第一膜3a及第二膜3b較佳為含有熱硬化性樹脂(以下有時簡稱為「(a)成分」)、高分子量成分(以下有時簡稱為「(b)成分」)及無機填料(以下有時簡稱為「(c)成分」)。第一膜3a及第二膜3b亦可更含有偶合劑(以下有時簡稱為「(d)成分」)及硬化促進劑(以下有時簡稱為「(e)成分」)。The first film 3a and the second film 3b are both thermosetting, and can be formed of a first adhesive and a second adhesive that are in a semi-hardened (B-stage) state and can be completely cured (C-stage) after hardening. . The first film 3a and the second film 3b preferably contain a thermosetting resin (hereinafter sometimes referred to as "(a) component"), a high molecular weight component (hereinafter sometimes referred to as "(b) component"), and an inorganic filler. (Hereinafter sometimes referred to as "(c) component"). The first film 3a and the second film 3b may further contain a coupling agent (hereinafter sometimes referred to as "(d) component") and a hardening accelerator (hereinafter sometimes referred to as "(e) component").

(a)熱硬化性樹脂
就接著性的觀點而言,(a)成分較佳為包含環氧樹脂(以下有時簡稱為「(a1)成分」)及可作為環氧樹脂的硬化劑的酚樹脂(以下有時簡稱為「(a2)成分」)。
(A) Thermosetting resin From the viewpoint of adhesiveness, the component (a) is preferably a phenol containing an epoxy resin (hereinafter sometimes simply referred to as "(a1) component") and a hardener for epoxy resin. Resin (hereinafter sometimes referred to as "(a2) component").

(a1)成分只要為分子內具有環氧基者則可並無特別限制地使用。作為(a1)成分,例如可列舉:雙酚A型環氧樹脂、雙酚F型環氧樹脂、雙酚S型環氧樹脂、苯酚酚醛清漆型環氧樹脂、甲酚酚醛清漆型環氧樹脂、雙酚A酚醛清漆型環氧樹脂、雙酚F酚醛清漆型環氧樹脂、二苯乙烯型環氧樹脂、含三嗪骨架的環氧樹脂、含茀骨架的環氧樹脂、三苯酚苯酚甲烷型環氧樹脂、聯苯型環氧樹脂、伸二甲苯基型環氧樹脂、聯苯芳烷基型環氧樹脂、萘型環氧樹脂、多官能苯酚類、蒽等多環芳香族類的二縮水甘油醚化合物等。該些可單獨使用一種或者將兩種以上組合使用。該些中,就膜的黏性、柔軟性等觀點而言,(a1)成分可為甲酚酚醛清漆型環氧樹脂、雙酚F型環氧樹脂、或雙酚A型環氧樹脂。The component (a1) can be used without particular limitation as long as it has an epoxy group in the molecule. Examples of the component (a1) include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol S epoxy resin, phenol novolac epoxy resin, and cresol novolac epoxy resin. Bisphenol A novolac epoxy resin, bisphenol F novolac epoxy resin, stilbene epoxy resin, epoxy resin containing triazine skeleton, epoxy resin containing fluorene skeleton, triphenol phenol methane Type epoxy resin, biphenyl type epoxy resin, xylylene type epoxy resin, biphenylaralkyl type epoxy resin, naphthalene type epoxy resin, polyfunctional phenols, anthracene and other polycyclic aromatics Glycidyl ether compounds and the like. These may be used alone or in combination of two or more. Among these, from the viewpoints of the viscosity and flexibility of the film, the (a1) component may be a cresol novolac-type epoxy resin, a bisphenol F-type epoxy resin, or a bisphenol A-type epoxy resin.

(a1)成分亦可包含軟化點小於30℃或常溫(25℃)下為液體的環氧樹脂。藉由包含此種環氧樹脂,則所獲得的膜可賦予柔軟性,晶片、導線或半導體基板的埋入性進一步提升,而有可緩和因埋入不足所導致的翹曲的傾向。The component (a1) may include an epoxy resin having a softening point of less than 30 ° C or a liquid at normal temperature (25 ° C). By including such an epoxy resin, the obtained film can be given flexibility, and the embedding property of a wafer, a lead, or a semiconductor substrate can be further improved, and there is a tendency that warpage due to insufficient embedding can be alleviated.

(a1)成分亦可包含軟化點為50℃以上的環氧樹脂。該情況下,較佳為使用當進行了軟化時流動性優異者。The component (a1) may include an epoxy resin having a softening point of 50 ° C or higher. In this case, it is preferable to use one having excellent fluidity when softened.

(a2)成分只要為分子內具有酚性羥基者則可並無特別限制地使用。作為(a2)成分,例如可列舉:使苯酚、甲酚、間苯二酚(resorcin)、鄰苯二酚、雙酚A、雙酚F、苯基苯酚、胺基苯酚等酚類及/或α-萘酚、β-萘酚、二羥基萘等萘酚類與甲醛等具有醛基的化合物於酸性觸媒下縮合或共縮合而獲得的酚醛清漆型酚樹脂;由烯丙基化雙酚A、烯丙基化雙酚F、烯丙基化萘二醇、苯酚酚醛清漆、苯酚等酚類及/或萘酚類與二甲氧基對二甲苯或雙(甲氧基甲基)聯苯所合成的苯酚芳烷基樹脂、萘酚芳烷基樹脂等。該些可單獨使用一種或者將兩種以上組合使用。該些中,(a2)成分可為苯酚芳烷基樹脂或萘酚芳烷基樹脂。The component (a2) can be used without particular limitation as long as it has a phenolic hydroxyl group in the molecule. Examples of the component (a2) include phenols such as phenol, cresol, resorcin, catechol, bisphenol A, bisphenol F, phenylphenol, and aminophenol, and / or Novolac-type phenol resins obtained by condensing or co-condensing naphthols such as α-naphthol, β-naphthol, and dihydroxynaphthalene with formaldehyde-containing compounds under acidic catalysts; allylated bisphenols A. Allylated bisphenol F, allylated naphthyl glycol, phenol novolac, phenols such as phenol and / or naphthols are combined with dimethoxy-p-xylene or bis (methoxymethyl) Phenol aralkyl resin, naphthol aralkyl resin, etc. synthesized by benzene. These may be used alone or in combination of two or more. Among these, the (a2) component may be a phenol aralkyl resin or a naphthol aralkyl resin.

(a2)成分的羥基當量較佳為70 g/eq以上,更佳為70 g/eq~300 g/eq。若(a2)成分的羥基當量為70 g/eq以上,則有膜的儲存彈性係數進一步提升的傾向,若為300 g/eq以下,則能夠防止因產生發泡、逸氣等所導致的不良。The hydroxyl equivalent of the component (a2) is preferably 70 g / eq or more, and more preferably 70 g / eq to 300 g / eq. If the hydroxyl equivalent of the component (a2) is 70 g / eq or more, the storage elastic coefficient of the film tends to be further improved. If it is 300 g / eq or less, it is possible to prevent defects caused by foaming and outgassing. .

(a2)成分的軟化點較佳為50℃~200℃,更佳為60℃~150℃。若(a2)成分的軟化點為200℃以下,則有可抑制與環氧樹脂的相容性下降的傾向。The softening point of the component (a2) is preferably 50 ° C to 200 ° C, and more preferably 60 ° C to 150 ° C. When the softening point of the component (a2) is 200 ° C. or lower, a decrease in compatibility with the epoxy resin tends to be suppressed.

就硬化性的觀點而言,(a1)成分的環氧當量與(a2)成分的羥基當量的比((a1)成分的環氧當量/(a2)成分的羥基當量)可為0.30/0.70~0.70/0.30、0.35/0.65~0.65/0.35、0.40/0.60~0.60/0.40、或0.45/0.55~0.55/0.45。若該當量比為0.30/0.70以上,則有可獲得更充分的硬化性的傾向。若該當量比為0.70/0.30以下,則可防止黏度變得過高,可獲得更充分的流動性。From the viewpoint of hardenability, the ratio of the epoxy equivalent of the (a1) component to the hydroxyl equivalent of the (a2) component (the epoxy equivalent of the (a1) component / the hydroxyl equivalent of the (a2) component) may be 0.30 / 0.70 to 0.70 / 0.30, 0.35 / 0.65 to 0.65 / 0.35, 0.40 / 0.60 to 0.60 / 0.40, or 0.45 / 0.55 to 0.55 / 0.45. If this equivalent ratio is 0.30 / 0.70 or more, there exists a tendency for sufficient hardenability to be obtained. When the equivalent ratio is 0.70 / 0.30 or less, it is possible to prevent the viscosity from becoming too high and obtain more sufficient fluidity.

相對於(a)成分、(b)成分及(c)成分的總質量100質量份,(a)成分的含量可為5質量份~70質量份、10質量份~65質量份、或20質量份~60質量份。若(a)成分的含量為5質量份以上,則有藉由交聯而彈性係數提升的傾向。若(a)成分的含量為70質量份以下,則有可維持膜操作性,並且剪切黏度及彈性係數容易成為所期望的範圍的傾向。The content of the component (a) may be 5 to 70 parts by mass, 10 to 65 parts by mass, or 20 parts by mass based on 100 parts by mass of the total mass of the components (a), (b), and (c). Parts to 60 parts by mass. When the content of the component (a) is 5 parts by mass or more, the elasticity coefficient tends to be improved by crosslinking. When the content of the component (a) is 70 parts by mass or less, the film operability can be maintained, and the shear viscosity and the elastic coefficient tend to fall within a desired range.

(b)高分子量成分
(b)成分較佳為玻璃轉移溫度(Tg)為50℃以下者。作為(b)成分,例如可列舉:丙烯酸樹脂、聚酯樹脂、聚醯胺樹脂、聚醯亞胺樹脂、矽酮樹脂、丁二烯樹脂、丙烯腈樹脂等;該些的改質體等。
(B) The high molecular weight component (b) is preferably one having a glass transition temperature (Tg) of 50 ° C or lower. Examples of the component (b) include acrylic resins, polyester resins, polyamide resins, polyimide resins, silicone resins, butadiene resins, and acrylonitrile resins; and such modified bodies.

就流動性的觀點而言,(b)成分可包含丙烯酸樹脂。此處,所謂丙烯酸樹脂,是指包含源自(甲基)丙烯酸酯的結構單元的聚合物。丙烯酸樹脂較佳為包含源自具有環氧基、醇性或酚性羥基、羧基等交聯性官能基的(甲基)丙烯酸酯的結構單元作為結構單元的聚合物。另外,丙烯酸樹脂亦可為(甲基)丙烯酸酯與丙烯腈的共聚物等丙烯酸橡膠。From the viewpoint of fluidity, the component (b) may include an acrylic resin. Here, the acrylic resin refers to a polymer including a structural unit derived from a (meth) acrylate. The acrylic resin is preferably a polymer containing, as a structural unit, a structural unit derived from a (meth) acrylate having a crosslinkable functional group such as an epoxy group, an alcoholic or phenolic hydroxyl group, and a carboxyl group. The acrylic resin may be an acrylic rubber such as a copolymer of (meth) acrylate and acrylonitrile.

丙烯酸樹脂的玻璃轉移溫度(Tg)可為-50℃~50℃或-30℃~30℃。若丙烯酸樹脂的Tg為-50℃以上,則有可防止接著劑的柔軟性變得過高的傾向。藉此,於晶圓切割時容易將膜狀接著劑切斷,能夠防止毛刺的產生。若丙烯酸樹脂的Tg為50℃以下,則有可抑制接著劑的柔軟性下降的傾向。藉此,當將膜狀接著劑貼附於晶圓時,有容易將空隙充分埋入的傾向。另外,能夠防止因晶圓的密接性的下降所導致的切割時的碎化(chipping)。此處,玻璃轉移溫度(Tg)是使用示差掃描熱量計(Differential Scanning Calorimeter,DSC)(例如理學股份有限公司製造的「Thermo Plus 2」)所測定出的值。The glass transition temperature (Tg) of the acrylic resin may be -50 ° C to 50 ° C or -30 ° C to 30 ° C. When the Tg of the acrylic resin is −50 ° C. or higher, the flexibility of the adhesive tends to be prevented from becoming too high. This makes it easy to cut the film-like adhesive during wafer dicing, and prevents the occurrence of burrs. When the Tg of the acrylic resin is 50 ° C or lower, there is a tendency that the softness of the adhesive can be suppressed from decreasing. Thereby, when a film-shaped adhesive is attached to a wafer, it tends to be easy to fully embed a space | gap. In addition, chipping at the time of dicing due to a decrease in the adhesiveness of the wafer can be prevented. Here, the glass transition temperature (Tg) is a value measured using a differential scanning calorimeter (DSC) (for example, "Thermo Plus 2" manufactured by Rigaku Corporation).

丙烯酸樹脂的重量平均分子量(Mw)可為10萬~300萬或50萬~200萬。若丙烯酸樹脂的Mw為此種範圍,則可適當地控制膜形成性、膜狀時的強度、可撓性、黏性等,並且回流性優異,可提升埋入性。另外,藉由使用Mw低(例如小於10萬)的丙烯酸樹脂,進而增加Mw低(例如小於10萬)的丙烯酸樹脂的添加量,則埋入性有提升的傾向,但剪切黏度及硬化後的儲存彈性係數有變低的傾向。此處,Mw是指藉由凝膠滲透層析法(Gel Permeation Chromatography,GPC)進行測定,並使用基於標準聚苯乙烯的校準曲線進行換算而得的值。The weight average molecular weight (Mw) of the acrylic resin may be 100,000 to 3 million or 500,000 to 2 million. When the Mw of the acrylic resin is within such a range, the film forming properties, strength, flexibility, and tackiness at the time of the film shape can be appropriately controlled, and the reflow properties can be excellent, and the embedding properties can be improved. In addition, by using an acrylic resin having a low Mw (for example, less than 100,000) and further increasing the addition amount of the acrylic resin having a low Mw (for example, less than 100,000), the embedding property tends to be improved, but after shear viscosity and hardening The storage elastic coefficient tends to be lower. Here, Mw is a value measured by gel permeation chromatography (GPC) and converted using a calibration curve based on standard polystyrene.

作為丙烯酸樹脂的市售品,例如可列舉:SG-70L、SG-708-6、WS-023 EK30、SG-280 EK23、HTR-860P-3CSP、HTR-860P-3CSP-30B(均為長瀨化成(Nagase ChemteX)股份有限公司製造)。Examples of commercially available acrylic resins include SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, HTR-860P-3CSP, HTR-860P-3CSP-30B (all of Nagase (Manufactured by Nagase ChemteX).

相對於(a)成分、(b)成分及(c)成分的總質量100質量份,(b)成分的含量可為5質量份~95質量份、5質量份~85質量份、或10質量份~80質量份。若(b)成分的含量為5質量份以上,則有80℃下的膜的剪切黏度變高的傾向。The content of the component (b) may be 5 to 95 parts by mass, 5 to 85 parts by mass, or 10 parts by mass based on 100 parts by mass of the total mass of the components (a), (b), and (c). Parts to 80 parts by mass. When the content of the component (b) is 5 parts by mass or more, the shear viscosity of the film at 80 ° C tends to be high.

(c)無機填料
作為(c)成分,例如可列舉:氫氧化鋁、氫氧化鎂、碳酸鈣、碳酸鎂、矽酸鈣、矽酸鎂、氧化鈣、氧化鎂、氧化鋁、氮化鋁、硼酸鋁晶鬚、氮化硼、二氧化矽等。該些可單獨使用一種或者將兩種以上組合使用。該些中,就熔融黏度的調整的觀點而言,(c)成分可為二氧化矽。
(C) Inorganic fillers As the component (c), for example, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, Aluminum borate whiskers, boron nitride, silicon dioxide, etc. These may be used alone or in combination of two or more. Among these, from the viewpoint of adjustment of the melt viscosity, the component (c) may be silicon dioxide.

就流動性的觀點而言,(c)成分的平均粒徑可為0.01 μm~1 μm、0.01 μm~0.08 μm、或0.03 μm~0.06 μm。此處,平均粒徑是指藉由根據布厄特(Brunauer-Emmett-Teller,BET)比表面積進行換算而求出的值。From the viewpoint of fluidity, the average particle diameter of the component (c) may be 0.01 μm to 1 μm, 0.01 μm to 0.08 μm, or 0.03 μm to 0.06 μm. Here, the average particle diameter refers to a value obtained by conversion from a specific surface area of Brunauer-Emmett-Teller (BET).

相對於(a)成分、(b)成分及(c)成分的總質量100質量份,(c)成分的含量可為3質量份~80質量份、3質量份~70質量份、或3質量份~60質量份。若(c)成分的含量為3質量份以上,則有剪切黏度及彈性係數進一步提升的傾向。The content of the component (c) may be 3 to 80 parts by mass, 3 to 70 parts by mass, or 3 parts by mass based on 100 parts by mass of the total mass of the components (a), (b), and (c). Parts to 60 parts by mass. When the content of the component (c) is 3 parts by mass or more, the shear viscosity and the elastic coefficient tend to be further improved.

(d)偶合劑
(d)成分可為矽烷偶合劑。作為矽烷偶合劑,例如可列舉:γ-脲基丙基三乙氧基矽烷、γ-巰基丙基三甲氧基矽烷、3-苯基胺基丙基三甲氧基矽烷、3-(2-胺基乙基)胺基丙基三甲氧基矽烷等。該些可單獨使用一種或者將兩種以上組合使用。
(D) Coupling agent (d) The component may be a silane coupling agent. Examples of the silane coupling agent include γ-ureidopropyltriethoxysilane, γ-mercaptopropyltrimethoxysilane, 3-phenylaminopropyltrimethoxysilane, and 3- (2-amine Ethyl) aminopropyltrimethoxysilane and the like. These may be used alone or in combination of two or more.

(e)硬化促進劑
(e)成分並無特別限定,可使用通常所使用者。作為(e)成分,例如可列舉:咪唑類及其衍生物、有機磷系化合物、二級胺類、三級胺類、四級銨鹽等。該些可單獨使用一種或者將兩種以上組合使用。該些中,就反應性的觀點而言,(e)成分可為咪唑類及其衍生物。
(E) The component of the hardening accelerator (e) is not particularly limited and can be used by ordinary users. Examples of the component (e) include imidazoles and derivatives thereof, organophosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. These may be used alone or in combination of two or more. Among these, from the viewpoint of reactivity, the component (e) may be imidazoles and derivatives thereof.

作為咪唑類,例如可列舉:2-甲基咪唑、1-苄基-2-甲基咪唑、1-氰基乙基-2-苯基咪唑、1-氰基乙基-2-甲基咪唑等。該些可單獨使用一種或者將兩種以上組合使用。Examples of the imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, and 1-cyanoethyl-2-methylimidazole Wait. These may be used alone or in combination of two or more.

第一膜3a及第二膜3b亦可更含有其他成分。作為其他成分,例如可列舉顏料、離子捕捉劑、抗氧化劑等。The first film 3a and the second film 3b may further contain other components. Examples of the other components include pigments, ion trapping agents, and antioxidants.

相對於(a)成分、(b)成分及(c)成分的總質量100質量份,(d)成分、(e)成分及其他成分的含量可為0質量份~30質量份。The content of the (d) component, the (e) component, and other components may be 0 to 30 parts by mass with respect to 100 parts by mass of the total mass of the components (a), (b), and (c).

第一膜3a及第二膜3b可藉由以下方式形成:製備含有(a)成分~(c)成分、視需要的(d)成分及(e)成分以及溶劑的第一接著劑清漆及第二接著劑清漆,將該些塗佈於基材膜,並進行加熱乾燥而將溶劑去除。第一接著劑清漆及第二接著劑清漆例如可藉由將(a)成分~(e)成分於溶劑中混合、混煉而進行製備。The first film 3a and the second film 3b can be formed by preparing a first adhesive varnish and a first adhesive containing (a) component to (c) component, and optionally (d) component and (e) component, and a solvent. Two adhesive varnishes are applied to the substrate film, followed by heating and drying to remove the solvent. The first adhesive varnish and the second adhesive varnish can be prepared, for example, by mixing (a) component to (e) component in a solvent and kneading.

混合、混煉可使用通常的攪拌機、擂潰機、三輥磨機(three-rod roll mill)、球磨機(ball mill)等分散機,將該些適當組合而進行。Mixing and kneading can be carried out by using an appropriate combination of these dispersers such as a general mixer, a masher, a three-rod roll mill, and a ball mill.

用於製作第一接著劑清漆及第二接著劑清漆的溶劑只要為可將所述各成分均勻地溶解、混煉或分散者則可無限制地使用現有公知者。作為此種溶劑,例如可列舉:丙酮、甲基乙基酮、甲基異丁基酮、環己酮等酮系溶媒;二甲基甲醯胺、二甲基乙醯胺、N-甲基吡咯啶酮、甲苯、二甲苯等。就乾燥速度快、價格低的方面而言,較佳為使用甲基乙基酮、環己酮等。As long as the solvent for producing the first adhesive varnish and the second adhesive varnish is capable of uniformly dissolving, kneading, or dispersing the components described above, a conventionally known one can be used without limitation. Examples of such solvents include ketone solvents such as acetone, methyl ethyl ketone, methyl isobutyl ketone, and cyclohexanone; dimethylformamide, dimethylacetamide, and N-methyl Pyrrolidone, toluene, xylene and the like. In terms of fast drying speed and low price, it is preferable to use methyl ethyl ketone, cyclohexanone, or the like.

作為將第一接著劑清漆及第二接著劑清漆塗佈於基材膜的方法,可使用公知的方法,例如可列舉:刮塗法、輥塗法、噴塗法、凹版塗佈法、棒塗法、簾塗法等。加熱乾燥的條件只要為所使用的溶劑充分揮發的條件則無特別限制,例如可於50℃~150℃下加熱1分鐘~30分鐘來進行。As a method of applying the first adhesive varnish and the second adhesive varnish to the substrate film, a known method can be used, and examples thereof include a blade coating method, a roll coating method, a spray coating method, a gravure coating method, and a bar coating. Method, curtain coating method, etc. The conditions for heating and drying are not particularly limited as long as the solvent used is sufficiently volatilized, and for example, heating can be performed at 50 ° C to 150 ° C for 1 to 30 minutes.

第一膜3a的厚度可根據所製造的半導體裝置的形狀或尺寸而適當設定,例如可為1 μm~200 μm。第一膜3a的厚度可為3 μm~150 μm、或3 μm~120 μm。再者,FOW用途中,較佳為20 μm~120 μm,更佳為30 μm~80 μm。為了埋入導線,需要確保足夠的厚度以使導線不與晶片接觸。FOD用途中,較佳為40 μm~200 μm,更佳為60 μm~150 μm。為了埋入晶片(例如晶片控制器),依存於其厚度,重要的是確保足夠的厚度。The thickness of the first film 3a may be appropriately set according to the shape or size of the semiconductor device to be manufactured, and may be, for example, 1 μm to 200 μm. The thickness of the first film 3a may be 3 μm to 150 μm, or 3 μm to 120 μm. Furthermore, in FOW applications, it is preferably 20 μm to 120 μm, and more preferably 30 μm to 80 μm. In order to embed the wires, it is necessary to ensure a sufficient thickness so that the wires do not contact the wafer. In FOD applications, it is preferably 40 μm to 200 μm, and more preferably 60 μm to 150 μm. In order to embed a wafer (such as a wafer controller), it is important to ensure a sufficient thickness depending on its thickness.

第二膜3b的厚度可根據所製造的半導體裝置的形狀或尺寸而適當設定,例如可為3 μm~150 μm。第二膜3b的厚度可為3 μm~100 μm、或3 μm~50 μm。再者,FOW用途中,較佳為3 μm~150 μm,更佳為3 μm~80 μm。為了埋入導線,需要確保足夠的厚度以使導線不與晶片接觸。FOD用途中,較佳為3 μm~150 μm,更佳為3 μm~100 μm。為了埋入晶片(例如晶片控制器),依存於其厚度,重要的是確保足夠的厚度。The thickness of the second film 3b may be appropriately set according to the shape or size of the semiconductor device to be manufactured, and may be, for example, 3 μm to 150 μm. The thickness of the second film 3b may be 3 μm to 100 μm, or 3 μm to 50 μm. Furthermore, in FOW applications, it is preferably 3 μm to 150 μm, and more preferably 3 μm to 80 μm. In order to embed the wires, it is necessary to ensure a sufficient thickness so that the wires do not contact the wafer. In FOD applications, it is preferably 3 μm to 150 μm, and more preferably 3 μm to 100 μm. In order to embed a wafer (such as a wafer controller), it is important to ensure a sufficient thickness depending on its thickness.

由第一膜3a與第二膜3b所構成的接著膜130的厚度可根據所製造的半導體裝置的形狀或尺寸而適當設定,較佳為6 μm~300 μm,更佳為10 μm~250 μm,進而佳為20 μm~200 μm。再者,FOW用途中,較佳為40 μm~250 μm,更佳為50 μm~80 μm。為了埋入導線,需要確保足夠的厚度以使導線不與晶片接觸。FOD用途中,較佳為60 μm~250 μm,更佳為80 μm~150 μm。為了埋入晶片(例如晶片控制器),依存於其厚度,重要的是確保足夠的厚度。The thickness of the adhesive film 130 composed of the first film 3a and the second film 3b can be appropriately set according to the shape or size of the semiconductor device to be manufactured, and is preferably 6 μm to 300 μm, and more preferably 10 μm to 250 μm. , And more preferably 20 μm to 200 μm. Furthermore, in FOW applications, it is preferably 40 μm to 250 μm, and more preferably 50 μm to 80 μm. In order to embed the wires, it is necessary to ensure a sufficient thickness so that the wires do not contact the wafer. In FOD applications, it is preferably 60 μm to 250 μm, and more preferably 80 μm to 150 μm. In order to embed a wafer (such as a wafer controller), it is important to ensure a sufficient thickness depending on its thickness.

第一膜3a的80℃下的剪切黏度若與第二膜3b的80℃下的剪切黏度不同,則並無特別限制。第一膜3a的80℃下的剪切黏度若高於第二膜3b的80℃下的剪切黏度,則第二膜3b對翹曲應力加以緩衝而使半導體基板的翹曲難以傳遞至晶片上表面,因而,結果有抑制半導體基板的翹曲的傾向。另外,若低於第二膜3b的80℃下的剪切黏度,則第二膜3b難以追隨因晶片及半導體基板的翹曲所導致的應力,因而有抑制半導體基板的翹曲的傾向。就進一步抑制半導體基板的翹曲的觀點而言,第一膜3a的80℃下的剪切黏度較佳為低於第二膜3b的80℃下的剪切黏度。If the shear viscosity at 80 ° C of the first film 3a is different from the shear viscosity at 80 ° C of the second film 3b, it is not particularly limited. If the shear viscosity at 80 ° C of the first film 3a is higher than the shear viscosity at 80 ° C of the second film 3b, the second film 3b buffers the warping stress and makes it difficult for the warpage of the semiconductor substrate to be transferred to the wafer As a result, there is a tendency that the warpage of the semiconductor substrate is suppressed as a result. If the shear viscosity at 80 ° C. of the second film 3b is lower than the second film 3b, it is difficult for the second film 3b to follow the stress caused by the warpage of the wafer and the semiconductor substrate, and thus the warpage of the semiconductor substrate tends to be suppressed. From the viewpoint of further suppressing the warpage of the semiconductor substrate, the shear viscosity at 80 ° C of the first film 3a is preferably lower than the shear viscosity at 80 ° C of the second film 3b.

第一膜3a的80℃下的剪切黏度例如可為500 Pa·s~30000 Pa·s。第一膜3a的80℃下的剪切黏度可為500 Pa·s以上、700 Pa·s以上、或1000 Pa·s以上。若第一膜3a的80℃下的剪切黏度為500 Pa·s以上,則有膜的操作性更優異的傾向。第一膜3a的80℃下的剪切黏度可為30000 Pa·s以下、20000 Pa·s以下、或15000 Pa·s以下。若第一膜3a的80℃下的剪切黏度為30000 Pa·s以下,則可充分埋入晶片、導線或半導體基板,有可抑制翹曲的傾向。The shear viscosity at 80 ° C. of the first film 3 a may be, for example, 500 Pa · s to 30,000 Pa · s. The shear viscosity at 80 ° C. of the first film 3 a may be 500 Pa · s or more, 700 Pa · s or more, or 1000 Pa · s or more. When the shear viscosity at 80 ° C. of the first film 3 a is 500 Pa · s or more, the handleability of the film tends to be more excellent. The shear viscosity at 80 ° C. of the first film 3 a may be 30,000 Pa · s or less, 20,000 Pa · s or less, or 15000 Pa · s or less. When the shear viscosity at 80 ° C. of the first film 3 a is 30,000 Pa · s or less, a wafer, a lead, or a semiconductor substrate can be sufficiently embedded, and warpage tends to be suppressed.

第二膜3b的80℃下的剪切黏度與第一膜3a不同。第二膜3b的80℃下的剪切黏度為500 Pa·s以上。第二膜3b的80℃下的剪切黏度若為滿足此種條件者則並無特別限制。根據與所述相同的理由,就進一步抑制半導體基板的翹曲的觀點而言,第二膜3b的80℃下的剪切黏度較佳為高於第一膜3a的80℃下的剪切黏度。The shear viscosity at 80 ° C. of the second film 3 b is different from that of the first film 3 a. The shear viscosity at 80 ° C of the second film 3b is 500 Pa · s or more. The shear viscosity at 80 ° C of the second film 3b is not particularly limited as long as it satisfies such conditions. For the same reason as described above, from the viewpoint of further suppressing the warpage of the semiconductor substrate, the shear viscosity at 80 ° C of the second film 3b is preferably higher than the shear viscosity at 80 ° C of the first film 3a. .

第二膜3b的80℃下的剪切黏度為500 Pa·s以上,且可為3000 Pa·s以上、5000 Pa·s以上、10000 Pa·s以上、15000 Pa·s以上、20000 Pa·s以上、或25000 Pa·s以上。若第二膜3b的80℃下的剪切黏度為500 Pa·s以上,則有膜的操作性更優異的傾向。第二膜3b的80℃下的剪切黏度的上限並無特別限制,可為100000 Pa·s以下、70000 Pa·s以下、或50000 Pa·s以下。The shear viscosity at 80 ° C of the second film 3b is 500 Pa · s or more, and may be 3,000 Pa · s or more, 5000 Pa · s or more, 10,000 Pa · s or more, 15000 Pa · s or more, and 20,000 Pa · s. Above, or above 25,000 Pa · s. When the shear viscosity at 80 ° C. of the second film 3 b is 500 Pa · s or more, the handleability of the film tends to be more excellent. The upper limit of the shear viscosity at 80 ° C. of the second film 3 b is not particularly limited, and may be 100,000 Pa · s or less, 70,000 Pa · s, or 50,000 Pa · s or less.

再者,第一膜3a及第二膜3b的80℃下的剪切黏度例如可藉由實施例中記載的方法進行測定。The shear viscosity at 80 ° C. of the first film 3 a and the second film 3 b can be measured, for example, by the method described in the examples.

第一膜3a及第二膜3b的80℃下的剪切黏度例如可藉由改變該些膜中所含有的成分的種類及含量來進行調整。The shear viscosities at 80 ° C. of the first film 3 a and the second film 3 b can be adjusted by, for example, changing the types and contents of the components contained in these films.

第一膜3a的硬化後的150℃下的儲存彈性係數並無特別限制,可為1000 MPa以下、500 MPa以下、或300 MPa以下,且可為10 MPa以上、15 MPa以上、或20 MPa以上。若第一膜3a的硬化後的150℃下的儲存彈性係數為1000 MPa以下,則可充分埋入晶片、導線或半導體基板,有可抑制翹曲的傾向。若第一膜3a的硬化後的150℃下的儲存彈性係數為10 MPa以上,則有於壓接時防止膜的擠壓,可抑制自晶片的端部露出的傾向。The storage elastic coefficient at 150 ° C of the first film 3a after curing is not particularly limited, and may be 1000 MPa or less, 500 MPa or less, or 300 MPa or less, and may be 10 MPa or more, 15 MPa, or 20 MPa or more . When the storage elastic coefficient at 150 ° C. of the first film 3 a after curing is 1000 MPa or less, the wafer, the lead, or the semiconductor substrate can be sufficiently embedded, and the warpage tends to be suppressed. If the storage elastic coefficient at 150 ° C. of the first film 3 a after curing is 10 MPa or more, it is possible to prevent the film from being squeezed at the time of pressure bonding, and it is possible to suppress exposure from the ends of the wafer.

第二膜3b的硬化後的150℃下的儲存彈性係數可為1000 MPa以下。第二膜3b的硬化後的150℃下的儲存彈性係數可為500 MPa以下、100 MPa以下、或70 MPa以下,且可為10 MPa以上、15 MPa以上、或20 MPa以上。若第二膜3b的硬化後的150℃下的儲存彈性係數為1000 MPa以下,則有可進一步緩和半導體基板或晶片的翹曲的傾向。The storage elastic coefficient at 150 ° C. of the second film 3 b after curing may be 1000 MPa or less. The storage elastic coefficient at 150 ° C. of the second film 3 b after curing may be 500 MPa or less, 100 MPa or less, or 70 MPa or less, and may be 10 MPa or more, 15 MPa or more, or 20 MPa or more. When the storage elastic coefficient at 150 ° C. of the second film 3 b after curing is 1000 MPa or less, there is a tendency that the warpage of the semiconductor substrate or wafer can be further alleviated.

再者,第一膜3a及第二膜3b的硬化後的150℃下的儲存彈性係數例如可藉由實施例中記載的方法進行測定。The storage elastic coefficients at 150 ° C. after the first film 3 a and the second film 3 b are cured can be measured, for example, by the method described in the examples.

接著膜130可藉由使用輥層壓機、真空層壓機等,將第一膜3a與第二膜3b於規定條件(例如室溫(20℃)或加熱狀態)下層壓,並去除基材膜4a及基材膜4b而進行製作。Next, the film 130 can be laminated on the first film 3a and the second film 3b under a predetermined condition (for example, room temperature (20 ° C) or a heated state) by using a roll laminator, a vacuum laminator, and the like, and the substrate can be removed. The film 4a and the base film 4b were produced.

接著膜130亦可藉由以下方式進行製作:首先,將第一接著劑組成物的清漆塗佈於基材膜,並進行加熱乾燥而將溶劑去除,製作第一膜3a,繼而,於第一膜3a上塗佈第二接著劑組成物的清漆,並進行加熱乾燥而將溶劑去除,形成第二接著膜,並去除基材膜。Next, the film 130 can also be produced by firstly coating the varnish of the first adhesive composition on the substrate film and heating and drying to remove the solvent to produce a first film 3a. The varnish of the second adhesive composition is applied to the film 3a, and the solvent is removed by heating and drying to form a second adhesive film, and the base film is removed.

半導體晶圓A並無特別限定,例如可使用10 μm~100 μm的薄型半導體晶圓。另外,作為半導體晶圓A,除單晶矽以外,亦可列舉多晶矽、各種陶瓷、砷化鎵等化合物半導體等。The semiconductor wafer A is not particularly limited, and for example, a thin semiconductor wafer of 10 μm to 100 μm can be used. In addition, as the semiconductor wafer A, in addition to single crystal silicon, compound semiconductors such as polycrystalline silicon, various ceramics, and gallium arsenide can also be cited.

[切割步驟]
其後,如圖5所示,使用例如刀片B來切割帶有接著膜的半導體晶圓300,進而加入清洗、乾燥步驟。藉此而切割至接著膜130,獲得帶有接著膜的(經單片化的)半導體晶片。切割時亦可使用切割器來代替刀片B。作為刀片B,例如可使用迪思科(Disco)股份有限公司製造的切割刀片NBC-ZH05系列、NBC-ZH系列等。作為切割器,例如可使用全自動切割鋸(full automatic dicing saw)6000系列、半自動切割鋸(semi-automatic dicing saw)3000系列(均為迪思科股份有限公司製造)等。再者,於切割時,於半導體晶圓A的周圍配置晶圓環(未圖示),經由接著膜來將半導體晶圓A固定。半導體晶圓A對接著膜的貼附面可為電路面,亦可為電路面的相反面。
[Cutting steps]
Thereafter, as shown in FIG. 5, the semiconductor wafer 300 with an adhesive film is cut using, for example, a blade B, and then a cleaning and drying step is added. This cuts the adhesive film 130 to obtain a (singulated) semiconductor wafer with an adhesive film. It is also possible to use a cutter instead of the blade B when cutting. As the blade B, for example, cutting blades NBC-ZH05 series, NBC-ZH series, etc. manufactured by Disco Co., Ltd. can be used. As the cutter, for example, a full automatic dicing saw 6000 series, a semi-automatic dicing saw 3000 series (both manufactured by Disco) can be used. Further, at the time of dicing, a wafer ring (not shown) is arranged around the semiconductor wafer A, and the semiconductor wafer A is fixed via an adhesive film. The attachment surface of the semiconductor wafer A to the adhesive film may be a circuit surface or an opposite surface of the circuit surface.

半導體晶片尺寸較佳為一邊為20 mm以下,即20 mm×20 mm以下。半導體晶片尺寸更佳為一邊為3 mm~15 mm,進而佳為一邊為5 mm~10 mm。再者,半導體基板亦包含晶片或同標準者。The size of the semiconductor wafer is preferably 20 mm or less on one side, that is, 20 mm × 20 mm or less. The size of the semiconductor wafer is more preferably 3 mm to 15 mm on one side, and still more preferably 5 mm to 10 mm on one side. Furthermore, the semiconductor substrate also includes a wafer or the same standard.

[紫外線照射步驟]
亦可更包括於切割步驟後,對黏著膜2照射紫外線(ultraviolet,UV)的紫外線照射步驟(圖6)。藉此,可將黏著膜2的一部分或大部分聚合硬化。紫外線照射的照度並無特別限定,較佳為10 mW/cm2 ~200 mW/cm2 ,更佳為20 mW/cm2 ~150 mW/cm2 。另外,紫外線照射時的照射量並無特別限定,較佳為50 mJ/cm2 ~400 mJ/cm2 ,更佳為100 mJ/cm2 ~250 mJ/cm2
[UV irradiation step]
It may further include an ultraviolet irradiation step (ultraviolet, UV) of the adhesive film 2 after the cutting step (FIG. 6). Thereby, a part or most of the adhesive film 2 can be polymerized and hardened. The illuminance of ultraviolet irradiation is not particularly limited, but is preferably 10 mW / cm 2 to 200 mW / cm 2 , and more preferably 20 mW / cm 2 to 150 mW / cm 2 . The amount of irradiation during ultraviolet irradiation is not particularly limited, but is preferably 50 mJ / cm 2 to 400 mJ / cm 2 , and more preferably 100 mJ / cm 2 to 250 mJ / cm 2 .

[拾取步驟]
於拾取步驟中,例如藉由吸引夾頭5來拾取應拾取的半導體晶片a。此時,亦可自基材膜1的下表面,利用例如針桿等來上推應拾取的半導體晶片a。若以半導體晶片a與接著膜130之間的密接力高於黏著膜2與基材膜1之間及接著膜130與黏著膜2之間的密接力的方式進行半導體晶片a的拾取,則將接著膜130以附著於半導體晶片a的下表面的狀態剝離(參照圖7)。
[Pickup step]
In the pickup step, the semiconductor wafer a to be picked up is picked up by, for example, the suction chuck 5. At this time, the semiconductor wafer a to be picked up may be pushed up from the lower surface of the base film 1 by, for example, a needle bar or the like. If the semiconductor wafer a is picked up in such a manner that the adhesion between the semiconductor wafer a and the adhesive film 130 is higher than the adhesion between the adhesive film 2 and the substrate film 1 and between the adhesive film 130 and the adhesive film 2, Then, the film 130 is peeled while being adhered to the lower surface of the semiconductor wafer a (see FIG. 7).

黏著膜2與第一膜3a的密接力較佳為小於半導體晶圓A與第二膜3b的密接力。若密接力為此種關係,則當於拾取步驟中上推晶片時,可防止在第一膜3a與第二膜3b之間發生剝離。若在第一膜3a與第二膜3b的界面發生剝離,則有無法獲得翹曲的減少效果的傾向。The adhesion force between the adhesive film 2 and the first film 3a is preferably smaller than the adhesion force between the semiconductor wafer A and the second film 3b. If the adhesion force is such a relationship, peeling between the first film 3a and the second film 3b can be prevented when the wafer is pushed up in the pickup step. When peeling occurs at the interface between the first film 3a and the second film 3b, there is a tendency that the effect of reducing warpage cannot be obtained.

[壓接步驟]
繼而,經由接著膜130而將半導體晶片a載置於半導體基板6來進行加熱。藉由加熱,接著膜130顯現充分的接著力,從而完成經由接著膜的硬化物130c的半導體晶片a與半導體基板6的接著(圖8)。再者,作為半導體基板6,例如可列舉半導體晶片搭載用支撐構件、其他半導體晶片等。
[Crimping step]
Then, the semiconductor wafer a is placed on the semiconductor substrate 6 via the adhesive film 130 and heated. By heating, the adhesive film 130 exhibits sufficient adhesive force, thereby completing the bonding of the semiconductor wafer a and the semiconductor substrate 6 via the cured product 130 c of the adhesive film (FIG. 8). Examples of the semiconductor substrate 6 include support members for mounting a semiconductor wafer, other semiconductor wafers, and the like.

壓接溫度並無特別限定,較佳為50℃~200℃,更佳為100℃~150℃。若壓接溫度高,則接著膜3變軟,因而有埋入性提升的傾向。壓接時間並無特別限定,較佳為0.5秒~20秒,更佳為1秒~5秒。壓接時的壓力並無特別限定,較佳為0.01 MPa~5 MPa,更佳為0.02 MPa~2 MPa。於FOW及FOD用途中,為提升埋入性,將壓接壓力設定得越高則越佳。The compression bonding temperature is not particularly limited, but is preferably 50 ° C to 200 ° C, and more preferably 100 ° C to 150 ° C. If the pressure-bonding temperature is high, the adhesive film 3 becomes soft, so that the embedding property tends to be improved. The crimping time is not particularly limited, but is preferably 0.5 to 20 seconds, and more preferably 1 to 5 seconds. The pressure at the time of compression bonding is not particularly limited, but is preferably 0.01 MPa to 5 MPa, and more preferably 0.02 MPa to 2 MPa. In FOW and FOD applications, in order to improve the embedding property, the higher the crimping pressure is set, the better.

[硬化步驟]
於壓接步驟後,實施使接著膜130硬化的硬化步驟。用以使接著膜130硬化的溫度及時間可根據接著膜中所含的成分的硬化溫度來適當設定。可使溫度階段地變化,亦可使用具有此種機構者。溫度及時間可為例如40℃~300℃,且可為例如30分鐘~300分鐘。
[Hardening step]
After the crimping step, a hardening step of hardening the adhesive film 130 is performed. The temperature and time for curing the adhesive film 130 can be appropriately set according to the curing temperature of the components contained in the adhesive film. The temperature can be changed stepwise, and a person having such a mechanism can also be used. The temperature and time may be, for example, 40 ° C to 300 ° C, and may be, for example, 30 minutes to 300 minutes.

<半導體裝置>
使用圖式來對藉由本實施形態的製造方法而獲得的半導體裝置的態樣進行具體說明。再者,近年來提出有各種結構的半導體裝置,藉由本實施形態的製造方法而獲得的半導體裝置並不限定於以下所說明的結構。
< Semiconductor device >
The aspect of the semiconductor device obtained by the manufacturing method of this embodiment is specifically described using drawings. In addition, semiconductor devices having various structures have been proposed in recent years, and the semiconductor devices obtained by the manufacturing method of this embodiment are not limited to the structures described below.

圖9是表示半導體裝置的一實施形態的示意剖面圖。圖9所示的半導體裝置400是將作為帶有接著膜的半導體晶片的半導體晶片a經由接著膜130而壓接於半導體基板10而成,而且是將半導體晶片a經由導線11而以打線接合的方式連接於半導體基板10上而成的半導體裝置。該半導體裝置中,半導體晶片a藉由接著膜的硬化物130c而接著於半導體基板10,半導體晶片a的連接端子(未圖示)經由導線11而與外部連接端子(未圖示)電性連接,並藉由密封材12而密封。FIG. 9 is a schematic cross-sectional view showing an embodiment of a semiconductor device. The semiconductor device 400 shown in FIG. 9 is formed by crimping a semiconductor wafer a, which is a semiconductor wafer with a bonding film, to a semiconductor substrate 10 through a bonding film 130, and bonding the semiconductor wafer a with a wire 11 via wires. A semiconductor device which is connected to the semiconductor substrate 10 in a system. In this semiconductor device, the semiconductor wafer a is adhered to the semiconductor substrate 10 by a cured product 130c adhering to the film, and a connection terminal (not shown) of the semiconductor wafer a is electrically connected to an external connection terminal (not shown) via a wire 11. , And sealed by the sealing material 12.

圖10是表示半導體裝置的一實施形態的示意剖面圖。圖10所示的半導體裝置410為導線埋入型的半導體裝置,其是藉由將第一半導體晶片a1 經由第一導線11a而以打線接合的方式連接於半導體基板10上,並且於第一半導體晶片a1 上,經由接著膜130而壓接作為帶有接著膜的半導體晶片的第二半導體晶片a2 ,從而將第一導線11a的至少一部分埋入接著膜130中而成。該半導體裝置中,第一半導體晶片a1 藉由接著膜的硬化物130c1 而接著於形成有端子13的半導體基板10,且於第一半導體晶片a1 上,進而藉由接著膜的硬化物130c2 而接著有第二半導體晶片a2 。第一半導體晶片a1 及第二半導體晶片a2 的連接端子(未圖示)經由第一導線11a及第二導線11b而與電路圖案14電性連接,並藉由密封材12而密封。如上所述,於將多個半導體晶片重合的結構的半導體裝置且需要埋入導線的一部分的情況下,所述製造方法亦可較佳地使用。FIG. 10 is a schematic cross-sectional view showing an embodiment of a semiconductor device. The semiconductor device 410 shown in FIG. 10 is a lead-embedded semiconductor device, which is connected to the semiconductor substrate 10 by wire bonding through the first semiconductor wafer a 1 through the first lead 11 a, and is connected to the first A second semiconductor wafer a 2 , which is a semiconductor wafer with a bonding film, is crimped onto the semiconductor wafer a 1 through the bonding film 130, and at least a part of the first lead 11 a is buried in the bonding film 130. In this semiconductor device, the first semiconductor wafer a 1 is bonded to the semiconductor substrate 10 on which the terminals 13 are formed by a hardened material 130 c 1 that is adhered to the film, and is further bonded to the first semiconductor wafer a 1 by the cured material 130c 2 is followed by a second semiconductor wafer a 2 . The connection terminals (not shown) of the first semiconductor wafer a 1 and the second semiconductor wafer a 2 are electrically connected to the circuit pattern 14 via the first lead wires 11 a and the second lead wires 11 b, and are sealed by the sealing material 12. As described above, in a case where a semiconductor device having a structure in which a plurality of semiconductor wafers are overlapped and a part of a conductive wire needs to be embedded, the manufacturing method can also be preferably used.

圖11及圖12是表示圖10所示的半導體裝置的製造順序的圖。首先,經由接著膜130而將帶有接著膜的第一半導體晶片a1 加熱壓接並接著於半導體基板10。藉由接著膜的硬化物130c1 而將第一半導體晶片a1 埋入。此時,亦可使用其他通常的製造方法。其後,藉由經過打線接合步驟而獲得圖11所示的半導體基板。其次,經由接著膜130而將帶有接著膜的第二半導體晶片a2 加熱壓接並接著於第一半導體晶片a1 。如上所述而獲得圖12所示的半導體基板。其後,藉由進而經過打線接合步驟及密封步驟,而可獲得圖10所示的半導體裝置。11 and 12 are diagrams showing a manufacturing procedure of the semiconductor device shown in FIG. 10. First, the first semiconductor wafer a 1 with an adhesive film is heat-pressed and bonded to the semiconductor substrate 10 via the adhesive film 130. The first semiconductor wafer a 1 is buried by the cured product 130 c 1 adhering to the film. In this case, other general manufacturing methods may be used. Thereafter, the semiconductor substrate shown in FIG. 11 is obtained by going through a wire bonding step. Next, the second semiconductor wafer a 2 with the adhesive film is heat-pressed and bonded to the first semiconductor wafer a 1 via the adhesive film 130. As described above, the semiconductor substrate shown in FIG. 12 is obtained. Thereafter, the semiconductor device shown in FIG. 10 can be obtained by further performing a wire bonding step and a sealing step.

圖13是表示半導體裝置的一實施形態的示意剖面圖。圖13所示的半導體裝置500為晶片埋入型的半導體裝置,其是藉由將第一半導體晶片a3 經由第一導線11a而以打線接合的方式連接於半導體基板10上,並且於第一半導體晶片a3 上,經由接著膜130而壓接為帶有接著膜的半導體晶片且較第一半導體晶片a3 的面積更大的第二半導體晶片a4 ,從而將第一導線11a及第一半導體晶片a3 埋入接著膜130中而成。半導體裝置500中,進而經由第二導線11b而將半導體基板10與第二半導體晶片a4 電性連接,並且藉由密封材12而將第二半導體晶片a4 密封。13 is a schematic cross-sectional view showing an embodiment of a semiconductor device. The semiconductor device 500 shown in FIG. 13 is a wafer-embedded semiconductor device. The first semiconductor wafer a 3 is connected to the semiconductor substrate 10 by wire bonding via a first wire 11 a. On the semiconductor wafer a 3 , the second semiconductor wafer a 4 having a larger area than the first semiconductor wafer a 3 is crimped to the semiconductor wafer with the adhesive film via the bonding film 130, so that the first lead 11 a and the first The semiconductor wafer a 3 is embedded in the adhesive film 130. In the semiconductor device 500, the semiconductor substrate 10 is further electrically connected to the second semiconductor wafer a 4 via the second lead 11 b, and the second semiconductor wafer a 4 is sealed by the sealing material 12.

第一半導體晶片a3 的厚度可為10 μm~170 μm,第二半導體晶片a4 的厚度可為20 μm~400 μm 接著膜的硬化物130c4 的厚度為20 μm~200 μm,較佳為30 μm~200 μm,更佳為40 μm~150 μm。埋入接著膜的硬化物130c4 內部的第一半導體晶片a3 例如為用以驅動半導體裝置500的控制器晶片。The thickness of the first semiconductor wafer a 3 may be 10 μm to 170 μm, and the thickness of the second semiconductor wafer a 4 may be 20 μm to 400 μm . The thickness of the cured film 130c 4 of the subsequent film is 20 μm to 200 μm, preferably 30 μm to 200 μm, and more preferably 40 μm to 150 μm. The first semiconductor wafer a 3 embedded in the cured material 130 c 4 of the adhesive film is, for example, a controller wafer for driving the semiconductor device 500.

半導體基板10例如可為於表面形成有電路圖案14的有機基板。第一半導體晶片a3 經由接著膜的硬化物130c3 而壓接於電路圖案14上,第二半導體晶片a4 以覆蓋未壓接有第一半導體晶片a3 的電路圖案14、第一半導體晶片a3 、第一導線11a及電路圖案14的一部分的方式經由接著膜的硬化物130c4 而壓接於半導體基板10。於由半導體基板10上的電路圖案14所引起的凹凸的階差中埋入有接著膜的硬化物130c4 。並且,藉由樹脂製的密封材12而將第二半導體晶片a4 、電路圖案14、及第二導線11b密封。The semiconductor substrate 10 may be, for example, an organic substrate having a circuit pattern 14 formed on a surface thereof. The first semiconductor wafer a 3 is crimped to the circuit pattern 14 via a cured material 130 c 3 which is a film, and the second semiconductor wafer a 4 covers the circuit pattern 14 and the first semiconductor wafer to which the first semiconductor wafer a 3 is not crimped. The mode of a 3 , a part of the first lead 11 a and the circuit pattern 14 is pressure-bonded to the semiconductor substrate 10 via a cured object 130 c 4 which is a film. A hardened body 130c 4 of the adhesive film is embedded in the step of the unevenness caused by the circuit pattern 14 on the semiconductor substrate 10. Then, the second semiconductor wafer a 4 , the circuit pattern 14, and the second lead 11 b are sealed by a resin sealing material 12.

圖14~圖18是表示圖13所示的半導體裝置的製造順序的圖。首先,如圖14所示,於半導體基板10上的電路圖案14上壓接帶有接著膜的第一半導體晶片a3 ,且經由第一導線11a而將半導體基板10上的電路圖案14與第一半導體晶片a3 電性接合連接。此時,亦可使用其他通常的製造方法。14 to 18 are diagrams showing a manufacturing procedure of the semiconductor device shown in FIG. 13. First, as shown in FIG. 14, a first semiconductor wafer a 3 with a bonding film is crimped onto a circuit pattern 14 on a semiconductor substrate 10, and the circuit pattern 14 on the semiconductor substrate 10 and the first A semiconductor wafer a 3 is electrically bonded. In this case, other general manufacturing methods may be used.

其次,如圖15所示,準備較第一半導體晶片a3 的面積更大的帶有接著膜的第二半導體晶片a4Next, as shown in FIG. 15, a second semiconductor wafer a 4 with a bonding film having a larger area than the first semiconductor wafer a 3 is prepared.

並且,將帶有接著膜的第二半導體晶片a4 壓接於經由第一導線11a而接合連接有第一半導體晶片a3 的半導體基板10。具體而言,如圖16所示,以接著膜覆蓋第一半導體晶片a3 的方式載置帶有接著膜的第二半導體晶片a4 ,繼而,如圖17所示,藉由使第二半導體晶片a4 壓接於半導體基板10而將第二半導體晶片a4 固定於半導體基板10。The second semiconductor wafer a 4 with an adhesive film is crimped to the semiconductor substrate 10 to which the first semiconductor wafer a 3 is bonded and connected via the first wire 11 a. Specifically, as shown in FIG. 16, the second semiconductor wafer a 4 with an adhesive film is placed so that the first semiconductor wafer a 3 is covered by the adhesive film, and then, as shown in FIG. 17, the second semiconductor The wafer a 4 is crimped to the semiconductor substrate 10, and the second semiconductor wafer a 4 is fixed to the semiconductor substrate 10.

繼而,如圖18所示,於將半導體基板10與第二半導體晶片a4 經由第二導線11b而電性連接後,利用密封材12將電路圖案14、第二導線11b及第二半導體晶片a4 密封。藉由經過此種步驟而可製造半導體裝置500。
[實施例]
Next, as shown in FIG. 18, after the semiconductor substrate 10 and the second semiconductor wafer a 4 are electrically connected via the second lead 11 b, the circuit pattern 14, the second lead 11 b and the second semiconductor wafer a are sealed by the sealing material 12. 4 hermetically sealed. The semiconductor device 500 can be manufactured by going through such steps.
[Example]

以下,列舉實施例來對本發明進行更具體的說明。但本發明並不限定於該些實施例。Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to these examples.

<接著劑清漆的製備>
[合成例A~合成例F]
以表1所示的品名及組成比(單位:質量份),於包含作為(a)熱硬化性樹脂的環氧樹脂及酚樹脂、以及(c)無機填料的組成物中添加環己酮,進行攪拌混合。於其中添加表1所示的作為(b)高分子量成分的丙烯酸橡膠並進行攪拌,進而添加表1所示的(d)偶合劑及(e)硬化促進劑來進行攪拌,直至各成分變得均勻,從而製備合成例A~合成例F的接著劑清漆。
< Preparation of adhesive varnish >
[Synthesis example A to synthesis example F]
Cyclohexanone was added to a composition containing (a) an epoxy resin and a phenol resin as a thermosetting resin, and (c) an inorganic filler under the product name and composition ratio (unit: part by mass) shown in Table 1, Stir and mix. The acrylic rubber (b) high-molecular-weight component shown in Table 1 is added and stirred, and the (d) coupling agent and (e) hardening accelerator shown in Table 1 are added and stirred until each component becomes The adhesive varnishes of Synthesis Example A to Synthesis Example F were made uniform.

再者,表1中的各成分的記號是指下述者。In addition, the symbol of each component in Table 1 means the following.

(環氧樹脂)
YDCN-700-10(商品名,新日鐵住金化學股份有限公司製造,鄰甲酚酚醛清漆型環氧樹脂,環氧當量:209 g/eq)
EXA-830CRP(商品名,迪愛生(DIC)股份有限公司製造,雙酚F型環氧樹脂,環氧當量:159 g/eq)
YDF-8170C(商品名,新日化環氧製造股份有限公司製造,雙酚F型環氧樹脂,環氧當量:156,常溫下為液體,重量分子量約為310)
(Epoxy resin)
YDCN-700-10 (trade name, manufactured by Nippon Steel & Sumitomo Chemical Co., Ltd., o-cresol novolac epoxy resin, epoxy equivalent: 209 g / eq)
EXA-830CRP (trade name, manufactured by DIC Corporation, bisphenol F-type epoxy resin, epoxy equivalent: 159 g / eq)
YDF-8170C (trade name, manufactured by Nisshinika Epoxy Manufacturing Co., Ltd., bisphenol F epoxy resin, epoxy equivalent: 156, liquid at normal temperature, weight molecular weight is about 310)

(酚樹脂)
PSM-4326(商品名,群榮化學股份有限公司製造,苯酚酚醛清漆樹脂,羥基當量:105 g/eq)
HE-100C-30(商品名,空氣水(AIR WATER)股份有限公司製造,苯基芳烷基型酚樹脂,羥基當量:174 g/eq,軟化點為77℃)
(Phenol resin)
PSM-4326 (trade name, manufactured by Qun Rong Chemical Co., Ltd., phenol novolac resin, hydroxyl equivalent: 105 g / eq)
HE-100C-30 (trade name, manufactured by Air Water Co., Ltd., phenylaralkyl phenol resin, hydroxyl equivalent: 174 g / eq, softening point: 77 ° C)

(無機填料)
R972(商品名,日本艾羅西爾(Aerosil)股份有限公司製造,二氧化矽,平均粒徑:0.016 μm)
SC2050-HLG(商品名,雅都瑪(Admatechs)股份有限公司製造,二氧化矽填料分散液,平均粒徑為0.50 μm)
(Inorganic filler)
R972 (trade name, manufactured by Japan Aerosil Co., Ltd., silicon dioxide, average particle size: 0.016 μm)
SC2050-HLG (trade name, manufactured by Admatechs Co., Ltd., silicon dioxide filler dispersion, average particle size is 0.50 μm)

(高分子量成分)
HTR-860P-3CSP(商品名,長瀨化成股份有限公司製造,丙烯酸橡膠,重量平均分子量:80萬,Tg:12℃)
HTR-860P-3CSP-30DB(商品名,長瀨化成股份有限公司製造,丙烯酸橡膠,重量平均分子量:30萬,Tg:12℃)
(High molecular weight component)
HTR-860P-3CSP (trade name, manufactured by Nagase Chemical Co., Ltd., acrylic rubber, weight average molecular weight: 800,000, Tg: 12 ° C)
HTR-860P-3CSP-30DB (trade name, manufactured by Nagase Chemical Co., Ltd., acrylic rubber, weight average molecular weight: 300,000, Tg: 12 ° C)

(偶合劑)
A-189(商品名,日本邁圖高新材料(Momentive Performance Materials Japan)有限責任公司製造,γ-巰基丙基三甲氧基矽烷)
A-1160(商品名,日本邁圖高新材料有限責任公司製造,γ-脲基丙基三乙氧基矽烷)
(Coupling agent)
A-189 (trade name, manufactured by Momentive Performance Materials Japan), γ-mercaptopropyltrimethoxysilane
A-1160 (trade name, manufactured by Momentive Advanced Materials Co., Ltd., γ-ureidopropyltriethoxysilane)

(硬化促進劑)
2PZ-CN(商品名,四國化成工業股份有限公司製造,1-氰基乙基-2-苯基咪唑)
(Hardening accelerator)
2PZ-CN (trade name, manufactured by Shikoku Chemical Industry Co., Ltd., 1-cyanoethyl-2-phenylimidazole)

[表1]
[Table 1]

<膜的製作>
(膜A的製作)
利用100目的過濾器對合成例A的接著劑清漆進行過濾,並進行真空脫泡。作為基材膜,準備厚度38 μm的已實施脫模處理的聚對苯二甲酸乙二酯(polyethylene terephthalate,PET)膜,將真空脫泡後的接著劑清漆塗佈於PET膜上。以90℃下5分鐘、繼而140℃下5分鐘的兩階段對所塗佈的接著劑清漆進行加熱乾燥。加熱乾燥後,剝去PET膜而獲得處於B階段狀態的膜A。該膜A中,調整接著劑清漆的塗佈量而製作厚度不同的膜。將厚度為10 μm、20 μm、40 μm、100 μm、120 μm及130 μm的膜分別設為膜A-10、膜A-20、膜A-40、膜A-100、膜A-120及膜A-130。
< Making a film >
(Production of Film A)
The adhesive varnish of Synthesis Example A was filtered using a 100-mesh filter, and vacuum-defoamed. As a base film, a polyethylene terephthalate (PET) film having a thickness of 38 μm which had been subjected to a mold release preparation was prepared, and the adhesive varnish after vacuum defoaming was applied to the PET film. The applied adhesive varnish was heat-dried in two stages of 5 minutes at 90 ° C and 5 minutes at 140 ° C. After heating and drying, the PET film was peeled to obtain a film A in a B-stage state. In this film A, the application amount of the adhesive varnish was adjusted to produce films having different thicknesses. Films with a thickness of 10 μm, 20 μm, 40 μm, 100 μm, 120 μm, and 130 μm were set as Film A-10, Film A-20, Film A-40, Film A-100, Film A-120 and Film A-130.

(膜A的剪切黏度的測定)
剪切黏度是使用ARES(流變科學(Rheometric Scientific)公司製造)來進行測定。測定樣品是藉由以下方式進行製作:以70℃下厚度成為160 μm的方式,將黏晶膜(日立化成股份有限公司製造)貼合於膜A,並衝壓為直徑9 mmf。藉由一邊對測定樣品賦予5%的應變一邊以5℃/分鐘的升溫速度升溫而進行測定,將80℃下的值設為80℃下的剪切黏度。膜A的80℃下的剪切黏度為2000 Pa·s。
(Measurement of Shear Viscosity of Film A)
The shear viscosity was measured using ARES (manufactured by Rheometric Scientific). A measurement sample was produced by bonding a viscous film (manufactured by Hitachi Chemical Co., Ltd.) to the film A so that the thickness became 160 μm at 70 ° C., and punching the film to a diameter of 9 mmf. The measurement was performed by increasing the temperature at a temperature increase rate of 5 ° C / min while applying a strain of 5% to the measurement sample, and the value at 80 ° C was set as the shear viscosity at 80 ° C. The shear viscosity of the film A at 80 ° C was 2000 Pa · s.

(膜A的硬化後的儲存彈性係數的測定)
儲存彈性係數是使用動態黏彈性測定裝置(流變股份有限公司製造,商品名:DVE流變光譜(DVE Rheospectra))進行測定。測定樣品是藉由以下方式進行製作:以70℃下厚度成為160 μm的方式,將黏晶膜(日立化成股份有限公司製造)貼合於膜A,並加工為寬4 mm的長條狀,利用示差掃描熱量計(DSC)於反應率成為100%的條件下使其硬化。對所製作的測定樣品,測定升溫速度10℃/min下自室溫至270℃的儲存彈性係數,將150℃下的值設為硬化後的150℃下的儲存彈性係數。膜A的硬化後的150℃下的儲存彈性係數為54 MPa。
(Measurement of storage elastic coefficient of film A after hardening)
The storage elastic coefficient was measured using a dynamic viscoelasticity measuring device (manufactured by Rheology Co., Ltd., trade name: DVE Rheospectra). The measurement sample was prepared by bonding a viscous film (manufactured by Hitachi Chemical Co., Ltd.) to the film A so that the thickness became 160 μm at 70 ° C., and processing it into a strip having a width of 4 mm. A differential scanning calorimeter (DSC) was used to harden it at a reaction rate of 100%. About the produced measurement sample, the storage elasticity coefficient from room temperature to 270 ° C at a heating rate of 10 ° C / min was measured, and the value at 150 ° C was the storage elasticity coefficient at 150 ° C after curing. The storage elastic coefficient at 150 ° C of the cured film A was 54 MPa.

(膜B的製作)
將合成例A的接著劑清漆變更為合成例B的接著劑清漆,除此以外,以與膜A的製作相同的方式獲得膜B。該膜B中,製作厚度為120 μm的膜B-120。膜B的80℃下的剪切黏度為1200 Pa·s,膜B的硬化後的150℃下的儲存彈性係數為31 MPa。
(Fabrication of Film B)
Except that the adhesive varnish of Synthesis Example A was changed to the adhesive varnish of Synthesis Example B, Film B was obtained in the same manner as in the production of Film A. In this film B, a film B-120 having a thickness of 120 μm was prepared. The shear viscosity of the film B at 80 ° C was 1200 Pa · s, and the storage elastic coefficient of the film B at 150 ° C after curing was 31 MPa.

(膜C的製作)
將合成例A的接著劑清漆變更為合成例C的接著劑清漆,除此以外,以與膜A的製作相同的方式獲得膜C。該膜C中,製作厚度為120 μm的膜C-120。膜C的80℃下的剪切黏度為9000 Pa·s,膜C的硬化後的150℃下的儲存彈性係數為160 MPa。
(Fabrication of Film C)
Except that the adhesive varnish of Synthesis Example A was changed to the adhesive varnish of Synthesis Example C, Film C was obtained in the same manner as in the production of Film A. In this film C, a film C-120 having a thickness of 120 μm was produced. The shear viscosity at 80 ° C of Film C was 9000 Pa · s, and the storage elastic coefficient at 150 ° C of Film C after hardening was 160 MPa.

(膜D的製作)
將合成例A的接著劑清漆變更為合成例D的接著劑清漆,除此以外,以與膜A的製作相同的方式獲得膜D。該膜D中,調整接著劑清漆的塗佈量而製作厚度不同的膜。將厚度為10 μm、20 μm及40 μm的膜分別設為膜D-10、膜D-20及膜D-40。膜D的剪切黏度為28000 Pa·s,膜D的硬化後的150℃下的儲存彈性係數為6 MPa。
(Fabrication of Film D)
Except that the adhesive varnish of Synthesis Example A was changed to the adhesive varnish of Synthesis Example D, Film D was obtained in the same manner as in the production of Film A. In this film D, the application amount of the adhesive varnish was adjusted to produce films having different thicknesses. Films having a thickness of 10 μm, 20 μm, and 40 μm were set as Film D-10, Film D-20, and Film D-40, respectively. The shear viscosity of the film D was 28000 Pa · s, and the storage elastic coefficient of the film D at 150 ° C. was 6 MPa.

(膜E的製作)
將合成例A的接著劑清漆變更為合成例E的接著劑清漆,除此以外,以與膜A的製作相同的方式獲得膜E。該膜E中,製作厚度為10 μm的膜E-10。膜E的80℃下的剪切黏度為7400 Pa·s,膜E的硬化後的150℃下的儲存彈性係數為760 MPa。
(Production of Film E)
Except that the adhesive varnish of Synthesis Example A was changed to the adhesive varnish of Synthesis Example E, Film E was obtained in the same manner as in the production of Film A. In this film E, a film E-10 having a thickness of 10 μm was produced. The shear viscosity of the film E at 80 ° C. was 7400 Pa · s, and the storage elastic coefficient of the film E at 150 ° C. was 760 MPa.

(膜F的製作)
將合成例A的接著劑清漆變更為合成例F的接著劑清漆,除此以外,以與膜A的製作相同的方式獲得膜F。該膜F中,製作厚度為20 μm的膜F-20。膜F的80℃下的剪切黏度為14200 Pa·s,膜F的硬化後的150℃下的儲存彈性係數為20 MPa。
(Fabrication of film F)
Except that the adhesive varnish of Synthesis Example A was changed to the adhesive varnish of Synthesis Example F, Film F was obtained in the same manner as in the production of Film A. In this film F, a film F-20 having a thickness of 20 μm was produced. The shear viscosity of the film F at 80 ° C was 14200 Pa · s, and the storage elastic coefficient of the film F at 150 ° C after curing was 20 MPa.

<接著膜的製作>
[實施例1-1~實施例1-8及比較例1-1~比較例1-3]
如表2、表3及表4所示,將膜A~膜F用作第一膜或第二膜。藉由貼合第一膜及第二膜,並加工為圓形而獲得接著膜。於第一膜的與第二膜為相反側的面貼合黏著膜(厚度為110 μm,日立化成股份有限公司製造),製作實施例1-1~實施例1-8及比較例1-1~比較例1-3的切割-黏晶一體型接著膜。
< Production of Adhesive Film >
[Example 1-1 to Example 1-8 and Comparative Example 1-1 to Comparative Example 1-3]
As shown in Table 2, Table 3, and Table 4, films A to F were used as the first film or the second film. The first film and the second film were bonded together and processed into a circle to obtain an adhesive film. An adhesive film (thickness: 110 μm, manufactured by Hitachi Chemical Co., Ltd.) was bonded to the surface of the first film opposite to the second film, and Examples 1-1 to 1-8 and Comparative Example 1-1 were produced. ~ A cut-and-stick crystal integrated type adhesive film of Comparative Examples 1-3.

[表2]
[Table 2]

[表3]
[table 3]

[表4]
[Table 4]

<半導體裝置的製作>
[實施例2-1]
(包括第一半導體晶片的半導體基板的製作)
準備包括接著膜及黏著膜的切割-黏晶一體型接著膜(接著膜:厚度為10 μm、膜E-10,黏著膜:厚度為110 μm,日立化成股份有限公司製造)。於階段溫度70℃下將50 μm厚的半導體晶圓層壓於接著膜,製作切割樣品。
<Production of Semiconductor Device>
[Example 2-1]
(Fabrication of a semiconductor substrate including a first semiconductor wafer)
A cut-bond-integrated adhesive film including an adhesive film and an adhesive film was prepared (adhesive film: 10 μm thick, film E-10, adhesive film: 110 μm thick, manufactured by Hitachi Chemical Co., Ltd.). A 50 μm-thick semiconductor wafer was laminated on the adhesive film at a step temperature of 70 ° C. to prepare a cut sample.

使用全自動切割器(full auto dicer)DFD-6361(迪思科股份有限公司製造),將所獲得的切割樣品切斷。切斷時,以使用兩片刀片的階梯切面方式來進行,並使用切割刀片ZH05-SD3500-N1-xx-DD、及ZH05-SD4000-N1-xx-BB(均為迪思科股份有限公司製造)。切斷條件設為刀片轉數為4000 rpm、切斷速度為50 mm/sec、晶片尺寸為3 mm×3 mm。切斷中,以半導體晶圓殘存25 μm左右的方式進行第一階段的切斷,繼而,以黏著膜中切入20 μm左右的切口的方式進行第二階段的切斷。The obtained cut sample was cut using a full auto dicer DFD-6361 (manufactured by Disco Corporation). The cutting is performed in a stepped manner using two blades, and the cutting blades ZH05-SD3500-N1-xx-DD and ZH05-SD4000-N1-xx-BB (both manufactured by DISCO Corporation) are used. . The cutting conditions were set to 4000 rpm, 50 mm / sec cutting speed, and 3 mm x 3 mm wafer size. During the cutting, the first-stage cutting was performed so that the semiconductor wafer remained approximately 25 μm, and then the second-stage cutting was performed such that an incision of approximately 20 μm was cut into the adhesive film.

其次,使用拾取用夾頭來拾取應拾取的半導體晶片,作為第一半導體晶片(控制器晶片)。圖19是表示拾取用夾頭的上推面的圖。如圖19所示,所使用的拾取用夾頭20例如具有3 mm×3 mm的上推面21,5根上推銷22沿上推面21的對角線上,以規定的間隔排列。拾取時,使用中央的1根銷來進行上推。拾取條件是將上推速度設定為20 mm/s,將上推高度設定為450 μm。如上所述而獲得帶有接著膜的第一半導體晶片(控制器晶片)。Next, a pick-up chuck is used to pick up a semiconductor wafer to be picked up as a first semiconductor wafer (controller wafer). FIG. 19 is a diagram showing a push-up surface of a pickup chuck. As shown in FIG. 19, the pickup chuck 20 used has, for example, a push-up surface 21 of 3 mm × 3 mm, and five push-up pins 22 are arranged at a predetermined interval along a diagonal of the push-up surface 21. When picking up, use the center pin to push up. The pick-up condition is to set the push-up speed to 20 mm / s and the push-up height to 450 μm. The first semiconductor wafer (controller wafer) with an adhesive film was obtained as described above.

其次,使用黏晶機(die bonder)BESTEM-D02(佳能機械(Canon Machinery)公司製造),將帶有接著膜的第一半導體晶片壓接於具有虛擬電路(dummy circuit)的玻璃環氧基板。此時,以第一半導體晶片位於虛擬電路的中央的方式來調整位置。以所述方式而獲得包括第一半導體晶片的半導體基板。Next, using a die bonder BESTEM-D02 (manufactured by Canon Machinery), the first semiconductor wafer with an adhesive film was pressure-bonded to a glass epoxy substrate having a dummy circuit. At this time, the position is adjusted so that the first semiconductor wafer is located in the center of the dummy circuit. In this manner, a semiconductor substrate including a first semiconductor wafer is obtained.

(帶有接著膜的第二半導體晶片的製作)
準備實施例1-1的切割-黏晶一體型接著膜,於階段溫度70℃下將100 μm厚的半導體晶圓(矽晶圓)層壓於第二膜的與第一膜為相反側的面,製作切割樣品。
(Production of a second semiconductor wafer with an adhesive film)
The dicing-bonding integrated film of Example 1-1 was prepared, and a 100 μm-thick semiconductor wafer (silicon wafer) was laminated on the second film on the side opposite to the first film at a stage temperature of 70 ° C. Surface to make cut samples.

使用全自動切割器DFD-6361(迪思科股份有限公司製造),將所獲得的切割樣品切斷。切斷時,以使用兩片刀片的階梯切面方式來進行,並使用切割刀片ZH05-SD2000-N1-xx-FF及ZH05-SD2000-N1-xx-EE(均為迪思科股份有限公司製造)。切斷條件設為刀片轉數為40000 rpm、切斷速度為50 mm/s、晶片尺寸為7 mm×7 mm。切斷中,以半導體晶圓殘存50 μm左右的方式進行第一階段的切斷,繼而,以黏著膜中切入20 μm左右的切口的方式進行第二階段的切斷。Using a fully automatic cutter DFD-6361 (manufactured by Disco Corporation), the obtained cut sample was cut. The cutting is performed in a stepped manner using two blades, and the cutting blades ZH05-SD2000-N1-xx-FF and ZH05-SD2000-N1-xx-EE (both manufactured by DISCO Corporation) are used. The cutting conditions were set to a blade rotation speed of 40,000 rpm, a cutting speed of 50 mm / s, and a wafer size of 7 mm × 7 mm. During the cutting, the first-stage cutting was performed so that the semiconductor wafer remained approximately 50 μm, and then the second-stage cutting was performed such that an incision of approximately 20 μm was cut into the adhesive film.

其次,使用拾取用夾頭,拾取半導體晶片。除使用5根上推銷來上推以外,以與第一半導體晶片的拾取條件相同的方式,獲得帶有接著膜的第二半導體晶片。Next, a semiconductor wafer is picked up using a picking chuck. A second semiconductor wafer with an adhesive film was obtained in the same manner as the pickup conditions of the first semiconductor wafer, except that it was pushed up by using five push-up pins.

(半導體裝置的製作)
將所獲得的帶有接著膜的第二半導體晶片壓接於包括第一半導體晶片的半導體基板。此時,以第二半導體晶片位於第一半導體晶片的中央的方式來調整位置。繼而,藉由加壓烘箱(千代田電子(Chiyoda Electric)股份有限公司製造),將壓接有第二半導體晶片的半導體基板於溫度70℃下保持2小時,進而於溫度150℃下保持30分鐘,使接著膜硬化,藉此而製作實施例2-1的半導體裝置。
(Fabrication of semiconductor devices)
The obtained second semiconductor wafer with an adhesive film was crimped to a semiconductor substrate including the first semiconductor wafer. At this time, the position is adjusted so that the second semiconductor wafer is located at the center of the first semiconductor wafer. Then, the semiconductor substrate on which the second semiconductor wafer was pressure-bonded was held at a temperature of 70 ° C for 2 hours by a pressure oven (manufactured by Chiyoda Electric Co., Ltd.), and further held at 150 ° C for 30 minutes. The adhesive film was hardened, thereby fabricating the semiconductor device of Example 2-1.

(翹曲量的測定)
<半導體基板的翹曲量>
對於實施例2-1的半導體裝置的半導體基板的表面(第二半導體晶片的背面),於室溫下(25℃),藉由雷射位移計(基恩士(KEYENCE)股份有限公司製造,LKG80,級(step)100 μm,測定範圍為縱7 mm、橫7 mm)來進行測定。根據所獲得的各點的位移而算出三維的平均面,並以兩端的點成為零點的方式進行修正。將所獲得的零點與藉由測量而獲得的位移的差最大者設為翹曲量,求出半導體基板的翹曲量。將結果示於表5中。
(Measurement of warpage)
<Warpage amount of semiconductor substrate>
The surface of the semiconductor substrate (the back surface of the second semiconductor wafer) of the semiconductor device of Example 2-1 was manufactured at room temperature (25 ° C) by a laser displacement meter (manufactured by KEYENCE Corporation), LKG80, step (100 μm, measurement range: 7 mm in height, 7 mm in width) were measured. A three-dimensional average plane is calculated from the obtained displacements of the points, and correction is performed so that the points at both ends become zero. The largest difference between the obtained zero point and the displacement obtained by the measurement is taken as the warpage amount, and the warpage amount of the semiconductor substrate is determined. The results are shown in Table 5.

<第二半導體晶片的翹曲量>
對於實施例2-1的半導體裝置的第二半導體晶片的半導體晶圓的表面,於室溫下(25℃),藉由雷射位移計(基恩士股份有限公司製造,LKG80,級(step)100 μm,測定範圍為縱7 mm、橫7 mm)來進行測定。根據所獲得的各點的位移而算出三維的平均面,並以兩端的點成為零點的方式進行修正。將所獲得的零點與藉由測量而獲得的位移的差最大者設為翹曲量,求出第二半導體晶片的翹曲量。將結果示於表5中。
<Warpage amount of the second semiconductor wafer>
The surface of the semiconductor wafer of the second semiconductor wafer of the semiconductor device of Example 2-1 was subjected to a laser displacement meter (manufactured by Keyence Corporation, LKG80, step (step) at room temperature (25 ° C) ) 100 μm, and the measurement range is 7 mm in length and 7 mm in width). A three-dimensional average plane is calculated from the obtained displacements of the points, and correction is performed so that the points at both ends become zero. The largest difference between the obtained zero point and the displacement obtained by the measurement is taken as the warpage amount, and the warpage amount of the second semiconductor wafer is determined. The results are shown in Table 5.

[實施例2-2~實施例2-6]
將實施例1-1的切割-黏晶一體型接著膜變更為實施例1-2~實施例1-6的切割-黏晶一體型接著膜,除此以外,以與實施例2-1相同的方式分別製作實施例2-2~實施例2-6的半導體裝置,並求出半導體基板的翹曲量及第二半導體晶片的翹曲量。將結果表示於表5、表6及表7中。
[Example 2-2 to Example 2-6]
Except that the cut-bond-integrated bonding film of Example 1-1 was changed to the cut-bond-integrated bonding film of Examples 1-2 to 1-6 except that it was the same as that of Example 2-1 The semiconductor devices of Examples 2-2 to 2-6 were fabricated in the same manner, and the amount of warpage of the semiconductor substrate and the amount of warpage of the second semiconductor wafer were determined. The results are shown in Tables 5, 6, and 7.

[比較例2-1]
將實施例1-1的切割-黏晶一體型接著膜變更為比較例1-1的切割-黏晶一體型接著膜,除此以外,以與實施例2-1相同的方式製作比較例2-1的半導體裝置,並求出半導體基板的翹曲量及第二半導體晶片的翹曲量。將結果示於表5及表6中。
[Comparative Example 2-1]
Comparative Example 2 was produced in the same manner as in Example 2-1 except that the cut-bond-integrated adhesive film of Example 1-1 was changed to a cut-adhered-crystal integrated film of Comparative Example 1-1. -1 semiconductor device, and the amount of warpage of the semiconductor substrate and the amount of warpage of the second semiconductor wafer were determined. The results are shown in Tables 5 and 6.

[表5]
[table 5]

[表6]
[TABLE 6]

[表7]
[TABLE 7]

與比較例2-1的半導體裝置相比,實施例2-1~實施例2-6的半導體裝置可抑制半導體基板的翹曲,進而可抑制第二半導體晶片的翹曲。另外,第一膜的剪切黏度越低,則越能夠降低翹曲量。推測其原因在於,第一半導體晶片的埋入性良好,因而可減少該晶片周邊的空隙,可抑制源自空隙的翹曲。Compared with the semiconductor device of Comparative Example 2-1, the semiconductor devices of Examples 2-1 to 2-6 can suppress the warpage of the semiconductor substrate and further suppress the warpage of the second semiconductor wafer. In addition, the lower the shear viscosity of the first film, the more the amount of warpage can be reduced. The reason for this is presumably that the first semiconductor wafer has good embedding properties, so that voids around the wafer can be reduced, and warpage due to voids can be suppressed.

<半導體裝置的製作>
[實施例2-7]
(帶有接著膜的半導體晶片的製作)
準備實施例1-7的切割-黏晶一體型接著膜,於階段溫度70℃下將100 μm厚的半導體晶圓(矽晶圓)層壓於第二膜的與第一膜為相反側的面,製作切割樣品。
<Production of Semiconductor Device>
[Example 2-7]
(Fabrication of semiconductor wafer with adhesive film)
The dicing-bonding integrated film of Example 1-7 was prepared, and a 100 μm-thick semiconductor wafer (silicon wafer) was laminated on the second film on the side opposite to the first film at a step temperature of 70 ° C. Surface to make cut samples.

使用全自動切割器DFD-6361(迪思科股份有限公司製造),將所獲得的切割樣品切斷。切斷時,以使用兩片刀片的階梯切面方式來進行,並使用切割刀片ZH05-SD2000-N1-xx-FF及ZH05-SD2000-N1-xx-EE(均為迪思科股份有限公司製造)。切斷條件設為刀片轉數為40000 rpm、切斷速度為50 mm/s、晶片尺寸為7 mm×7 mm。切斷中,以半導體晶圓殘存50 μm左右的方式進行第一階段的切斷,繼而,以黏著膜中切入20 μm左右的切口的方式進行第二階段的切斷。Using a fully automatic cutter DFD-6361 (manufactured by Disco Corporation), the obtained cut sample was cut. The cutting is performed in a stepped manner using two blades, and the cutting blades ZH05-SD2000-N1-xx-FF and ZH05-SD2000-N1-xx-EE (both manufactured by DISCO Corporation) are used. The cutting conditions were set to a blade rotation speed of 40,000 rpm, a cutting speed of 50 mm / s, and a wafer size of 7 mm × 7 mm. During the cutting, the first-stage cutting was performed so that the semiconductor wafer remained approximately 50 μm, and then the second-stage cutting was performed such that an incision of approximately 20 μm was cut into the adhesive film.

其次,使用拾取用夾頭,拾取半導體晶片。除使用5根銷來上推以外,以與第一半導體晶片的拾取條件相同的方式,獲得帶有接著膜的半導體晶片。Next, a semiconductor wafer is picked up using a picking chuck. A semiconductor wafer with an adhesive film was obtained in the same manner as the pickup conditions of the first semiconductor wafer, except that the five pins were used to push up.

將所獲得的帶有接著膜的半導體晶片壓接於具有虛擬電路的玻璃環氧基板。此時,以半導體晶片位於虛擬電路的中央的方式來調整位置。繼而,藉由加壓烘箱(千代田電子股份有限公司製造),將壓接有半導體晶片的玻璃環氧基板於溫度70℃下保持2小時,進而於溫度150℃下保持30分鐘,使接著膜硬化,藉此而製作實施例2-7的半導體裝置。The obtained semiconductor wafer with an adhesive film was pressure-bonded to a glass epoxy substrate having a dummy circuit. At this time, the position is adjusted so that the semiconductor wafer is located in the center of the dummy circuit. Subsequently, the glass epoxy substrate to which the semiconductor wafer was pressure-bonded was held at 70 ° C for 2 hours in a pressure oven (manufactured by Chiyoda Electronics Co., Ltd.), and further held at 150 ° C for 30 minutes to harden the adhesive film. Thus, the semiconductor device of Example 2-7 was manufactured.

(翹曲量的測定)
藉由與所述半導體基板的翹曲量相同的方法,求出半導體基板的翹曲量。將結果示於表8中。
(Measurement of warpage)
The warpage amount of the semiconductor substrate was determined by the same method as the warpage amount of the semiconductor substrate. The results are shown in Table 8.

[實施例2-8及比較例2-2、比較例2-3]
將實施例1-7的切割-黏晶一體型接著膜變更為實施例1-8及比較例1-2、比較例1-3的切割-黏晶一體型接著膜,除此以外,以與實施例2-7相同的方式分別製作實施例2-8及比較例2-2、比較例2-3的半導體裝置,並求出半導體基板的翹曲量。將結果示於表8中。
[Example 2-8 and Comparative Example 2-2, Comparative Example 2-3]
The cut-and-sticky crystal-integrated bonding film of Example 1-7 was changed to the cut-and-sticky crystal-integrated bonding film of Example 1-8 and Comparative Examples 1-2 and Comparative Examples 1-3. In the same manner as in Example 2-7, the semiconductor devices of Example 2-8 and Comparative Example 2-2 and Comparative Example 2-3 were fabricated respectively, and the amount of warpage of the semiconductor substrate was determined. The results are shown in Table 8.

[表8]
[TABLE 8]

與比較例2-2及比較例2-3的半導體裝置相比,實施例2-7及實施例2-8的半導體裝置可抑制半導體基板的翹曲。Compared with the semiconductor devices of Comparative Examples 2-2 and 2-3, the semiconductor devices of Examples 2-7 and 2-8 can suppress the warpage of the semiconductor substrate.

根據以上而確認到,本發明的半導體裝置的製造方法能夠抑制半導體基板的翹曲。From the above, it was confirmed that the method for manufacturing a semiconductor device of the present invention can suppress the warpage of a semiconductor substrate.

1、4a、4b‧‧‧基材膜 1, 4a, 4b‧‧‧ substrate film

2‧‧‧黏著膜 2‧‧‧ adhesive film

3a‧‧‧第一膜 3a‧‧‧first film

3b‧‧‧第二膜 3b‧‧‧Second film

5‧‧‧吸引夾頭 5‧‧‧ attract chuck

6、10‧‧‧半導體基板 6, 10‧‧‧ semiconductor substrate

11‧‧‧導線 11‧‧‧ Lead

11a‧‧‧第一導線 11a‧‧‧First Lead

11b‧‧‧第二導線 11b‧‧‧Second Lead

12‧‧‧密封材 12‧‧‧sealing material

13‧‧‧端子 13‧‧‧Terminal

14‧‧‧電路圖案 14‧‧‧Circuit Pattern

20‧‧‧拾取用夾頭 20‧‧‧ Pickup Chuck

21‧‧‧上推面 21‧‧‧ push up

22‧‧‧上推銷 22‧‧‧ Upsell

100、110、120‧‧‧膜 100, 110, 120‧‧‧ film

130‧‧‧接著膜 130‧‧‧ Adhesive film

130c、130c1、130c2、130c3、130c4‧‧‧硬化物130c, 130c 1 , 130c 2 , 130c 3 , 130c 4 ‧‧‧ hardened

140‧‧‧切割-黏晶一體型接著膜 140‧‧‧cut-sticky crystal integrated film

200‧‧‧接著片 200‧‧‧ Follow-up

300‧‧‧帶有接著膜的半導體晶圓 300‧‧‧ semiconductor wafer with adhesive film

400、410、500‧‧‧半導體裝置 400, 410, 500‧‧‧ semiconductor devices

A‧‧‧半導體晶圓 A‧‧‧Semiconductor wafer

a‧‧‧半導體晶片 a‧‧‧Semiconductor wafer

a1、a3‧‧‧第一半導體晶片a 1 , a 3 ‧‧‧ the first semiconductor wafer

a2、a4‧‧‧第二半導體晶片a 2 , a 4 ‧‧‧Second semiconductor wafer

B‧‧‧刀片 B‧‧‧ Blade

UV‧‧‧紫外線 UV‧‧‧UV

圖1是包括基材膜及黏著膜的膜的示意圖。FIG. 1 is a schematic diagram of a film including a base film and an adhesive film.

圖2(a)是包括基材膜及接著膜的膜的示意圖。圖2(b)是包括基材膜及接著膜的膜的示意圖。圖2(c)是接著膜的示意圖。 FIG. 2 (a) is a schematic diagram of a film including a base film and an adhesive film. FIG. 2 (b) is a schematic diagram of a film including a base film and an adhesive film. Fig. 2 (c) is a schematic diagram of a film.

圖3是接著膜的示意圖。 FIG. 3 is a schematic view of a film.

圖4是帶有接著膜的半導體晶圓的示意圖。 FIG. 4 is a schematic diagram of a semiconductor wafer with an adhesive film.

圖5是表示切割步驟的示意圖。 FIG. 5 is a schematic diagram showing a cutting step.

圖6是表示紫外線照射步驟的示意圖。 FIG. 6 is a schematic diagram showing an ultraviolet irradiation step.

圖7是表示拾取步驟的示意圖。 FIG. 7 is a schematic diagram showing a pickup step.

圖8是表示壓接步驟的示意圖。 FIG. 8 is a schematic diagram showing a crimping step.

圖9是表示半導體裝置的一實施形態的示意圖。 FIG. 9 is a schematic diagram showing an embodiment of a semiconductor device.

圖10是表示半導體裝置的一實施形態的示意圖。 FIG. 10 is a schematic diagram showing an embodiment of a semiconductor device.

圖11是表示半導體裝置的製造步驟的示意圖。 FIG. 11 is a schematic diagram showing a manufacturing process of a semiconductor device.

圖12是表示半導體裝置的製造步驟的示意圖。 FIG. 12 is a schematic diagram showing a manufacturing process of a semiconductor device.

圖13是表示半導體裝置的一實施形態的示意圖。 FIG. 13 is a schematic diagram showing an embodiment of a semiconductor device.

圖14是表示半導體裝置的製造步驟的示意圖。 FIG. 14 is a schematic diagram showing a manufacturing process of a semiconductor device.

圖15是表示半導體裝置的製造步驟的示意圖。 FIG. 15 is a schematic diagram showing a manufacturing process of a semiconductor device.

圖16是表示半導體裝置的製造步驟的示意圖。 FIG. 16 is a schematic diagram showing a manufacturing process of a semiconductor device.

圖17是表示半導體裝置的製造步驟的示意圖。 FIG. 17 is a schematic diagram showing a manufacturing process of a semiconductor device.

圖18是表示半導體裝置的製造步驟的示意圖。 FIG. 18 is a schematic diagram showing a manufacturing process of a semiconductor device.

圖19是表示拾取用夾頭(collet)的上推面的圖。 FIG. 19 is a diagram showing a push-up surface of a collet for picking up.

Claims (10)

一種半導體裝置的製造方法,其包括: 準備帶有接著膜的半導體晶圓的步驟,所述帶有接著膜的半導體晶圓於黏著膜上依序具有接著膜及半導體晶圓; 切割步驟,切割所述帶有接著膜的半導體晶圓,而獲得帶有接著膜的半導體晶片;以及 壓接步驟,將所述帶有接著膜的半導體晶片壓接於半導體基板;且 自所述黏著膜起,所述接著膜依序包含第一膜及80℃下的剪切黏度與所述第一膜不同的第二膜, 所述第二膜的80℃下的剪切黏度為500 Pa·s以上。A method for manufacturing a semiconductor device includes: A step of preparing a semiconductor wafer with an adhesive film, the semiconductor wafer with an adhesive film sequentially having an adhesive film and a semiconductor wafer on an adhesive film; A dicing step of dicing the semiconductor wafer with an adhesive film to obtain a semiconductor wafer with an adhesive film; and A crimping step of crimping the semiconductor wafer with an adhesive film to a semiconductor substrate; and Starting from the adhesive film, the adhesive film sequentially includes a first film and a second film having a shear viscosity different from the first film at 80 ° C. The shear viscosity at 80 ° C. of the second film is 500 Pa · s or more. 如申請專利範圍第1項所述的半導體裝置的製造方法,其中所述第二膜的厚度為3 μm~150 μm。The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the thickness of the second film is 3 μm to 150 μm. 如申請專利範圍第1項或第2項所述的半導體裝置的製造方法,其中所述第二膜的硬化後的150℃下的儲存彈性係數為1000 MPa以下。The method for manufacturing a semiconductor device according to item 1 or item 2 of the scope of patent application, wherein the storage film has a storage elastic coefficient at 150 ° C. of 1000 MPa or less after the second film is cured. 如申請專利範圍第1項至第3項中任一項所述的半導體裝置的製造方法,其中所述半導體裝置為藉由將第一半導體晶片經由第一導線而以打線接合的方式連接於半導體基板上,並且於所述第一半導體晶片上,經由所述接著膜而壓接第二半導體晶片,從而將所述第一導線的至少一部分埋入所述接著膜中而成的導線埋入型的半導體裝置。The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is connected to the semiconductor by wire bonding by connecting a first semiconductor wafer through a first wire. A lead-embedded type in which at least a part of the first lead is buried in the bonding film on the substrate and on the first semiconductor wafer by crimping a second semiconductor wafer through the bonding film. Semiconductor device. 如申請專利範圍第1項至第3項中任一項所述的半導體裝置的製造方法,其中所述半導體裝置為藉由將第一半導體晶片經由第一導線而以打線接合的方式連接於半導體基板上,並且於所述第一半導體晶片上,經由所述接著膜而壓接第二半導體晶片,從而將所述第一導線及所述第一半導體晶片埋入所述接著膜中而成的晶片埋入型的半導體裝置。The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is connected to the semiconductor by wire bonding by connecting a first semiconductor wafer through a first wire. A substrate formed on the first semiconductor wafer and crimping a second semiconductor wafer through the adhesive film to embed the first lead and the first semiconductor wafer in the adhesive film; Wafer-embedded semiconductor device. 一種接著膜,其包括: 第一膜;以及 第二膜,所述第二膜積層於所述第一膜上,且80℃下的剪切黏度與所述第一膜不同, 所述第二膜的80℃下的剪切黏度為500 Pa·s以上。An adhesive film comprising: First film; and A second film, the second film being laminated on the first film, and having a shear viscosity at 80 ° C. different from that of the first film, The shear viscosity at 80 ° C. of the second film is 500 Pa · s or more. 如申請專利範圍第6項所述的接著膜,其中所述第二膜的厚度為3 μm~150 μm。The adhesive film according to item 6 of the scope of patent application, wherein the thickness of the second film is 3 μm to 150 μm. 如申請專利範圍第6項或第7項所述的接著膜,其中所述第二膜的硬化後的150℃下的儲存彈性係數為1000 MPa以下。The adhesive film according to item 6 or item 7 of the scope of patent application, wherein the storage elastic coefficient of the second film after curing at 150 ° C. is 1,000 MPa or less. 如申請專利範圍第6項至第8項中任一項所述的接著膜,其於第一半導體晶片經由第一導線而以打線接合的方式連接於半導體基板上,並且於所述第一半導體晶片上壓接第二半導體晶片而成的半導體裝置中,用於壓接所述第二半導體晶片並且埋入所述第一導線的至少一部分。The adhesive film according to any one of claims 6 to 8 of the scope of patent application, which is connected to a semiconductor substrate by wire bonding on a first semiconductor wafer via a first wire, and is connected to the first semiconductor In a semiconductor device formed by crimping a second semiconductor wafer on a wafer, the second semiconductor wafer is crimped and at least a portion of the first wire is buried. 如申請專利範圍第6項至第8項中任一項所述的接著膜,其於第一半導體晶片經由第一導線而以打線接合的方式連接於半導體基板上,並且於所述第一半導體晶片上壓接第二半導體晶片而成的半導體裝置中,用於壓接所述第二半導體晶片並且埋入所述第一導線及所述第一半導體晶片。The adhesive film according to any one of claims 6 to 8 of the scope of patent application, which is connected to a semiconductor substrate by wire bonding on a first semiconductor wafer via a first wire, and is connected to the first semiconductor In a semiconductor device formed by crimping a second semiconductor wafer on a wafer, the second semiconductor wafer is crimped and the first wire and the first semiconductor wafer are embedded.
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JP2019134020A (en) 2019-08-08
CN111656500A (en) 2020-09-11

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