TW201027555A - Semiconductor storage device and storage controlling method - Google Patents
Semiconductor storage device and storage controlling method Download PDFInfo
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- TW201027555A TW201027555A TW098130427A TW98130427A TW201027555A TW 201027555 A TW201027555 A TW 201027555A TW 098130427 A TW098130427 A TW 098130427A TW 98130427 A TW98130427 A TW 98130427A TW 201027555 A TW201027555 A TW 201027555A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims description 23
- 238000006243 chemical reaction Methods 0.000 claims abstract description 57
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- 238000013500 data storage Methods 0.000 claims 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
- G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
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- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
Abstract
Description
201027555 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體儲存裝置之儲存控制。 本申請案係基於且主張於2008年12月22曰申請之先前曰 本專利申請案第2008-325632號之優先權的權利，該案之 全部内容以引用的方式併入本文中。 【先前技術】 在併有NAND快閃ROM或其類似物之半導體儲存裝置 中，先前儲存之資料需要加以安全地保護，使得其在電源 供應器在資料寫入操作期間突然被切斷且導致寫入失敗時 將不會惡化。根據不同電壓將多個位元儲存於其中之多位 準單元（MLC)類型之NAND快閃ROM具有藉由執行若干次 寫入以一次一個位元之方式將資訊寫入至記憶體單元中之 模式。在此寫入模式中存在如下問題：若在正將資訊添加 至其中具有資訊之記憶體單元中時電源供應器被切斷，則 先前所儲存之資訊可丟失。 為解決此問題，JP-A 2006-221743(KOKAI)提出一種管 理共用記憶體單元之區塊中之頁的關係及控制寫入操作以 單次將資料寫入至每一區塊之記憶體單元中之技術。以此 方式，可臨時儲存外部供應之資料，且在特定定時將臨時 儲存之資料複製至另一區塊。可藉此避免資料惡化。 更具體言之，MLC NAND快閃ROM臨時用作SLC(雙 態）NAND快閃ROM，使得保護資料（針對其完成寫入操作） 使其免於惡化。接著，藉由規則寫入方法將臨時儲存之資 143117.doc 201027555 料複製至另一區塊。此實現MLC NAND快閃jR〇M之安全資 料寫入操作。藉由此方法，即使在正將臨時儲存之資料複 製至另一區塊時電源供應器突然被切斷，所儲存之最初資 料亦將不會惡化且因此可易於尋回資料。 然而’根據JP-A 2006·221743(ΚΟΚΑΙ)之技術，在一抹 除之後可寫入區塊中之資料的量減少至「1/記憶體單元中 之可寫入位元的數目」。此意謂，為將特定量之資料寫入201027555 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to storage control of a semiconductor storage device. The present application is based on and claims the benefit of priority to the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit. [Prior Art] In a semiconductor storage device having a NAND flash ROM or the like, previously stored data needs to be securely protected so that it is suddenly cut off during the data write operation of the power supply and causes writing It will not deteriorate when it fails. A multi-level cell (MLC) type NAND flash ROM in which a plurality of bits are stored according to different voltages has write information into a memory cell by performing a number of writes one bit at a time. mode. In this write mode, there is a problem that if the power supply is cut off while information is being added to the memory unit having information therein, the previously stored information can be lost. In order to solve this problem, JP-A 2006-221743 (KOKAI) proposes a relationship for managing pages in a block of a shared memory unit and controlling a write operation to write data to a memory unit of each block in a single time. The technology in the middle. In this way, externally supplied materials can be temporarily stored, and temporarily stored data can be copied to another block at a specific timing. This can be used to avoid data deterioration. More specifically, the MLC NAND flash ROM is temporarily used as an SLC (Double State) NAND flash ROM, so that the data is protected (for which write operations are completed) from deterioration. Next, the temporarily stored capital 143117.doc 201027555 is copied to another block by the rule writing method. This implements the secure data write operation of the MLC NAND flash jR〇M. By this means, even if the power supply is suddenly cut off while the temporarily stored data is being copied to another block, the original stored information will not deteriorate and thus the data can be easily retrieved. However, according to the technique of JP-A 2006-221743 (ΚΟΚΑΙ), the amount of data that can be written into a block after erasing is reduced to "the number of writable bits in the memory unit". This means that a specific amount of data is written.
❹ 至MLC NAND快閃ROM中，必須抹除待寫入之資料的量乘 以記憶體單元中之可寫入位元的數目。此外，根據此技 術，始終將臨時儲存之資料複製至另一區塊。此意謂，在 、’-=束時而要抹除資料之量乘以「（記憶體單元中之可寫 入位元之數目）+1」。 舉例而a，當在此系統中採用兩個位元可寫入每個記憶 體單元之MLCNAND快閃R〇M時，需要抹除係待寫入之資 料的量之2 + 1=3倍的資料，其為高度不必要之量。此外， 考慮到重寫入之數目有限’應最小化資料抹除之數目。 【發明内容】 根據本發明之-態樣’-種半導體儲存裝置包括一第一 單元，其具有係資料寫入區之複數個第一區塊；一指 :單7〇 ’其發出一將資料寫入至該等第一區塊中之寫入指 令；-轉換單元，其參考—轉換表將輸入資料之一外部位 址轉換為該第-區塊中之—記憶體位置，在該轉換表中， 該資料之外部位址虚該|黎 止/、及專第一區塊中之該資料之該等記憶 體位置相關聯；及-判斷單元，其基於該輸入資料之該等 143117.doc 201027555 :己隐體位置判斷該等第一區塊中之任一者是否儲存有效資 料，該有效資料為與該外部位址相關聯之該資料，其中該 才a *7單元在該等第—區塊中之任一者未儲存該有效資料時 發出將該資料寫入至未儲存該有效資料之該第一區塊中的 該寫入指令。 根據本發明之另—態樣，—種半導體儲存裝置包括—第 儲存單元，其具有係資料寫入區之複數個第一區塊；一 指令單元，其發出—將資料寫入至該等第一區塊中之寫入 指令；一轉換單元’其參考一轉換表將輸入資料之一外部G 位址轉換為該第一區塊中之一記憶體位置，在該轉換表 中，忒 > 料之外部位址與該等區塊中之該資料之記憶體位 置相關聯；—管理單元，其管理該等第-區塊中之該資料 ^ 6己憶體狀態；及一判斷單元，其基於該輸入資料之該 等记憶體位置及該資料之該記憶體狀態判斷該等第一區塊 疋否包括資料寫入不會造成該有效資料之丟失之任何第一 區塊，該有效資料為與該外部位址相關聯之資料，其中該❹ 才a 7單元在該等第一區塊包括該資料寫入不會造成有效資 料之丟失之該第一區塊時發出將該資料寫入至該資料寫入 不會造成該有效資料之丟失之該第一區塊中的該寫入指 令。 根據本發明之又一態樣，（提供）一種實施於一半導體儲 存裝置中之儲存控制方法，該方法包含：發出一將資料寫 入至為一儲存單元中之資料寫入區之區塊中的寫入指令； 參考一轉換表將輸入資料之一外部位址轉換為該區塊中之 143117.doc -6 - 201027555 一記憶體位置，在該轉換表中，該資料之外部位址與該等 區塊中之該資料的該等記憶體位置相關聯；及基於該輸入 資料之S亥等記愧體位置判斷該等區塊中之任一者是否儲存 有效資料，該有效資料為與該外部位址相關聯的該資料， 其中該發出在該等區塊中之任一者未储存該有效資料時發 出將該資料寫入至未儲存該有效資料之該區塊中的該寫入 指令。 ^ 【實施方式】 以下參看隨附圖式詳細解釋根據本發明之半導體儲存裝 置及控制半導體儲存裝置之方法的例示性實例。 (第一實施例） 如圖1中所說明，根據第一實施例之半導體儲存裝置i將 資料儲存於其中，且包括一主機介面2、一動態隨機存取 記憶體（DRAM)3、一 NAND快閃唯讀記憶體（R〇M)4及一控 制器5。主機介面2執行與諸如個人電腦之主機裝置6之資 ❹ 料通信以傳輸及接收資料。 DRAM 3為將在操作期間由主機裝置6供應之所寫入之資 料及自NAND快閃ROM 4讀取之寫入/讀出資料7臨時儲存 於其中之6己憶體。DRAM 3亦將在操作期間自NAND快閃 ROM 4讀取之位址轉換表8儲存於其中。稍後在解釋 快閃ROM 4時將詳細論述位址轉換表8。 NAND快閃⑽心核⑽負型且將由主機裝置綠應且臨 時儲存於 DRAM3*U_MmdNANd^r〇m4 包括位址轉換表8、第一儲存單元9、第二儲存單元ι〇及區 143117.doc 201027555 塊管理清單11。 參看圖2解釋普通MLC NAND快閃ROM之結構及駐留於 該結構中之問題。在圖2中假設NAND快閃ROM在每個記 憶體單元中儲存兩個位元。 NAND快閃ROM經劃分為多個區塊，該等區塊為用於抹 除操作之單位區域。每一區塊進一步經劃分為多個頁，該 等頁為用於寫入/讀取操作之單位區域，且每一頁按次序 與記憶體單元之位元中的一者相關聯。在圖2之實例中， 區塊包括8個頁，頁〇至頁7。資料寫入至頁中之次序定義 為頁0、1、2、...7。在此圖式中，資料現儲存達頁4。 大體而言，對應於記憶體單元中之第一經寫入位元的頁 被稱為下部頁，且對應於同一記憶體單元中之第二經寫入 位元的頁被稱為上部頁。由此，在共用nand快閃之 同一記憶體單元之下部頁及上部頁中，除非至下部頁之寫 入完成，否則不可將資料寫入至上部頁中。在此實例中， 頁〇與1、頁2與3、頁4與5及頁6與7中之每一對共用一記 體單元。 α 在具有此結構之NAND快閃R0M中，若在至上部頁之資 :寫入期間斷開電源供應器’則已寫入至同一記憶體單元 中欠之下部頁中的資料亦惡化。另―方面，^在至下部頁之 貝料寫入期間斷開電源供應器， w呙入不冋皁兀（其下部 頁及上邛頁）中之資料不會惡化。 143117.doc 201027555 之Γ例中，右在至頁5(上部頁）之資料寫入期間斷開電源供 應器1]儲存於同—記憶體單元之頁4(下部頁）中之資料同 時惡化。 ，若：憶體單元之下部頁及上部頁包括更多頁，則對於記 憶體單元之所有頁類似地發生此問題。 相同問題可在根據本實施例之NAND快閃4中出 現:位址轉換表8、第一儲存單元9、第二儲存單元10及區 φ 土鬼官理清單11基本上具有相同結構。本實施例旨在防止此 問題出現。 位址轉換表8指示NAND快閃R〇M 4之區塊的儲存由主機 裝置6供應之資料的頁位置（位址）。位址轉換表8因此將 NAND快閃R0M 4之針對每一頁儲存由主機裝置6供應之資 料的位置（位址）儲存於其中。此處，其位址儲存於位址轉 換表8中之頁中之資料或換言之由位址轉換表8所指定的資 料被稱為有效資料。另一方面，其位址未儲存於位址轉換 φ 表8中之頁中之資料或換言之經儲存但未由位址轉換表8所 指定的資料被稱為無效資料。 當半導體儲存裝置1未操作時’位址轉換表8僅存在於 NAND快閃ROM 4中。然而，當主機裝置6向半導體儲存裝 置1發出資料寫入/讀取指令時，自NAND快閃ROM 4讀取 位址轉換表8且將其臨時儲存於DRAM 3中。接著，稱後描 述之控制器5之位址轉換單元14在臨時儲存於DRAM 3中的 位址轉換表8上執行位址更新過程。用於NAND快閃ROM 4 中之位址轉換表8之位址更新過程係在諸如在半導體儲存 143117.doc 201027555 裝置1停止其操作時的任何給定定時執行。 第-儲存單元9及第二儲存單元1G各自包括多個區塊， 〃先&所提及。在每__區塊中，寫人由主機裝置6供應且 岛時儲存於DRAM 3中之資料。當實際寫入該資料時，稍 後描述之控制器5之寫入/讀取指令單元13自第一儲存單元 9及第二儲存單元10的該等區塊選擇一區塊。在圖1中，第 —餘存單元9包括四個區塊A至D，且第二儲存單元1〇包括 兩個區塊E及F。 首先將由主機裝置6供應且臨時儲存於DRAM 3中之所有 賣料寫入第一儲存單元9之區塊（第一區塊）中。另一方面， 當在第一儲存單元9中不存在可寫入區塊時，僅將由稍後 描述之控制器5之移動單元16指定的資料自第一儲存單元9 之區塊移動且寫入第二儲存單元1〇之區塊（第二區塊）中。 應注意，第一儲存單元9之區塊及第二儲存單元1〇之彼 等區塊並不固定，而是可由稍後描述之控制器5之區塊管 理單元17動態地改變。 區塊管理清單11管理第一儲存單元9之區塊及第二儲存 單元10之區塊’如圖3中所說明。在此圖式中，四個區塊a 至D屬於第一儲存單元9，且兩個區塊e及F屬於第二儲存 單元10。 區塊管理清單11僅存在於NAND快閃ROM 4中。然而， 該結構可經組態使得當主機裝置6向半導體儲存裝置1發出 資料寫入/讀取指令時自NAND快閃ROM 4讀取區塊管理清 單11且將其臨時儲存於DRAM 3中。在此結構中，臨時儲 143117.doc • 10- 201027555 存於DRAM 3中之區塊管理清單11應由控制器5之稍後描述 的區塊管理單元17更新，而NAND快閃R0M 4中之區塊管 理清單11應在諸如關閉半導體儲存裝置1時的任何給定定 時更新。 控制器5控制半導體儲存裝置1之操作。控制器5包括 CPU 12且根據由CPU 12執行之指令控制半導體儲存裝 置1。CPU 12包括寫入/讀取指令單元13、位址轉換單元 ❹ 14、判斷單元丨5、移動單元16及區塊管理單元17。實際 上，由CPU 12執行之程式具有包括寫入/讀取指令單元 13、位址轉換單元14、判斷單元15、移動單元^及區塊管 理單元17之模組結構。當CPU 12自R〇M或其類似物（未圖 示）讀取程式且執行該程式時，寫入/讀取指令單元13、位 址轉換單元14、判斷單元15、移動單元16及區塊管理單元 17在CPU 12上產生。 回應於來自主機裳置6之請求，寫入/讀取指令單元13發 ❹ 出將DRAM 3之資料寫入至NAND快閃R〇M 4(由判斷單元 15指定之第一儲存單元9之區塊）的資料寫入指令或將來自 NAND快閃ROM 4(第一儲存單元9或第二儲存單元⑺之區 塊）之資料讀取至DRAM 3的資料讀取指令。 位址轉換單S Μ將由主機裝置6供應之f料之外部位址 轉換為NAND快閃ROM 4的區棟之實際儲存資料之頁。更 具體言之’當由主機裝置6供應之資料儲存於卿〇快閃 ROM 4中時’位址轉換單元14將資料之外部位址與區塊之 儲存資料的頁相關聯，且將其儲存於位址轉換表8中。當 143117.doc -11· 201027555 自主機裝置6接收到讀取請求時，位址轉換單元14將外部 位址轉換為區塊之相應頁。換言之，針對個別頁執行位址 轉換。 如圖4中所說明，位址轉換單元14參考位址轉換表8將由 主機裝置6供應之資料之外部位址轉換為NANJ>^閃r〇m 4 中的區塊之頁。詳言之，在由位址轉換單元14進行之轉換 過程中，由主機裝置6供應之外部位址之一些最高位元經 轉換為NAND快閃ROM 4的區塊之頁，且剩餘較低位元轉 換為頁内之資料位置。 根據圖4，自外部位址供應之位址具有48個位元。外部 位址之較高37個位元用於轉換為區塊之頁，而外部位址之 較低11個位元用於轉換為頁的資料位置。位元之數目根據 頁之容量而變化。儲存於位址轉換表8中之nand快閃 ROM 4中之區塊的頁位置上之資料為與個別外部位址相關 聯儲存之有效資料，且因此不允許此資料惡化。 在併有NAND快閃ROM之半導體儲存裝置中，在寫入至至 To the MLC NAND flash ROM, the amount of data to be written must be erased by the number of writable bits in the memory unit. In addition, according to this technique, temporarily stored data is always copied to another block. This means that the amount of data to be erased at the time of the '-= bundle is multiplied by "(the number of writable bits in the memory unit) +1". For example, a, when two bits are used in this system to write the MLCNAND flash R〇M of each memory unit, it is necessary to erase 2 + 1=3 times the amount of data to be written. Information, which is a highly unnecessary quantity. In addition, considering the limited number of rewrites, the number of data erases should be minimized. SUMMARY OF THE INVENTION According to the present invention, a semiconductor storage device includes a first unit having a plurality of first blocks that are data writing areas; a finger: a single 7〇' which sends a data a write command written to the first block; a conversion unit whose reference-conversion table converts an external address of the input data into a memory location in the first block, in the conversion table The location outside the data is associated with the location of the memory of the data in the first block; and the judging unit is based on the input data 143117.doc 201027555: The location of the hidden body determines whether any of the first blocks stores valid data, the valid data is the data associated with the external address, wherein the a*7 unit is in the first- When the valid data is not stored in any of the blocks, the write command is written to the first block in which the valid data is not stored. According to another aspect of the present invention, a semiconductor storage device includes a storage unit having a plurality of first blocks that are data writing areas, and an instruction unit that issues a data to the first a write instruction in a block; a conversion unit's reference to a conversion table converts an external G address of one of the input data into a memory location in the first block, in the conversion table, 忒> The location outside the material is associated with the memory location of the data in the blocks; a management unit that manages the data in the first-block; and a determination unit Determining, based on the location of the memory of the input data and the state of the memory of the data, whether the first block includes any first block that does not cause loss of the valid data, the valid data And the data associated with the external address, wherein the unit a 7 sends the data to the first block when the first block includes the first block that does not cause loss of valid data. Until the data is written, it will not cause the The loss of the first block of data in the write command. According to still another aspect of the present invention, a storage control method implemented in a semiconductor storage device includes: writing a data to a block of a data write area in a storage unit Write instruction; refer to a conversion table to convert an external address of the input data into a memory location 143117.doc -6 - 201027555 in the block, in the conversion table, the location outside the data and the Corresponding to the memory locations of the data in the blocks; and determining whether any of the blocks stores valid data based on the location of the input data, such as Shai, etc., the valid data is The data associated with the external address, wherein the issuing the write command to write the data to the block in which the valid data is not stored when the valid data is not stored in any of the blocks . [Embodiment] Hereinafter, an illustrative example of a semiconductor storage device and a method of controlling a semiconductor storage device according to the present invention will be explained in detail with reference to the accompanying drawings. (First Embodiment) As illustrated in FIG. 1, a semiconductor storage device i according to a first embodiment stores therein data, and includes a host interface 2, a dynamic random access memory (DRAM) 3, and a NAND. Flash read only memory (R〇M) 4 and a controller 5. The host interface 2 performs communication with a host device such as a personal computer 6 to transmit and receive data. The DRAM 3 is a 6-remembered body in which the data written by the host device 6 and the write/read data 7 read from the NAND flash ROM 4 are temporarily stored. The DRAM 3 also stores therein the address conversion table 8 read from the NAND flash ROM 4 during operation. The address conversion table 8 will be discussed in detail later when explaining the flash ROM 4. NAND flash (10) core (10) negative type and will be temporarily stored by the host device in DRAM3*U_MmdNANd^r〇m4 including address conversion table 8, first storage unit 9, second storage unit ι and area 143117.doc 201027555 Block Management Listing 11. The structure of a conventional MLC NAND flash ROM and the problems residing in the structure will be explained with reference to FIG. It is assumed in Fig. 2 that the NAND flash ROM stores two bits in each of the memory cells. The NAND flash ROM is divided into a plurality of blocks, which are unit areas for erase operations. Each block is further divided into a plurality of pages, which are unit areas for write/read operations, and each page is associated with one of the bits of the memory unit in order. In the example of Figure 2, the block includes 8 pages, page 〇 to page 7. The order in which data is written to the page is defined as pages 0, 1, 2, ... 7. In this figure, the data is now stored on page 4. In general, a page corresponding to a first written bit in a memory cell is referred to as a lower page, and a page corresponding to a second written bit in the same memory cell is referred to as an upper page. Thus, in the lower page and the upper page of the same memory cell sharing the nand flash, the data cannot be written to the upper page unless the writing to the lower page is completed. In this example, page 〇 shares a record unit with each of the pages 1, 2 and 3, pages 4 and 5, and pages 6 and 7. α In the NAND flash ROM having this structure, if the power supply is turned off during the write to the upper page: the data written to the lower page of the same memory unit is also deteriorated. On the other hand, if the power supply is disconnected during the writing of the material to the lower page, the data in the saponin (the lower page and the upper page) will not deteriorate. In the example of 143117.doc 201027555, the data stored in the page 4 (lower page) of the same memory unit during the data writing to the page 5 (upper page) is deteriorated at the same time. If the lower page and the upper page of the memory cell include more pages, this problem occurs similarly for all pages of the memory cell. The same problem can be seen in the NAND flash 4 according to the present embodiment: the address conversion table 8, the first storage unit 9, the second storage unit 10, and the area φ 鬼 官 list 11 have substantially the same structure. This embodiment is intended to prevent this problem from occurring. The address conversion table 8 indicates the page position (address) of the material of the NAND flash R 〇 M 4 that is stored by the host device 6. The address conversion table 8 thus stores therein the location (address) of the NAND flash ROM 4 for storing the material supplied by the host device 6 for each page. Here, the material whose address is stored in the page in the address conversion table 8 or in other words, the information specified by the address conversion table 8 is referred to as valid data. On the other hand, the data whose address is not stored in the page of the address conversion φ Table 8 or, in other words, the data which is stored but not specified by the address conversion table 8, is referred to as invalid data. The address conversion table 8 is only present in the NAND flash ROM 4 when the semiconductor memory device 1 is not operating. However, when the host device 6 issues a material write/read command to the semiconductor memory device 1, the address conversion table 8 is read from the NAND flash ROM 4 and temporarily stored in the DRAM 3. Next, the address conversion unit 14 of the controller 5, which will be described later, performs an address update process on the address conversion table 8 temporarily stored in the DRAM 3. The address update process for the address translation table 8 in the NAND flash ROM 4 is performed at any given timing, such as when the semiconductor storage 143117.doc 201027555 device 1 stops its operation. The first storage unit 9 and the second storage unit 1G each include a plurality of blocks, referred to as & In each of the blocks, the data stored in the DRAM 3 by the host device 6 and stored by the host device 6 is written. When the data is actually written, the write/read command unit 13 of the controller 5, which will be described later, selects a block from the blocks of the first storage unit 9 and the second storage unit 10. In Fig. 1, the first remaining unit 9 includes four blocks A to D, and the second storage unit 1 includes two blocks E and F. All the merchandise supplied by the host device 6 and temporarily stored in the DRAM 3 is first written in the block (first block) of the first storage unit 9. On the other hand, when there is no writable block in the first storage unit 9, only the material specified by the mobile unit 16 of the controller 5 described later is moved and written from the block of the first storage unit 9. The second storage unit 1 is in the block (second block). It should be noted that the blocks of the first storage unit 9 and the blocks of the second storage unit 1 are not fixed, but may be dynamically changed by the block management unit 17 of the controller 5 described later. The block management list 11 manages the block of the first storage unit 9 and the block of the second storage unit 10 as illustrated in FIG. In this figure, four blocks a to D belong to the first storage unit 9, and two blocks e and F belong to the second storage unit 10. The block management list 11 exists only in the NAND flash ROM 4. However, the structure can be configured such that when the host device 6 issues a data write/read command to the semiconductor memory device 1, the block management list 11 is read from the NAND flash ROM 4 and temporarily stored in the DRAM 3. In this configuration, the temporary storage 143117.doc • 10- 201027555 The block management list 11 stored in the DRAM 3 should be updated by the block management unit 17 described later by the controller 5, and the NAND flash ROM 4 The block management list 11 should be updated at any given timing, such as when the semiconductor storage device 1 is turned off. The controller 5 controls the operation of the semiconductor storage device 1. The controller 5 includes a CPU 12 and controls the semiconductor storage device 1 in accordance with an instruction executed by the CPU 12. The CPU 12 includes a write/read instruction unit 13, an address conversion unit ❹ 14, a judgment unit 丨5, a mobile unit 16, and a block management unit 17. Actually, the program executed by the CPU 12 has a module structure including a write/read instruction unit 13, an address conversion unit 14, a determination unit 15, a mobile unit, and a block management unit 17. When the CPU 12 reads a program from R〇M or the like (not shown) and executes the program, the write/read instruction unit 13, the address conversion unit 14, the determination unit 15, the mobile unit 16, and the block The management unit 17 is generated on the CPU 12. In response to a request from the host device 6, the write/read command unit 13 issues a write of the data of the DRAM 3 to the NAND flash R〇M 4 (the area of the first storage unit 9 designated by the determination unit 15). The data write command of the block or the data read command from the NAND flash ROM 4 (the block of the first storage unit 9 or the second storage unit (7)) is read to the DRAM 3. The address conversion table S 转换 converts the address other than the material supplied from the host device 6 into the page of the actual stored data of the block of the NAND flash ROM 4. More specifically, 'when the data supplied from the host device 6 is stored in the flash ROM 4', the address conversion unit 14 associates the location other than the data with the page of the stored material of the block and stores it. In the address conversion table 8. When 143117.doc -11· 201027555 receives a read request from the host device 6, the address translation unit 14 converts the external address into a corresponding page of the block. In other words, address translation is performed for individual pages. As illustrated in Fig. 4, the address conversion unit 14 refers to the address conversion table 8 to convert the location other than the data supplied from the host device 6 into the page of the block in NANJ> In detail, during the conversion by the address conversion unit 14, some of the highest bits of the external location supplied by the host device 6 are converted into pages of the block of the NAND flash ROM 4, and the remaining lower bits are The meta is converted to the location of the data within the page. According to Figure 4, the address supplied from the external address has 48 bits. The upper 37 bits of the external address are used to convert to the page of the block, while the lower 11 bits of the external address are used to convert to the data location of the page. The number of bits varies depending on the capacity of the page. The data stored on the page position of the block in the nand flash ROM 4 stored in the address conversion table 8 is valid data stored in association with the individual external address, and thus the data is not allowed to deteriorate. In a semiconductor storage device with NAND flash ROM, write to
NAND快閃ROM中之前需要抹除操作。此外，僅在NAND 快閃ROM之特定區域中之頻繁重寫入將縮短r〇m之壽 命。出於此等原因，位址轉換單元通常提供於此裝置中以 將由主機裝置供應之外部位址之資料儲存於任意區塊及頁 中。 當自主機裝置6接收到資料寫入請求時，判斷單元15判 斷第一儲存單元9中是否存在其中未儲存有效資料之任何 區塊，且識別此區塊。更具體言之，判斷單元丨5自第一儲 143117.doc •12- 201027555 2元9之該等區塊識別其中未儲存由位址轉換表8指定之 資^有效資料）的區塊。接著，寫入/讀取指令單元Η將自 裝置6接收之資料寫入至所識別之區塊中。 以下參看圖5解釋由判斷單元15採用之判斷方法。在此 圖式中’區塊屬於第—儲存單元9。在區塊中， 區塊A為其中未儲存任何有效資料或換言之由位址轉換表8 指定之資料的唯—區塊。判斷單元15因此識別區塊The erase operation is required before the NAND flash ROM. In addition, frequent rewriting in only certain areas of the NAND flash ROM will shorten the life of r〇m. For these reasons, the address translation unit is typically provided in the device to store data from locations external to the host device in any of the blocks and pages. When receiving a material write request from the host device 6, the judging unit 15 judges whether or not any of the blocks in which the valid data is not stored exists in the first storage unit 9, and identifies the block. More specifically, the judging unit 丨5 recognizes the blocks in which the blocks of the first storage 143117.doc • 12- 201027555 2 and 9 are not storing the valid data specified by the address conversion table 8 . Next, the write/read command unit 写入 writes the data received from the device 6 into the identified block. The judging method employed by the judging unit 15 will be explained below with reference to Fig. 5 . In this figure, the 'block' belongs to the first-storage unit 9. In the block, block A is a unique block in which no valid data or, in other words, the data specified by the address translation table 8 is stored. The judging unit 15 thus identifies the block
/自主«置6接收到資料寫入請求時且當第一儲存單 疋9不包括其中未儲存有效資料之區塊時，或換言之，當 第—儲存單元9之所有區塊在其中儲存有效f料之至少一 項時，移動單元16將儲存於第一儲存單元9之該等區塊中 之有效資料移動至第二儲存單元1〇的一區塊。更具體言 之’移動單元將儲存於第一儲存單元9之該等區塊中^ 有效資料讀取至DRAM 3,且將資料—次寫人 單元10的一區塊中。 仔 、、以下參看圖6及圖7解釋由移動單元16採用之資料移動方 法。圖6為用於展示在由移動單元16移動之前之資料的 圖’且圖7為用於展示由移動單元“移動之後之資料的 圖在圖6中，至少一有效資料項儲存於第一健存單元9之 區免A至D中之每一者中。因此’移動單元將儲存於區 塊A至D中之有效資料移動至第二儲存單元1()之區塊£，如 圖中所-尤B月。在移動單元16移動資料之後，位址轉換單 4更新位址轉換表8中之資料項之位置以指示資料項所 移動至的位置。因& ’儲存於區塊A至區塊D中之所有有 143117.doc -13- 201027555 效資料項改變為無效資料項。 區塊管理單元17管理區塊管理清單^，或換言之，第一 儲存單元9及第二儲存單元1〇之區塊。如之前所描述，第 一儲存單7G 9之區塊用於寫入由主機裝置6供應之資料，而 第二儲存單元10之區塊僅在資料由移動單元16移動時使 用。/ autonomous «set 6 when receiving a data write request and when the first storage unit 9 does not include a block in which valid data is not stored, or in other words, when all the blocks of the first storage unit 9 are stored therein are valid f At least one of the materials, the mobile unit 16 moves the valid data stored in the blocks of the first storage unit 9 to a block of the second storage unit 1 . More specifically, the mobile unit reads the valid data stored in the blocks of the first storage unit 9 into the DRAM 3, and stores the data in a block of the secondary write unit 10. Next, the data moving method adopted by the mobile unit 16 will be explained with reference to Figs. 6 and 7. 6 is a diagram for showing the material before being moved by the mobile unit 16 and FIG. 7 is a diagram for showing the data after the movement by the mobile unit. In FIG. 6, at least one valid data item is stored in the first health. The area of the storage unit 9 is free from each of A to D. Therefore, the 'moving unit moves the valid data stored in the blocks A to D to the block of the second storage unit 1 (), as shown in the figure. - Especially B. After the mobile unit 16 moves the data, the address translation unit 4 updates the position of the data item in the address translation table 8 to indicate the location to which the data item is moved. Since & 'is stored in block A to All of the blocks 143 have a 143117.doc -13 - 201027555 effect data item changed to an invalid data item. The block management unit 17 manages the block management list ^, or in other words, the first storage unit 9 and the second storage unit 1 The block of the first storage list 7G 9 is used to write the material supplied by the host device 6, and the block of the second storage unit 10 is used only when the data is moved by the mobile unit 16.
在移動單元16將儲存於第一儲存單元9之該等區塊中之 資料移動至第二儲存單元10的一區塊中之後，區塊管理單 元17更新區塊管理清單u，使得在儲存於第一儲存單元9 之該等區塊中之資料移動至第二儲存單元1〇的該區塊之 後，第二儲存單元1()之資料自第—儲存單元9之該等區塊 所移動至的此區塊移動至第一儲存單元9,且第一儲存單 元9之區塊中之一者移動至第二儲存單元1〇。此處假設第 儲存單元9之移動至第二儲存單元1〇之區塊在資料移動 至第二儲存單元10之後未在其中儲存有效資料。After the mobile unit 16 moves the data stored in the blocks of the first storage unit 9 into a block of the second storage unit 10, the block management unit 17 updates the block management list u so that it is stored in After the data in the blocks of the first storage unit 9 is moved to the block of the second storage unit 1 , the data of the second storage unit 1 ( ) is moved from the blocks of the first storage unit 9 to This block moves to the first storage unit 9, and one of the blocks of the first storage unit 9 moves to the second storage unit 1 . It is assumed here that the block of the first storage unit 9 moved to the second storage unit 1 has not stored valid data therein after the data has been moved to the second storage unit 10.
自圖6及圖7,可見在圖6中於資料移動之前在區塊管王】 清單U中屬於第二儲存單元1G的區塊E在圖7中於資料移重 之後移動至第-儲存單元9,且在資料移動之前屬於第一 儲存單元9之區塊A移動至第二儲存單元1()。在此實例中， 區塊A至區塊D中具有當前未儲存有效資料之最少未使用 頁的區塊A移動至第二儲存單元…此係因為抹除過㈣ ^第二儲存單元1G中對每-區塊之所有頁執行（不管該筹 頁經使用或未經使用），且因此可藉由將具有最少未使用 頁之區塊移動至第二儲存單元1〇來消除不必要的操作。 143117.doc -14- 201027555 接著，移動單元16及區塊管理單元17將第-儲存單元9 之£塊八至區塊])中之所有有效資料移動至區塊砂得資料 可寫^至區塊B至區塊〇中，但不可寫入至已移動至第二 儲存單元10的區塊A中。 "接下來，參看圖8解釋根據本實施例之將新資料寫入至 半導體儲存裝置1之NAND快閃R〇M 4中的方法。當半導體 儲存裝置1接收到來自主機裝置6之資料寫人指令時，由主 φ 機裝置6供應之待寫入的資料臨時儲存於DRAM3中。 接著，判斷單元15判斷第一儲存單元9是否包括其中未 儲存有效資料之任何區塊（步驟su)。更具體言之，判斷單 元15判斷第一儲存單兀9之區塊中是否存在其中未儲存由 位址轉換表8指定之資料（有效資料）的任何區塊。 當判斷單元15判斷第一儲存單元9包括其中未儲存有效 資料之區塊（步驟S11處之是）時，判斷單元15識別此區塊。 寫入/讀取指令單元13發出將資料寫入至第一儲存單元9之 • 其中未儲存有效資料之該區塊中的指令（步驟S12) ^資料 藉此寫入至區塊中。 另一方面，當判斷單元15判斷第一儲存單元9中不存在 其中未儲存有效資料之區塊（步驟S11處之否）時，移動單元 16將第一儲存單元9中之一些區塊中的有效資料移動至第 二儲存單元10之一區塊（步驟S13)。較佳移動該等區塊中 之所有有效資料使得在移動之後此等區塊中不保留有效資 料。當第二儲存單元10包括一個以上區塊時，可將有效資 料一次移動至多個區塊。然而，較佳針對每一區塊一次處 143117.doc -15- 201027555 理該等有效資料項。 如之前所提及，移動單元16首先將儲存於NAND快閃 ROM 4之區塊中之有效資料讀取至Dram 3，且接著將其 寫入至NAND快閃ROM 4的另一區塊。然而，若有效資料 在當前寫入指令之前已回應於先前自主機裝置6發出之讀 取指令而自NAND快閃ROM 4讀取且臨時儲存於DRAM 3 中，則此資料可直接寫入。在此情形下，可節省將nand 快閃ROM 4之區塊中之有效資料讀取至dram 3中所需的 時間。 接下來，位址轉換單元14更新關於移動至第二儲存單元 1〇之區塊之有效資料的位址轉換表8，使得其指示有效資 料所移動至的位置（第二儲存單元1〇之區塊/頁位置）（步驟 S14)。 接著，區塊管理單元17將第二儲存單元1〇之有效資料所 移動至的區塊移動至第一儲存單元9之清單’且將第一儲 存單元9之自其移動有效資料之無有效資料區塊移動至第 二儲存單元10的清單（步驟S15)。可在此步驟移動任何數 目之區塊。 此後’在步驟S12 ’寫入/讀取指令單元13發出將資料寫 入至第一儲存單元9之未儲存有效資料之區塊（自其移動有 效資料之區塊)中的指令，且藉此將資料寫入至該區塊 中。 最後，位址轉換單元14以關於寫人至區塊中之資料的位 址轉換表8指示資料所移動至的位置(第一儲存單元9之區 143117.doc 16 201027555 塊/頁位幻之方式更新該表（步驟S16)。在以上步驟之後， 將新資料寫入快閃R〇M4t之操作完成。 在步驟S12’當第一儲存單元9包括其中未儲存有效資料 之-個以上區塊時’寫入/讀取指令單元13需要選擇該等 區塊中之一者。若選擇具有未寫入資料之最少未使用頁之 區塊，或換言之，若選擇具有最大量之經寫人資料的區 塊，則保留具有最多未使用頁之區塊。接著，即使在此後 接收到寫人具有跨縣干頁之大的大小之資料的請求時， 可在不執行抹除操作之情形下寫入資料。因此，可減少抹 除之數目’此情形增加半導體儲存裝置職仙快閃職 4)之壽命。應注意，選擇方法不限於以上方法，而是可任 思地選擇一區塊。 ❹ 在根據第-實施例之半導體儲存裝置中，當判斷單元判 斷第-儲存單元中之區塊中之任一者在其中未儲存與外部 位址相關聯的資料時’可將外部供應之新資料寫入其中未 儲存與外部位址相關聯之任何資料的區塊中。因此，、可減 少資料抹除之數目，同時可防止先前儲存於新資料待以 之同-區塊中的有效資料惡化及變得不可讀取。亦 資料寫入速度。 ^ 此外’在根據第-實施例之半導體儲存裝置中，當判斷 單元判斷第-儲存單元之所有區塊在其中錯存與外:位址 相關聯的-些資料時，移動單元將與外部位址相關聯且儲 存於第-儲存單元之區塊中之資料移動至第二儲存單元的 區塊中，使得可將外部供應之資料新寫入自其移動斑外邻 143117.doc •17· 201027555 位址相關聯之資料的區塊中。由此，在減少資料抹除之數 目時，防止先前儲存於新資料待寫入至之區塊中之有效資 料惡化及變得不可讀取，且增加資料寫入速度。 在根據本實施例之半導體儲存裝置丨中，當接收到來自 主機裝置6之資料寫入請求時，判斷單元15判斷第一儲存 單元9是否包括未儲存有效資料之任何區塊，且若存在， 則識別此種區塊。然而，移動單元16將不移動任何有效資 料直至第一儲存單元9中不再存在其中未儲存有效資料之 區塊為止。出於此原因，一旦判斷單元15判斷不存在其中❾ 未儲存有效資料之區塊時，自資料寫入請求之開始至結束 之過程即花費極長時間。 相比之下，修改實例以如下之此種方式經組態：在接收 到來自主機裝置6之資料寫入請求後，判斷單元15即判斷 儲存於第-儲存單元9之區塊中之有效資料的總量是否超 過對應於一個區塊之資料量，且識別此等區塊。接著，每 -人有效貝料之總量變為對應於一個區塊之量移動單元Μ 便將儲存於第-财單元9之該等區塊中之有效資料移動@ 至第二儲存單元1〇的一區塊。可藉此使自資料寫入請求之 開始至結束所需之時間達到平均（可改良需要最長時間之 一在此修改實例中，當主機裝置6向半導體儲存裝置ι發出 資料寫人&令時，判斷單元15判斷儲存於第—儲存翠元9 之區塊中之有效資料之總量是否等於或大於對應於一個區 塊的資料量（步驟S21)，如圖9中所說明。更具體言之，判 143117.doc -18- 201027555 斷單元15判斷第一儲存單元9之區塊中之由位址轉換表8指 定的資料（有效資料）之總量是否等於或大於對應於—個區 塊之資料量。 當判斷單元15判斷儲存於第一儲存單元9之區塊中之有 效資料的總量不大於對應於一個區塊之資料量（步驟S2i處 • 之否）時’判斷單元15識別第一儲存單元9中之其中未储存 任何有效資料一之區塊。接著，寫入/讀取指令單元13發 φ 出將資料寫入至第一儲存單元9之其中未儲存有效資料的 該區塊中之指令（步驟S22)，且資料經寫入至此區塊中。 此處假設，當儲存於第一儲存單元9之區塊中之有效資料 的總量未達到對應於一個區塊之資料量時，第一儲存單元 9始終包括其中未儲存有效資料之區塊。 另一方面，當判斷單元15判斷儲存於第一儲存單元9之 區塊中之有效資料的總量等於或大於對應於一個區塊之資 ^置（步驟S21處之是）時’移動單元16將儲存於第一儲存 ❹單it 9之些區塊中的等同於—個區塊之有效資料移動至 第一儲存皁兀10之—區塊（步驟S23)。以下步驟824至§26 處之操作與圖8之步驟S14至S16相同，且因此省略其 釋。 、 在此修改實财，基於關於儲存於第-儲存單元9之區 東:之有放資料的總量是否等於或大於等同於一區塊之資 料置的判斷來判定移動單元16是否移動資料。然而，判斷 可基於關於有效眘 σ 貝科疋否等於或大於等同於η個區塊之資 料量（其中η為正整數）。 143117.doc -19· 201027555 在根據第一實施例之修改實例的半導體儲存裝置中，當 判斷單元判斷與外部位址相關聯且儲存於第一儲存單元之 區塊中之資料的總量未達到特定資料量時，可將外部供應 之資料新寫入至其中未儲存與外部位址相關聯之任何資料 的區塊中。因此，在減少資料抹除之數目時，防止先前儲 存於新資料經寫入其中之區塊中的有效資料惡化及變得不 可讀取。可改良資料寫人速度，且可使自資料寫入請求之 開始至結束之時間達到平均。6 and FIG. 7, it can be seen that the block E belonging to the second storage unit 1G in the block U in the block U in FIG. 6 is moved to the first storage unit after the data is transferred in FIG. 7 9, and the block A belonging to the first storage unit 9 before the data movement moves to the second storage unit 1 (). In this example, the block A of the block A to the block D having the least unused page that does not currently store the valid data is moved to the second storage unit... This is because the erased (4) ^ the second storage unit 1G All pages of each block are executed (regardless of whether the page is used or not used), and thus unnecessary operations can be eliminated by moving the block with the least unused pages to the second storage unit 1 . 143117.doc -14- 201027555 Next, the mobile unit 16 and the block management unit 17 move all the valid data in the block 8 to block] of the first storage unit 9 to the block sand data to be written to the area Block B is in block , but cannot be written to block A that has moved to the second storage unit 10. " Next, a method of writing new data into the NAND flash R〇M 4 of the semiconductor memory device 1 according to the present embodiment will be explained with reference to FIG. When the semiconductor storage device 1 receives the data writer command from the host device 6, the data to be written supplied from the main device 6 is temporarily stored in the DRAM 3. Next, the judging unit 15 judges whether or not the first storage unit 9 includes any block in which the valid material is not stored (step su). More specifically, the judging unit 15 judges whether or not any block in which the material (valid data) specified by the address conversion table 8 is not stored exists in the block of the first storage unit 9. When the judging unit 15 judges that the first storage unit 9 includes the block in which the valid data is not stored (YES at step S11), the judging unit 15 recognizes the block. The write/read instruction unit 13 issues an instruction in the block in which the data is written to the first storage unit 9 (where the valid data is not stored) (step S12). The data is thereby written into the block. On the other hand, when the judging unit 15 judges that there is no block in the first storage unit 9 in which the valid data is not stored (NO at step S11), the mobile unit 16 will be in some of the blocks in the first storage unit 9. The valid data is moved to a block of the second storage unit 10 (step S13). Preferably, all of the valid data in the blocks are moved such that no valid data is retained in the blocks after the move. When the second storage unit 10 includes more than one block, the valid data can be moved to a plurality of blocks at a time. However, it is preferable to treat these valid data items once for each block at 143117.doc -15- 201027555. As mentioned previously, the mobile unit 16 first reads the valid data stored in the block of the NAND flash ROM 4 to the Dram 3 and then writes it to another block of the NAND flash ROM 4. However, if the valid data has been read from the NAND flash ROM 4 and temporarily stored in the DRAM 3 in response to a read command previously issued from the host device 6 before the current write command, the data can be directly written. In this case, the time required to read the valid data in the block of the nand flash ROM 4 into the dram 3 can be saved. Next, the address conversion unit 14 updates the address translation table 8 regarding the valid material of the block moved to the second storage unit 1 so that it indicates the location to which the valid data is moved (the area of the second storage unit 1) Block/page position) (step S14). Then, the block management unit 17 moves the block to which the valid data of the second storage unit 1 is moved to the list of the first storage unit 9 and moves the valid data of the first storage unit 9 from the valid data. The block moves to the list of the second storage unit 10 (step S15). You can move any number of blocks in this step. Thereafter, at step S12, the write/read command unit 13 issues an instruction to write data to the block of the first storage unit 9 where the valid data is not stored (from the block in which the valid data is moved), and thereby Write data to this block. Finally, the address conversion unit 14 indicates the location to which the data is moved in the address conversion table 8 on the data in the write-to-block (the area of the first storage unit 9 143117.doc 16 201027555 block/page illusion) The table is updated (step S16). After the above steps, the operation of writing new data to the flash R〇M4t is completed. When the first storage unit 9 includes more than one block in which the valid data is not stored, in step S12' The write/read instruction unit 13 needs to select one of the blocks. If a block having the least unused page with no data to be written is selected, or in other words, if the file having the largest amount of the file is selected, Block, the block with the most unused pages is retained. Then, even after receiving a request for the writer to have a large size data across the county dry page, the write operation can be performed without performing the erase operation. Information. Therefore, the number of erasures can be reduced. 'This situation increases the life of the semiconductor storage device. It should be noted that the selection method is not limited to the above method, but a block can be selected arbitrarily. ❹ In the semiconductor storage device according to the first embodiment, when the judging unit judges that any one of the blocks in the first storage unit does not store the material associated with the external address therein, the external supply may be newly added. The data is written into a block in which no data associated with the external address is stored. Therefore, the number of data erases can be reduced, and at the same time, the effective data previously stored in the same data block to be corrupted and become unreadable can be prevented. Also write data speed. ^ In addition, in the semiconductor storage device according to the first embodiment, when the judging unit judges that all the blocks of the first storage unit are in which the data associated with the outer: address is misregistered, the mobile unit will be externally The data associated with the address and stored in the block of the first storage unit is moved to the block of the second storage unit, so that the externally supplied data can be newly written from its moving spot neighbor 143117.doc •17· 201027555 The block of the data associated with the address. Thus, when the number of data erasures is reduced, the effective data previously stored in the block to which the new data is to be written is prevented from deteriorating and becoming unreadable, and the data writing speed is increased. In the semiconductor storage device according to the present embodiment, when receiving a data write request from the host device 6, the judging unit 15 judges whether the first storage unit 9 includes any block in which the valid data is not stored, and if so, Then identify such a block. However, the mobile unit 16 will not move any valid data until the block in the first storage unit 9 in which no valid data is stored is no longer present. For this reason, once the judging unit 15 judges that there is no block in which the valid material is not stored, it takes a very long time from the start to the end of the data write request. In contrast, the modified example is configured in such a manner that upon receiving the data write request from the host device 6, the determining unit 15 judges the valid data stored in the block of the first storage unit 9. Whether the total amount exceeds the amount of data corresponding to one block and identifies such blocks. Then, the total amount of effective beakers per person becomes a mobile unit corresponding to one block, and the valid data stored in the blocks of the first financial unit 9 is moved @ to the second storage unit 1 One block. This can be used to average the time required from the beginning to the end of the data write request (one of which can be improved for the longest time). In this modified example, when the host device 6 sends a data to the semiconductor storage device ι writes & The judging unit 15 judges whether the total amount of the valid data stored in the block of the first storage emerald 9 is equal to or larger than the amount of data corresponding to one block (step S21), as illustrated in Fig. 9. More specifically , 141117.doc -18- 201027555 The breaking unit 15 determines whether the total amount of the data (valid data) specified by the address conversion table 8 in the block of the first storage unit 9 is equal to or larger than the corresponding block. When the judging unit 15 judges that the total amount of valid data stored in the block of the first storage unit 9 is not larger than the amount of data corresponding to one block (NO at step S2i), the judgment unit 15 recognizes The block of any valid data is not stored in the first storage unit 9. Then, the write/read command unit 13 sends out the data to the area of the first storage unit 9 in which the valid data is not stored. Piece The instruction (step S22), and the data is written into the block. It is assumed here that when the total amount of valid data stored in the block of the first storage unit 9 does not reach the amount of data corresponding to one block The first storage unit 9 always includes the block in which the valid data is not stored. On the other hand, when the judging unit 15 judges that the total amount of the valid data stored in the block of the first storage unit 9 is equal to or larger than the corresponding one area When the block is set (YES at step S21), the mobile unit 16 moves the valid data of the same block stored in the blocks of the first storage unit it 9 to the first storage sapon 10 The block (step S23). The operations at the following steps 824 to § 26 are the same as the steps S14 to S16 of Fig. 8, and thus the explanation thereof is omitted. Here, the real money is modified based on the storage in the first storage unit 9 Zone East: Whether the total amount of data is equal to or greater than the judgment of the data of one block to determine whether the mobile unit 16 moves the data. However, the judgment can be based on whether the effective caution σ 疋 等于 等于 is equal to or greater than Equivalent to n blocks In the semiconductor storage device according to the modified example of the first embodiment, when the judging unit judges that it is associated with the external address and is stored in the first storage unit When the total amount of data in the block does not reach a certain amount of data, the externally supplied data can be newly written to the block in which any data associated with the external address is not stored. Therefore, the data erased is reduced. In the case of numbers, the effective data previously stored in the block in which the new data is written is prevented from being deteriorated and becomes unreadable. The speed of writing the data can be improved, and the time from the start to the end of the data write request can be reached. average.
(第二實施例）(Second embodiment)
根據第-實施例，當第一儲存單元無其中未健存任何； 效資料之區塊時，將第一儲存單元之區塊之有效資_ 至第二儲存單元的區塊。相比之下，根據第二實施例，一 第-儲存單元無其中未儲存可變為丢失之任何有效資心 區塊時’將儲存於第-儲存單元之區塊中之有效資料移儀 至第二儲存單元的區塊。解釋根據本實施例之半導體儲4 裝置結構’集中於第—實施例㈣二實施例之間的不同肩 上。該結構之剩餘部分與第-實施例相同，且因此將相p 數字給予此等部分。与· 6士 該、.、Q構之剩餘部分的解釋應參」 描述且在此處被省略。 如以上針對第一實施例參看圖2所解釋，當資料寫入] 上.P頁中時’可出現已寫入至同一記憶體單元之下邙頁t 之：：惡化及丟失的問題。在圖2之實例中若在⑽ 二體ΐ上部頁)中時斷開電源供應器，則健存於共用同-隐體早兀之頁4(下部頁)中的資料可惡化。 143117.doc •20· 201027555 當儲存於下部頁（頁4)中之資料為無效資料時，寫入操 作即使失敗亦不會造成任何問題，因為可變為吾失的資料 並非有效資料。類似地，當寫入操作自下部頁開始時，寫 入之失敗將不會造成有效資料之丟失。此點構成根據本實 施例之半導體儲存裝置之特徵。 如圖10中所說明，根據第二實施例之半導體儲存裝置21 包括主機介面2、DRAM 3、NAND快閃ROM 22及控制器 ❿ 23°NAND快閃R0M 22包括位址轉換表8、第一儲存單^ 9、第二儲存單元10、區塊管理清單u及區塊記憶體管理 清單24。 區塊記憶體管理清單24指示區塊中之那些頁在其中儲存 有資料，如圖11中所說明。在此圖式中，資料已儲存達區 塊之頁4 ’且未使用頁5及隨後頁。區塊記憶體管理清單 儲存第一儲存單元9及第二儲存單元10之所有區塊之記憶 體狀態。 φ 區塊記憶體管理清單24僅存在於NAND快閃ROM 22中。 然而，區塊記憶體管理清單24可經組態以當主機襞置6向 半導體儲存裝置21發出資料寫入/讀取指令時自NAND快閃 ROM 22讀取且臨時儲存於dram 3中。在此組態中，控制 |§ 23之稍後描述之區塊記憶體管理單元27更新臨時儲存於 DRAM 3中的區塊記憶體管理清單24。NAND快閃ROM 22 中之區塊記憶體管理清單24係在諸如當半導體儲存裝置21 停止其操作時之任何給定定時更新。 控制器23包括CPU 25，且根據由CPU 25執行之指令控 143117.doc -21 · 201027555 CPU 25包括寫入/讀取指令單元 判斷單元26、移動單元16、區塊管 制半導體儲存裝置21 13、位址轉換單元14、 理單元17及區塊記憶體管理單元27。 當自主機裝置6接收到資料寫入請求時，判斷單元％判 斷第-儲存單元9之區塊中是否存在新資料寫入將不會造 成有㈣料之丟失的區塊，且若存在，則制此區塊。更 具體&之’判斷單元26藉由使用位址轉換表8及區塊記憶 體管理清單24判斷是否存在新資料寫人自上部頁開始且對 應於此上部頁之下部頁在其中儲存無效資料的任何區塊， 或是否存在其中新資料寫人自下部頁開始之任何區塊。若 存在’則判斷單元26識別此區塊。 現參看圖12解釋由判斷單元26採用之判斷方法4此圖 式中，包括於每-區塊中之「L」指定下部頁，而包括於 每-區塊中之「U」指定上部頁。圖12之第一儲存單元9包 括區塊Α至D。在區塊八至〇中，新資料寫入自區塊Α中之 下部頁開始，且因此此區塊可用作寫入新資料之區塊。類 似地，新資料寫入自區塊D中之上部頁開始，且儲存於相 應下邻頁中之資料為無效的。因此，該區塊可用作寫入新 資料之區塊。在圖12中，判斷單元26指定區塊1)，但其可 替代指定區塊A。 接著，當自主機裝置6接收到資料寫入請求時，但當第 一儲存單元9之區塊不包括新資料寫入將不會造成有效資 料之丟失的任何區塊時，移動單元16將儲存於第一儲存單 元9之區塊中之有效資料移動至第二儲存單元1〇的區塊。 143117.doc -22* 201027555 區塊纪憶體管理單元27管理區塊記憶體管理清單24，或 換。之，第一儲存單元9及第二儲存單元ίο之區塊_之每 —頁的記憶體狀態。 接下來’在根據本實施例之半導體儲存裝置21中，以下 :看圖13解釋將新資料寫入至NAND快閃中的方 法。當主機裝置6向半導體儲存裝置21發出資料寫入指令 寺由主機裴置6供應之待寫入的資料臨時儲存mDRAM 3 中。 接著’判斷單兀26判斷第一儲存單元9之區塊是否包括 新資料寫入將不會造成有效資料之丟失的任何區塊(步驟 更具體言之’判斷單元26判斷是否存在新資料寫入 自上部頁開始且儲存於相應下部頁中之資料為無效資料的 任何區塊，或是否存在新資料寫入自下部頁開始之任何區 塊。 當判斷單元26判斷第一儲存單元9之區塊包括新資料寫 φ 入將不會造成有效資料之丟失的區塊(步驟s3i處之是 時·，判斷單元26識別此區塊。寫入/讀取指令單元13發出 將資料寫人至第-儲存單元9之未儲存有效資料之該區塊 中的資料寫人指令（步驟S32)使得f料寫人操作在此區塊 上執行。 另-方面’當判斷單元26判斷第一儲存單元9之區塊不 包括新資料寫人將不會造成有效資料之丢失的任何區塊 (步驟S3i處之否）時，移動單元_第—儲存單元9之一些 區塊中的有效資料移動至第二赌存單元_ —區塊（步驟 143117.doc •23. 201027555 S33)。在此步驟，較佳移動此等區塊中之所有有效資料使 得在移動之後區塊中不保留有效資料。若第二儲存單元1〇 包括-個以上區塊，則可將有效資料一次移動至多個區 免」而較佳針對每一區塊一次處理待移動之有效資料 的項。 接著，位址轉換單元14更新關於移動至第二儲存單元10 之區塊之有效資料的位址轉換表8，使得位址轉換表8指示 有效資料所移動至的位置（第二儲存單元1〇中之區塊/頁位 置）（步驟S34)。 接下來，區塊管理單元17將第二儲存單元1〇之有效資料 已移動至的區塊移動至第一儲存單元9之清單，且將第一 儲存單元9之已自其移動有效資料且當前未儲存有效資料 之區塊移動至第二儲存單元10之清單（步驟S35)。此處移 動之區塊之數目不受限制。 此後，在步驟S32，寫入/讀取指令單元13發出將資料寫 入至第一儲存單兀9之未儲存有效資料之區塊（亦即，自其 移動有效資料之區塊）中的資料寫入指令，且藉此在此區 塊上執行資料寫入操作。 接下來，區塊記憶體管理單元27更新區塊記憶體管理清 單24，或換言之，第一儲存單元9及第二儲存單元⑺之區 塊中之每一頁的記憶體狀態（步驟S36)。 最後’位址轉換單元14更新關於經寫入至區塊中之資料 之位址轉換表8使得位址轉換表8指示資料所移動至的位置 (第一儲存單元9之區塊/頁位置）（步驟S37)。經由以上步 I431I7.doc -24- 201027555 驟’將新資料寫入至NAND快閃ROM 22中之過程完成。 在根據第二實施例之半導體儲存裝置中，當判斷單元判 斷第一儲存單元不包括其中與外部位址相關聯之資料不會 因寫入新資料而丟失的任何區塊時，可將外部供應之資料 新寫入至其中與外部位址相關聯之資料將不會丟失之區 •塊。因此，在減少資料抹除之數目時，防止先前儲存於新 資料待寫入至之區塊中的有效資料惡化及變得不可讀取。 此外’可增加資料寫入速度。 9 另外，在根據第二實施例之半導體儲存裝置中，判斷單 元識別其中即使寫入操作失敗有效資料亦不會丟失之區塊 作為用於新寫入外部供應的資料之區塊。此增加資料寫入 至之區塊之選擇，同時可減少由移動單元進行之資料移動 之數目，藉此增加重寫入的壽命。 熟習此項技術者將易於想到額外優勢及修改。因此，本 發明就其較廣泛態樣而言不限於本文中所展示並描述之特 參 定細節及代表性實施例。因此，可在不脫離如由隨附申請 專利範圍及其等效物界定之一般發明性概念之精神或範疇 的情況下進行各種修改。 【圖式簡單說明】 圖1為根據第一實施例之半導體儲存裝置之方塊圖； 圖2為用於解釋MLCNAND快閃ROM之結構之圖； 圖3為說明區塊管理清單之圖； 圖4為用於解釋位址轉換方法之圖； 圖5為用於解釋根據第一實施例之判斷方法之圖； 143117.doc •25- 201027555 圖6為用於解釋根據第一實施例之資料移動方法的圖. 圖7為用於亦解釋根據第一實施例之資料移動方法 園， 圖8為根據第一實施例之將新資料寫入至NAND快閃 ROM中之程序的流程圖； 圖9為根據修改實例之將新資料寫入至NAND快閃ROM 中之程序的流程圖； 圖10為根據第二實施例之半導體儲存裝置之方塊圖； 圖11為說明根據第二實施例之區塊記憶體管理清單的 1£) · 圃， 圖12為用於解釋根據第二實施例之判斷方法之圖；及 圖13為根據第二實施例之將新資料寫入至nand快閃 ROM中之程序的流程圖。 【主要元件符號說明】 1 半導體儲存裝置 2 主機介面 3 動態隨機存取記憶體（DRAM) 4 NAND快閃唯讀記憶體（ROM) 5 控制器 6 主機裝置 7 寫入/讀出資料 8 位址轉換表 9 第一儲存單元 10 第二儲存單元 143117.doc 201027555 11 區塊管理清單According to the first embodiment, when the first storage unit has no block in which any data is not stored, the valid block of the first storage unit is transferred to the block of the second storage unit. In contrast, according to the second embodiment, when a first storage unit does not store any valid core blocks that are lost to be lost, the valid data is to be stored in the block of the first storage unit to A block of the second storage unit. It is explained that the structure of the semiconductor memory device according to the present embodiment is focused on the different shoulders between the two embodiments of the first embodiment (four). The remainder of the structure is the same as in the first embodiment, and thus the phase p number is given to these parts. Interpretation of the remainder of the structure of the ., Q, and Q should be described and omitted here. As explained above with reference to Fig. 2 for the first embodiment, when the data is written in the .P page, the problem of deterioration and loss that has been written to the lower page t of the same memory unit may occur. In the example of Fig. 2, if the power supply is disconnected while in the (10) upper page of the two-body, the data stored in the page 4 (lower page) sharing the same-hidden early can be deteriorated. 143117.doc •20· 201027555 When the data stored in the lower page (page 4) is invalid, the write operation will not cause any problems even if it fails, because the data that is lost to me is not valid. Similarly, when a write operation begins at the bottom of the page, a write failure will not result in the loss of valid data. This point constitutes a feature of the semiconductor memory device according to the present embodiment. As illustrated in FIG. 10, the semiconductor memory device 21 according to the second embodiment includes a host interface 2, a DRAM 3, a NAND flash ROM 22, and a controller. The 23° NAND flash ROM 22 includes an address conversion table 8, first. The storage unit 9, the second storage unit 10, the block management list u, and the block memory management list 24. The block memory management list 24 indicates that those pages in the block have stored therein data, as illustrated in FIG. In this figure, the data has been stored on page 4' of the block and page 5 and subsequent pages are not used. The block memory management list stores the memory states of all the blocks of the first storage unit 9 and the second storage unit 10. The φ block memory management list 24 exists only in the NAND flash ROM 22. However, the block memory management list 24 can be configured to be read from the NAND flash ROM 22 and temporarily stored in the dram 3 when the host device 6 issues a data write/read command to the semiconductor memory device 21. In this configuration, the tile memory management unit 27 described later in Control | § 23 updates the tile memory management list 24 temporarily stored in the DRAM 3. The block memory management list 24 in the NAND flash ROM 22 is updated at any given timing, such as when the semiconductor memory device 21 ceases its operation. The controller 23 includes a CPU 25, and according to an instruction executed by the CPU 25, 143117.doc - 21 · 201027555 CPU 25 includes a write/read instruction unit determination unit 26, a mobile unit 16, a block-controlled semiconductor storage device 21, The address conversion unit 14, the processing unit 17, and the block memory management unit 27. When receiving a data write request from the host device 6, the determining unit % determines whether there is a block in the block of the first storage unit 9 that a new data write will not cause a loss of (4) material, and if so, Make this block. The more specific & 'determination unit 26' determines whether there is a new material writer starting from the upper page and corresponding to the lower page of the upper page storing invalid data therein by using the address conversion table 8 and the block memory management list 24. Any block, or any block in which new material is written from the lower page. If there is, then the judging unit 26 identifies the block. Referring now to Fig. 12, the judgment method 4 employed by the judging unit 26 is explained. In this figure, "L" included in each block designates the lower page, and "U" included in each block designates the upper page. The first storage unit 9 of Figure 12 includes blocks Α to D. In blocks VIII to ,, new data is written from the lower page of the block, and thus this block can be used as a block for writing new data. Similarly, new data is written from the top page in block D, and the data stored in the corresponding lower page is invalid. Therefore, this block can be used as a block for writing new data. In Fig. 12, the judging unit 26 specifies the block 1), but it can replace the designated block A. Then, when a data write request is received from the host device 6, but when the block of the first storage unit 9 does not include any blocks in which new data writes will not result in loss of valid data, the mobile unit 16 will store The valid data in the block of the first storage unit 9 is moved to the block of the second storage unit 1〇. 143117.doc -22* 201027555 Block memory management unit 27 manages the block memory management list 24, or swap. The memory state of each page of the block _ of the first storage unit 9 and the second storage unit ίο. Next, in the semiconductor memory device 21 according to the present embodiment, the following: Fig. 13 explains a method of writing new data into the NAND flash. When the host device 6 issues a data write command to the semiconductor storage device 21, the data to be written supplied by the host device 6 is temporarily stored in the mDRAM 3. Then, the judgment unit 26 judges whether the block of the first storage unit 9 includes any block in which new data is written and will not cause loss of valid data (step more specifically, the judgment unit 26 judges whether or not new data is written. The data starting from the upper page and stored in the corresponding lower page is any block of invalid data, or whether there is any block in which new data is written from the lower page. When the judging unit 26 judges the block of the first storage unit 9 Including the new data write φ into the block that will not cause the loss of valid data (at step s3i, the judgment unit 26 recognizes the block. The write/read command unit 13 issues the data to the first - The data writer command in the block of the storage unit 9 that does not store the valid data (step S32) causes the f-writer operation to be performed on the block. The other aspect 'when the judging unit 26 judges the first storage unit 9 If the block does not include any block in which the new data writer will not cause the loss of the valid data (No at step S3i), the valid data in some blocks of the mobile unit_first storage unit 9 moves to the second bet. Deposit slip Meta_block (step 143117.doc • 23. 201027555 S33). In this step, it is preferred to move all valid data in the blocks so that no valid data is retained in the block after the move. If the second storage unit If one or more blocks are included, the valid data can be moved to the plurality of zones at one time, and the item of the valid data to be moved is preferably processed once for each block. Next, the address conversion unit 14 updates the information about moving to The address conversion table 8 of the valid data of the block of the second storage unit 10 causes the address conversion table 8 to indicate the position to which the valid data is moved (the block/page position in the second storage unit 1) (step S34) Next, the block management unit 17 moves the block to which the valid data of the second storage unit 1 has been moved to the list of the first storage unit 9, and moves the first storage unit 9 from the valid data. And the block in which the valid data is not currently stored is moved to the list of the second storage unit 10 (step S35). The number of blocks moved here is not limited. Thereafter, in step S32, the write/read command unit 13 issues Data The data is written into the block of the first storage unit 9 in which the valid data is not stored (that is, the block from which the valid data is moved), and thereby the data writing operation is performed on the block. Next, the tile memory management unit 27 updates the block memory management list 24, or in other words, the memory state of each of the blocks of the first storage unit 9 and the second storage unit (7) (step S36). Finally, the address conversion unit 14 updates the address conversion table 8 regarding the data written in the block so that the address conversion table 8 indicates the location to which the material is moved (block/page position of the first storage unit 9). (Step S37) The process of writing new data into the NAND flash ROM 22 is completed via the above step I431I7.doc -24- 201027555. In the semiconductor storage device according to the second embodiment, when the determination unit determines that the first storage unit does not include any of the blocks in which the data associated with the external address is not lost due to writing of new material, the external supply may be The data is newly written to the area where the data associated with the external address will not be lost. Therefore, when the number of data erasures is reduced, the effective data previously stored in the block to which the new data is to be written is prevented from deteriorating and becoming unreadable. In addition, the data writing speed can be increased. Further, in the semiconductor storage device according to the second embodiment, the judgment unit recognizes the block in which the valid data is not lost even if the write operation fails, as the block for newly writing the externally supplied material. This increases the selection of the data to be written to, while reducing the number of data movements by the mobile unit, thereby increasing the life of the rewrite. Those skilled in the art will readily appreciate additional advantages and modifications. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment; FIG. 2 is a diagram for explaining the structure of an MLCNAND flash ROM; FIG. 3 is a diagram illustrating a block management list; FIG. 5 is a diagram for explaining a judging method according to the first embodiment; 143117.doc • 25- 201027555 FIG. 6 is a diagram for explaining a data moving method according to the first embodiment. Figure 7 is a flowchart for explaining the data moving method according to the first embodiment, and Figure 8 is a flowchart of a procedure for writing new data into the NAND flash ROM according to the first embodiment; A flowchart of a program for writing new data into a NAND flash ROM according to a modified example; FIG. 10 is a block diagram of a semiconductor memory device according to a second embodiment; FIG. 11 is a block diagram illustrating a block memory according to a second embodiment. 1) of the volume management list, FIG. 12 is a diagram for explaining the determination method according to the second embodiment; and FIG. 13 is a procedure for writing new data to the nand flash ROM according to the second embodiment. Flow chart. [Main component symbol description] 1 Semiconductor storage device 2 Host interface 3 Dynamic random access memory (DRAM) 4 NAND flash read-only memory (ROM) 5 Controller 6 Host device 7 Write/read data 8 address Conversion Table 9 First Storage Unit 10 Second Storage Unit 143117.doc 201027555 11 Block Management Checklist
12 CPU 13 寫入/讀取指令單元 14 15 16 17 21 22 23 2412 CPU 13 Write/read command unit 14 15 16 17 21 22 23 24
位址轉換單元 判斷單元 移動單元 區塊管理單元 半導體儲存裝置 NAND 快閃 ROM 控制器 區塊記憶體管理清單Address conversion unit Judging unit Mobile unit Block management unit Semiconductor storage device NAND flash ROM controller Block memory management list
25 CPU 26 判斷單元 27 區塊記憶體管理單元25 CPU 26 Judgment Unit 27 Block Memory Management Unit
143117.doc -27-143117.doc -27-
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| TWI472918B (en) * | 2010-12-15 | 2015-02-11 | Toshiba Kk | Semiconductor storage device and method of controlling the same |
| US9189323B2 (en) | 2010-12-15 | 2015-11-17 | Kabushiki Kaisha Toshiba | Semiconductor storage device and method of controlling the same |
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| KR20100073971A (en) | 2010-07-01 |
| EP2200045A1 (en) | 2010-06-23 |
| JP2010146469A (en) | 2010-07-01 |
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| JP4551958B2 (en) | 2010-09-29 |
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| EP2200045B1 (en) | 2011-11-09 |
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| CN101763894A (en) | 2010-06-30 |
| KR101121698B1 (en) | 2012-02-28 |
| CN103151073A (en) | 2013-06-12 |
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