JP2008191855A - Semiconductor storage device and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further balance the load on each physical block of a nonvolatile memory. <P>SOLUTION: The semiconductor device distributes the update frequency of data to each segment by dividing a logic space within each segment while associating a logic address with a physical block so that the frequency of writing data from external equipment for each segment is balanced, and achieves wear leveling for balancing the load on each physical block. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a memory control method for equalizing a load on each physical block of a nonvolatile memory.

  Some recent semiconductor memory devices have a nonvolatile memory therein. In the nonvolatile memory, a data storage area is divided into a plurality of blocks, and data is written and erased for each block.

  In general, an upper limit is set for the number of times data is erased from a physical block included in a nonvolatile memory, and a physical block exceeding the upper limit is treated as a defective block that cannot store data. Then, when the number of defective blocks exceeds a predetermined number, such a nonvolatile memory is considered to have reached the end of its life due to the specifications on the product and cannot be used.

  As described above, when data is written or erased only to a specific physical block, and only the number of times the specific physical block is erased increases, the specific physical block becomes defective earlier than the other physical blocks. It becomes a block. When the number of defective blocks exceeds a predetermined number, the nonvolatile memory becomes unusable even though the number of times of erasure is small and there are still many physical blocks that can store data. There was a case.

  In order to solve this problem, for example, the following method (hereinafter referred to as the first method) has been proposed. That is, in the semiconductor memory device to which the first method is applied, the number of data erases is counted for each physical block, and the result is recorded in the erase management table and managed. Then, when the semiconductor storage device finds a physical block that has reached a predetermined specified number of times by referring to the erasure management table as appropriate, by referring to the number of erasures of all physical blocks described in the erasure management table, The physical block with the smallest erase count is identified. Next, the semiconductor memory device moves the data stored in the physical block that has reached the specified number of times to the physical block that has the smallest specified number of erasures. As described above, in this first method, it is possible to improve the usable period of the nonvolatile memory by equalizing the load on each physical block of the nonvolatile memory (so-called wear leveling). (See Patent Document 1).

JP 2003-203016 A

  By the way, the semiconductor memory device to which the first method is applied records the number of times of erasure (for example, 1000 times) for each physical block in the erasure management table. Thus, when performing wear leveling, it is necessary to execute a process of referring to the number of times of erasure of all physical blocks described in the erasure management table, and thus it is difficult to simplify the configuration.

  On the other hand, in the conventional semiconductor memory device, the following method (hereinafter referred to as the second method) is also employed. This second method can simplify the configuration of the semiconductor memory device without requiring an erasure management table or the like.

  12 and 13 are diagrams for explaining the second method. 12A to 12E, one segment SGX in the nonvolatile memory is shown in a simplified manner. Actually, this one segment SGX has, for example, 512 physical blocks BK (BK0, BK1,...), And each physical block BK can store, for example, 64 pages of data. (For example, one page corresponds to 2 [Kbyte]).

  In FIG. 12 and FIG. 13, the physical block BK storing data is shaded and the physical block BK subjected to the data wear leveling process is shaded, and the data wear leveling process is performed. The shading applied to the physical block BK with a larger number of times is made dense.

  In the semiconductor memory device to which the second method is applied, as shown in FIG. 12A, data supplied from the outside is sequentially transferred to empty physical blocks BK0, BK1,. Write.

  Thereafter, for example, update data for updating a part of the data of 64 pages stored in the physical block BK6 is supplied to the semiconductor memory device from the outside (FIG. 12B).

  At this time, the semiconductor storage device reads data that is not the update target (hereinafter referred to as “non-update target data”) from the data stored in the physical block BK6, and reads the non-update target data and this update. Data is written to an empty physical block BK21 secured in a predetermined portion in the segment SGX ((a) in FIG. 12C). Then, this semiconductor memory device erases all old data stored in the physical block BK6 ((b) in FIG. 12C). Thereafter, when update data for updating a part of the data stored in the physical block BK3 is supplied from the outside to the semiconductor memory device, the semiconductor memory device performs the same processing (FIG. 12D ) (C) and (d)) are executed.

  As described above, when the semiconductor memory device to which the second technique is applied updates, for example, a part of the data stored in the physical block BK6, all the data stored together in the physical block BK6 is changed. By moving to the physical block BK21, it is possible to avoid to some extent that data write processing and erasure are performed only on the physical block BK6.

  Next, the state of the data writing process in the second method will be described in detail with reference to FIG. Actually, such a semiconductor memory device has a table (hereinafter referred to as a logical physical conversion table) in which a logical address and a physical address assigned to a physical block BK are associated with each other. The storage location of each written data is managed.

  Here, in the state shown in FIG. 13A, for example, update data for updating a part of the data stored in the physical block BK0 corresponding to the logical address # 0 is supplied from the outside. The semiconductor memory device recognizes the physical address # 0 corresponding to the logical address # 0 with reference to the logical-physical conversion table. Then, the semiconductor memory device accesses the physical block BK0 based on the recognized physical address # 0, and among the data stored in the accessed physical block BK0, the non-update target data that is not the update target of the update data. And the read non-update target data and update data are written to the empty block BK3 in the segment SGX (FIG. 13B). Subsequently, the semiconductor memory device deletes all old data stored in the physical block BK0 and updates the logical-physical conversion table so that the logical address # 0 and the physical address # 3 of the physical block BK3 are associated with each other. .

  Thereafter, when update data for updating a part of data stored in the physical block BK3 corresponding to the logical address # 0 is supplied from the outside, the semiconductor memory device refers to the logical-physical conversion table. Thus, the physical address # 3 corresponding to the logical address # 0 is recognized. Then, the semiconductor memory device accesses the block BK3 based on the recognized physical address # 3, and among the data stored in the accessed physical block BK3, the non-update target data that is not the update target of the update data. The read-out non-update target data and the update data are written to the empty physical block BK6 in the segment SGX (FIG. 13C). Subsequently, the semiconductor memory device deletes all old data stored in the physical block BK3 and updates the logical-physical conversion table so that the logical address # 0 and the physical address # 6 of the physical block BK6 are associated with each other. .

  As described above, in the semiconductor memory device to which the second method is applied, for example, only data corresponding to the logical address # 0 is frequently updated, and data corresponding to the other logical addresses is almost updated. Otherwise, as shown in FIG. 13D, the physical block BK on which the wear leveling process is executed is fixed to some extent (in this case, the physical blocks BK0, BK3, BK6, BK10, BK13, BK19).

  As a result, in the nonvolatile memory, many physical blocks BK (so-called non-moving blocks) are generated in which the same data remains stored because the wear leveling process is not performed.

  When a large number of immovable blocks are generated in this way, the load on each physical block BK of the nonvolatile memory is biased, so it is difficult to improve the usable period of the nonvolatile memory. End up.

  As described above, the semiconductor memory device to which the second technique is applied does not need to hold the erasure management table or the like, and thus the configuration can be simplified as compared with the case where the first technique is applied. There is a problem that the load on each physical block BK cannot be made sufficiently uniform.

  The present invention has been made in consideration of the above points, and proposes a semiconductor memory device and a memory control method capable of making the load on each block of the nonvolatile memory more uniform with a simple configuration. is there.

  In order to achieve the above object, a semiconductor memory device according to the present invention includes a nonvolatile memory having a plurality of segments each having a predetermined number of physical blocks associated with data erasure processing information, and access from an external device. Memory control means for performing data write and / or read control on the non-volatile memory in response to a request, the memory control means being a part of physical space in the segment and two different logical spaces The physical block that associates and manages the first logical space and the second logical space and the physical block associated with the erase processing information indicating that the erase processing in the segment is not executed And data movement means for moving the stored data to another physical block in the segment.

  In order to achieve the above-described object, a memory control method according to the present invention includes a non-volatile memory having a plurality of segments each having a predetermined number of physical blocks associated with data erasure processing information. A memory control method for performing data write and / or read control on the non-volatile memory in response to an access request from an external device, comprising a part of the physical space in the segment and two different logics The first logical space and the second logical space which are spaces are managed in association with each other, and the erasure processing information indicating that the erasure processing in the segment is not executed is stored in the associated physical block. The data is moved to another physical block in the segment.

  According to the present invention, it is possible to realize the wear leveling process for distributing the data writing frequency to each segment and making the load on the physical block uniform with higher accuracy.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a semiconductor memory device 1 according to an embodiment to which the present invention is applied. The semiconductor memory device 1 is a card-type semiconductor memory device including a nonvolatile memory 2 including nonvolatile memories 2A, 2B,... And a controller 3 that performs control processing of the nonvolatile memory 2. The semiconductor memory device 1 corresponds to a Memory Stick (registered trademark), and data supplied from an external device such as a personal computer is written therein.

  In the controller 3, an MPU (Micro Processing Unit) 4 that controls memory control includes a register 5 including an instruction register, an ECC (Error Correcting Circuit) 6 that executes error correction processing, and the MPU 4 executes and develops a program. RAM (Random Access Memory) 7 and a data buffer 8 in which data to be read / written from / to the nonvolatile memory 2A are temporarily stored. The controller 3 also includes a clock generation unit 9 for generating a memory stick internal clock.

  A program for executing the processing operation according to the present embodiment is stored in a predetermined area of the nonvolatile memory 2, and the MPU 4 reads this program from the nonvolatile memory 2 and expands it in the RAM 7. Perform processing based on the program.

  The data buffer 8 is connected to the serial interface 11 and the parallel interface 12 via the bus 10. Data from an external device is sequentially input to the data buffer 8 via the lines DATA0 to DATA3 and the parallel interface 12, the line DATA0 and the serial interface 11, and the MPU 4 converts the data input to the data buffer 8 to the nonvolatile memory 2A. , 2B,...

  Further, power is supplied to the semiconductor memory device 1 via lines VSS and VCC. Further, the semiconductor memory device 1 determines whether or not the semiconductor memory device 1 is normally attached to the line SCLK to which a clock necessary for taking in data from the external device is input and the external device. For example, a line INS to which a signal for input is input and a line BS to which a signal for determining the direction of data supplied from an external device is input.

  The non-volatile memory 2 includes a plurality of non-volatile memories (non-volatile memories 2A, 2B,...).

  As shown in FIG. 2, the physical space of the nonvolatile memory 2A is composed of a plurality of physical blocks. Each physical block is composed of a plurality of pages. Each page is composed of data write or read units called a plurality of sectors (not shown).

  As shown in FIG. 3, the physical space of the nonvolatile memory 2A is an area where data is actually written, read, erased, etc., and a user data area having a plurality of segments each having a predetermined number of physical blocks, and The management area includes a logical physical conversion table for managing the physical block address and the logical block address in association with each other in the user data area. For example, a file system such as FAT (File Allocation Tables) is applied to the logical-physical conversion table.

  Note that data can be added to the physical block and the pages constituting the physical block of the nonvolatile memory 2A, but cannot be overwritten. In the nonvolatile memory 2A, data writing or reading is performed in units of sectors, and data is erased in units of blocks.

  The logical-physical conversion table is assigned to the logical block that constitutes the logical space that is a virtual space for performing processing such as data writing, reading, and erasing, and the physical address assigned to the physical block for each segment. The logical address is managed in association with it.

  In the semiconductor memory device 1, one segment has, for example, 512 physical blocks, and each physical block can store, for example, 64 pages of data (for example, one page is 2 [Kbyte]). Equivalent).

  The logical-physical conversion table includes a first logical space, which is two logical spaces, and a physical space composed of a predetermined number of physical blocks in each segment so that the frequency of writing data from the external device for each segment is uniform. Management is performed in association with the second logical space.

For example, physical space segment _{S 0,} S 1 having nonvolatile memory 2A, · · _·, if consisting of _{S n-1,} the physical this segment _{S 0, S 1, ···,} S n-1 has respectively The first logical space A _0a and the second logical space A _0b , the first logical space A _1a and the second logical space A _1b ,..., The first logical space A _{(n−1), respectively. ) A} and the second logical space A _{(n-1) b} are managed in association with each other. Data acquired from an external device, the logical space _{A 0a, A 1a, ···,} A (n-1) a, logical space _{A (n-1) b,} ···, A 1b, in the order of _{A 0b} Written.

  Each segment is a physical block that is applied to the data wear leveling process (hereinafter, wear leveling process) as a physical block that is not associated with two logical spaces (first logical space and second logical space). And a physical block applied to the data update process (hereinafter referred to as a data update block), and the load on the physical block is made uniform by the wear leveling process described later.

  FIG. 4 is a diagram for explaining an example of a logical address assignment method for this logical block.

  In this example, the physical space of the non-volatile memory 2A is composed of segment 0 consisting of physical blocks 0 to 9, segment 1 consisting of physical blocks 10 to 19, and segment 2 consisting of physical blocks 20 to 29. To do.

  Here, the data update blocks are the physical block 8, the physical block 18, and the physical block 28, and the wear leveling processing blocks are the physical block 9, the physical block 19, and the physical block 29.

  Here, for example, a physical block and a logical block to which an address M is assigned are described as a physical block M and a logical block M, respectively.

  The logical-physical conversion table manages the physical addresses and logical addresses assigned to the remaining physical blocks excluding the data update block and the wear leveling processing block among the physical blocks of each segment, one by one. .

  The logical-physical conversion table is for logical spaces corresponding to physical blocks 0 to 3, physical blocks 10 to 13, physical blocks 20 to 23, physical blocks 24 to 27, physical blocks 14 to 17, and physical blocks 4 to 7, respectively. In order, logical addresses 0 to 3, logical addresses 10 to 13, logical addresses 20 to 23, logical addresses 30 to 33, logical addresses 40 to 43, and logical addresses 50 to 53 are assigned. The logical-physical conversion table is a logical space in which logical addresses 0 to 3, logical addresses 10 to 13, logical addresses 20 to 23, logical addresses 30 to 33, logical addresses 40 to 43, and logical addresses 50 to 53 are associated with each other. The logical space 0, logical space 1, logical space 2, logical space 3, logical space 4, and logical space 5 are managed in order.

  Data acquired from the external device is written in the order of logical addresses 0 to 3, logical addresses 10 to 13, logical addresses 20 to 23, logical addresses 30 to 33, logical addresses 40 to 43, and logical addresses 50 to 53.

  FIG. 5 is a diagram showing the relationship between the physical space per segment managed by the logical-physical conversion table and the logical space corresponding to this physical space.

  The logical-physical conversion table manages the physical blocks constituting each segment in association with an erasure processing flag indicating whether or not data erasure processing has been performed. The MPU 4 sets the erase process flag associated with the physical block that has been erased to 1 and sets the erase process flag associated with the physical block that has not been erased to 0.

  Further, the logical-physical conversion table manages a wear leveling process flag indicating whether or not a wear leveling process, which will be described later, has been performed on the physical blocks constituting each segment. The MPU 4 sets the wear leveling processing flag to 1 for a physical block that has been subjected to wear leveling processing, and sets the wear leveling processing flag to 0 for a physical block that has not been subjected to wear leveling processing.

  Also, the logical-physical conversion table manages a physical block constituting each segment in association with a wear leveling processing flag indicating whether or not a later-described wear leveling processing is being processed. The MPU 4 sets the wear leveling process flag to 1 when the wear leveling process starts, and sets the wear leveling process flag to 0 when the wear leveling process ends.

  Also, the logical-physical conversion table has a data update block address for the physical block a + 8 that is a data update block, and a wear leveling block address for the physical block a + 9 that is a wear leveling block. The wear leveling process progress information indicating the progress of the wear leveling process and the wear leveling process flag are managed in association with each other.

  The erasing process flag, the wear leveling process flag, and the wear leveling process in progress flag are stored in the management area as management information. Further, the data update block address, the wear leveling block address, and the wear leveling process progress information are also stored in the management area.

  As described above, in the semiconductor memory device 1, the erasing process flag, the wear leveling process flag, and the wear leveling process in progress flag are associated with each physical block and stored as management information in the management area. Both the flag and the wear leveling in-process flag are information only indicating whether or not the data has been processed, and the amount of information can be one bit (0 or 1) per block, so the number of erasures and the like is managed. Compared to the conventional configuration, a simpler configuration can be achieved.

  Of the physical blocks constituting each segment, physical addresses assigned to physical blocks other than the data update block and the wear leveling processing block are managed in association with the logical addresses set by the above-described method. For example, the physical address a, the physical address a + 1, the physical address a + 2, and the physical address a + 3 are managed in association with the logical address m, the logical address m + 1, the logical address m + 2, and the logical address m + 3, respectively, and the physical address a + 4 and the physical address a + 5. The physical address a + 6 and the physical address a + 7 are managed in association with the logical address n, the logical address n + 1, the logical address n + 2, and the logical address n + 3, respectively. Here, the logical space to which the logical address m, the logical address m + 1, the logical address m + 2, and the logical address m + 3 are respectively assigned is managed as a logical space X. The logical address n, the logical address n + 1, the logical address n + 2, and the logical address The logical spaces to which n + 3 are respectively assigned are collectively managed as a logical space Y.

  In general, data managed by a file system such as FAT is updated in ascending order of logical addresses. Here, when logical addresses are assigned in order according to the physical block arrangement order, even if data wear leveling processing is performed for each segment, it is erased for physical blocks included in a segment with a small number such as segment 0. The accompanying load is concentrated, and the consumption time is reached earlier than the physical blocks of other segments.

  Normally, data is not written to the full size with respect to the size of the nonvolatile memory. In the nonvolatile memory 2A, when the erase process is frequently performed on the physical space corresponding to the logical space 0 to 2 as shown in FIG. Since the erasure process is not performed on the physical space, a difference occurs in the number of erasures between these two physical spaces, and the wear leveling process becomes effective. In addition, when data is stored in ascending order of logical addresses and the data is not semi-permanently updated, that is, when data is stored as a read-only file, the data written in the physical blocks corresponding to the logical spaces 0 to 2 Therefore, the erasure process is not performed and the address spaces of the logical spaces 3 to 5 are frequently updated. Even in this case, there is a difference in the number of erasures for each physical block in the segment, and wear leveling processing becomes effective.

  As described above, in the semiconductor memory device 1, specifically, the data write frequency from the external device for each segment is made uniform so that the data write frequency is distributed in the physical space of the nonvolatile memory 2 </ b> A. By associating the logical address with the physical address, the load on the physical block can be made uniform with higher accuracy by the wear leveling process described later.

  In a predetermined segment constituting the nonvolatile memory 2A, the MPU 4 performs a data update process on the physical block to which data has been written. At this time, the MPU 4 sets the erasure processing flag to 1 as shown in FIG. 5 for the physical block that has undergone the erasure processing. When the erasure process is performed again on the physical block associated with the erasure process flag 1, the MPU 4 performs a wear leveling process for equalizing the load on the nonvolatile memory 2 associated with the data erasure operation. Start.

  In addition, the MPU 4 sets the erasure processing flag to 0 for a physical block that has not been erased in the segment. The MPU 4 searches for physical blocks associated with the erasure processing flag 0 in descending order of logical addresses in a physical space corresponding to a logical space with a low data update frequency. Then, the MPU 4 performs the wear leveling process using the physical block associated with the erasure process flag 0.

  FIG. 6 is a diagram for explaining an example of the data update process accompanying the data write process for each segment. As shown in FIG. 6A, when an external device makes a data write request to a physical block a corresponding to a logical address m (not shown), for example, the MPU 4 refers to the logical physical conversion table. As a result, the physical address a corresponding to the logical address m is recognized. Further, the MPU 4 recognizes the physical block a + 8 that is a data update block. Then, the MPU 4 writes data from the external device to the physical block a + 8, and updates the logical-physical conversion table so as to associate the physical address a + 8 with the logical address m as shown in FIG. The data stored in a is erased, and the logical-physical conversion table is updated with the physical block a as a data update block. Further, the MPU 4 updates the management information stored in the management area so as to set the erasure processing flag associated with the physical block a to 1.

  FIG. 7 is a diagram for explaining an example of the wear leveling process for each segment. After a data update process, when a data write request to the physical block a + 8 corresponding to the logical address m is made again, if an update process similar to the update process shown in FIG. 6 is performed, the physical block Since only data a and physical block a + 8 are erased, the load on physical block a and physical block a + 8 is greater than other physical blocks. Therefore, when a data write request is again made to the physical block corresponding to the logical address m, for example, by performing wear leveling processing as shown in FIGS. The fixing of physical blocks to be processed is suppressed, and the load on the physical blocks in the segment is made uniform.

  For example, when the erasure processing flag 0 is associated with the physical block a + 7, the data stored in the physical block a + 7 is copied to the physical block a + 9 that is a wear leveling processing block.

  The logical-physical conversion table updates the management information so that the physical block a + 9 is associated with the logical address n + 3, the physical block a + 7 as the data update block, and the physical block a as the wear leveling processing block. Update management information.

  After the data update process subjected to such data wear leveling process, the same data update process as described above is performed in the physical block a + 8 and the physical block a + 7.

  In this wear leveling process, the MPU 4 searches for physical blocks associated with the erasure process flag 0 in descending order of logical addresses. For example, as shown in FIG. 8, the MPU 4 searches the physical block associated with the erasure processing flag 0 in the segment in the descending order of the logical address as the search target block. In the example shown in FIG. 8, in segment 0, the physical block a + 6 corresponding to the logical address n + 2 of the logical space 5 is the physical block used for the wear leveling process.

  The MPU 4 ends the wear leveling process when the wear leveling process flags associated with the physical blocks included in the segment 0 are all set to 1.

  The MPU 4 performs a wear leveling process on one page of data stored in a physical block associated with an erasure processing flag 0 with a low data update frequency in a data update process corresponding to a normal write process on a storage medium. The wear leveling process for copying to the block is performed, and the data update process is terminated. Then, when the next data update process occurs, the MPU 4 performs a wear leveling process of copying one page of subsequent data to the wear leveling process block, and ends the data update process. As a result, a decrease in performance in the semiconductor memory device 1 is suppressed.

  Further, when the wear leveling process is performed on all the physical blocks in the segment, the semiconductor memory device 1 sets the erasure process flag, the wear leveling process flag, and the wear leveling process flag that are associated with all the physical blocks. Is changed from 1 to 0, and the wear leveling process is terminated.

  FIG. 9 is a flowchart for explaining the processing operation of the data update processing of the physical block in each segment in the nonvolatile memory 2A.

  In step S1, data is written from an external device to the nonvolatile memory 2 included in the semiconductor memory device 1.

  In step S2, the MPU 4 included in the semiconductor storage device 1 refers to the logical-physical conversion table stored in the management area of the nonvolatile memory 2A, and determines the physical block corresponding to the logical address to be updated in the segment. get.

  In step S3, the MPU 4 acquires a data update block.

  In step S4, the MPU 4 writes the data acquired from the external device into the data update block.

  In step S5, the MPU 4 updates the management information of the logical-physical conversion table with the data update block as a physical block corresponding to the logical address to be updated.

  In step S6, the MPU 4 erases the data stored in the physical block corresponding to the logical address to be updated.

  In step S7, the MPU 4 updates the management information in the logical-physical conversion table using the physical block corresponding to the logical address to be updated as a data update block.

  In step S7, the logical-physical conversion table sets the erasure processing flag associated with the physical block in which the data erasure processing has been performed in step S6 to 1. When the erasure process is performed again on the physical block associated with the erasure process flag 1, the MPU 4 determines that the number of erasures is larger than that of other physical blocks in the segment, and accompanies the data erasure operation. A wear leveling process for equalizing the load on the nonvolatile memory 2A is started.

  In step S8, the MPU 4 performs a physical space wear leveling process. Here, the details of the processing operation of the wear leveling process in step S8 will be described with reference to the flowcharts of FIGS. 10A and 10B.

  In step S20, the MPU 4 starts the wear leveling process in the segment.

  In step S21, the MPU 4 confirms whether the wear leveling process is currently being performed by confirming whether the wear leveling process flag is 1 or 0. In this step S21, if the wear leveling processing flag is 1, the process proceeds to step S25 following A, and if it is 0, the process proceeds to step S22.

  In step S22, when an erasure process associated with a data update process by writing is performed on a specific physical block in the segment, the MPU 4 determines whether the erasure process flag associated with this physical block is 0 or 1. Check if it exists. If the erasure processing flag is 0 in step S22, the process proceeds to step S27. In step S27, the MPU 4 sets the erasure processing flag to 1 and proceeds to step S44 following D, and ends a series of wear leveling processing.

  On the other hand, if the erasure processing flag is 1 in step S22, the process proceeds to step S23. In step S23, the MPU 4 sets the wear leveling processing flag to 1, and then sets the wear leveling processing flag of the physical block that has been erased by writing data in step S24 to 1 and proceeds to step S28.

  In the semiconductor memory device 1, for example, when other data processing such as data writing processing is performed, the data writing processing is divided into physical block units, and wear leveling processing is performed every time the writing processing in physical block units is completed. .

  In step S25, the MPU 4 confirms whether or not an erasure process by writing has occurred in the physical block for which the wear leveling process is performed. In this step S25, when the MPU 4 confirms that the erasure process by the write has occurred in the physical block that performs the wear leveling process, the process proceeds to step S43, and the erase process by the write occurs in the physical block that performs the wear leveling process. If it is confirmed that the process has not been performed, the process proceeds to step S26.

  In step S26, the MPU 4 wears the wear leveling process at any time point in case 1 in which the processes in steps S28 to S34 are performed, case 2 in which the processes in steps S35 to S37 are performed, and case 3 in which the processes in steps S38 to S42 are performed. Based on the wear leveling process progress information indicating whether the process is in progress, the process proceeds to any of the process steps of case 1, case 2, and case 3. The wear leveling process progress information is set in case 1, case 2, or case 3 so as to indicate which processing step is to be continued.

  When the process proceeds to case 1 after step S26, in step S28 following B, the MPU 4 searches for the physical block of the wear leveling processing flag 0 in the segment.

  In step S29, the MPU 4 checks whether or not the wear leveling processing flag associated with all the physical blocks in the segment is 1. In this step S29, when the MPU 4 confirms that the wear leveling processing flag associated with all the physical blocks in the segment is 1, that is, there is no physical block to which the wear leveling processing flag 0 is attached. Proceeding to step S30, if it is confirmed that there is a physical block with the erasure processing flag 0, the process proceeds to step S33.

  In step S30, the MPU 4 sets the wear leveling processing flag to 0 for all physical blocks in the segment, and proceeds to step S31.

  In step S31, the MPU 4 sets the erasure processing flag to 0 for all physical blocks in the segment, and proceeds to step S32.

  In step S32, the MPU 4 sets the wear leveling processing flag to 0, and proceeds to step S44 following C.

  In step S33, the MPU 4 sets the wear leveling process progress information in case 2 and proceeds to step S34.

  In step S34, the MPU 4 associates the address of the wear leveling target physical block with the wear leveling block address.

  When proceeding to case 2 after step S26, in step S35, the MPU 4 copies the data for one page stored in the physical block associated with the erasure processing flag 0 to the wear leveling processing block.

  In step S36, it is confirmed whether or not data has been copied for one physical block. In this step S36, if the MPU 4 confirms that the data for one physical block has been copied, the process proceeds to step S37. If the MPU 4 confirms that the data for one physical block has not been copied, Proceed to step S44.

  In step S37, the MPU 4 sets the wear leveling process progress information in case 3, and proceeds to step S44. In this case 2, the physical block data is copied page by page in step S35. However, if 64 pages of data are stored in each physical block, a series of wear leveling processing via this case 2 is performed. Will be repeated 64 times.

  When the process proceeds to case 3 after step S26, in step S38, the MPU 4 erases the data stored in the physical block to which the wear leveling processing flag 0 is attached.

  In step S39, the MPU 4 sets the wear leveling process progress information to case 1 and proceeds to step S40.

  In step S40, the MPU 4 sets the erasure processing flag to 1, and proceeds to step S41.

  In step S41, the MPU 4 sets the wear leveling processing flag to 1, and proceeds to step S42.

  In step S42, the MPU 4 clears the setting of the physical address set in the wear leveling processing block. This wear leveling process ends when the wear leveling process flag is set to 1 in all physical blocks constituting the segment.

  In step S43, the MPU 4 interrupts the wear leveling process. Details of the process of step S43 will be described with reference to the flowchart of FIG.

  In step S430, the MPU 4 starts the wear leveling interruption process in the segment.

  In step S431, the MPU 4 confirms wear leveling process progress information. When the process proceeds to case 2 or case 3 after step S26, the process proceeds from step S431 to step S432, and the MPU 4 erases the data stored in the physical block of the wear leveling block address, and then proceeds to step S433. When the process proceeds to case 1 after step S26, the process proceeds from step S431 to step S433.

  In step S433, the MPU 4 sets the erasure processing flag to 1.

  In step S434, the MPU 4 sets the wear leveling processing flag to 1.

  In step S435, the MPU 4 clears the setting of the physical address set in the wear leveling processing block.

  In step S436, the MPU 4 sets the wear leveling process progress information in case 1.

  In step S437, the MPU 4 ends the wear leveling interruption process.

  In step S44, a series of wear leveling processing is terminated.

  Returning to FIG. 9, in step S9, the MPU 4 stores the updated management information in the management area.

  In step S10, the MPU 4 ends a series of data update processing.

  As described above, in the semiconductor memory device 1, specifically, the data write frequency from the external device for each segment is made uniform so that the data write frequency is distributed in the physical space of the nonvolatile memory 2 </ b> A. By associating the physical address with the logical address, the wear leveling process accompanying the data update process can be realized with higher accuracy. Thereby, in the semiconductor memory device 1, it is possible to make the load on each physical block of the nonvolatile memory more uniform.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, in the above-described embodiment, the MPU 4 is applied as a means for executing a series of wear leveling processes. However, the present invention is not limited to this, and various other configurations can be applied.

  The present invention can be used for a semiconductor memory device having a nonvolatile memory.

It is a figure which shows the structure of the semiconductor memory device in this Embodiment. It is a figure which shows schematic structure of the non-volatile memory with which a semiconductor memory device is provided. It is a figure which shows schematic structure of the non-volatile memory with which a semiconductor memory device is provided. 3 is a diagram for explaining an example of a method for assigning a logical address to a logical block in the semiconductor memory device 1; FIG. It is a figure which shows the relationship between the physical space per segment which a logical physical conversion table manages, and the logical space corresponding to this physical space. It is a figure for demonstrating an example of the update process of data. It is a figure for demonstrating an example of a wear leveling process. It is a figure for demonstrating an example of the method of searching the physical block to which the deletion process flag 0 was attached | subjected within the segment. It is a flowchart for demonstrating the processing operation | movement of the update process of the physical block in the segment of a non-volatile memory. It is a flowchart for demonstrating the detail of the processing operation | movement of a wear leveling process. It is a flowchart for demonstrating the detail of the processing operation | movement of a wear leveling process. It is a flowchart for demonstrating operation | movement of the interruption process of a wear leveling process. It is a figure for demonstrating an example of the conventional write processing. It is a figure for demonstrating an example of the conventional write processing.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 2 Non-volatile memory, 3 Controller, 4 MPU, 5 Register, 6 ECC, 7 RAM, 8 Data buffer, 9 Clock generation part, 10 Bus, 11 Serial I / F, 12 Parallel I / F

Claims (6)

A non-volatile memory having a plurality of segments each having a predetermined number of physical blocks associated with data erasure processing information;
Memory control means for performing data write and / or read control on the nonvolatile memory in response to an access request from an external device,
The memory control means includes
Logical-physical conversion means for managing a part of the physical space in the segment in association with two different logical spaces, the first logical space and the second logical space;
Data moving means for moving the data stored in the physical block associated with the erasure processing information indicating that the erasure processing in the segment is not executed to another physical block in the segment; A semiconductor memory device. When the physical space of the non-volatile memory is composed of segments S ₀ , S ₁ ,..., S _n−1 , the logical-physical conversion means has the segments S ₀ , S _{1 ,.} the physical _{space 1} has respectively, each of the first logical space _{a 0a} and second logical space _{a 0b,} the first logical space _{a 1a} and the second logical space _a 1b, · · ·, a first logic Managed in association with the space A _{(n-1) a} and the second logical space A _{(n-1) b} ,
The data acquired from the external device includes logical spaces A _0a , A _1a ,..., A _{(n−1) a} , logical spaces A _{(n−1) b} ,..., A _1b , A _0b . The semiconductor memory device according to claim 1, which is written in order.   The data moving means performs the data moving process when the data erasing process is executed again for the physical block associated with the erasing process information indicating that the data erasing process has been executed. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is started.   The data movement means executes the data movement processing until it is indicated that data erasure processing has been executed in all the erasure processing information associated with the physical block. The semiconductor memory device according to Item 1.   When it is indicated that the data erasure process is executed in all the erasure process information, all the erasure process information is updated to indicate that the data erasure process is not executed. The semiconductor memory device according to claim 4. Used in a semiconductor storage device including a nonvolatile memory having a plurality of segments each having a predetermined number of physical blocks associated with data erasure processing information, and in response to an access request from an external device, A memory control method for performing writing and / or reading control,
A part of the physical space in the segment is managed in association with the first logical space and the second logical space which are two different logical spaces, and the erasure processing in the segment is not executed. A memory control method, comprising: moving data stored in a physical block associated with the erasure processing information to another physical block in the segment.

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