TW200943070A - Memory device with network on chip methods, apparatus, and systems - Google Patents

Memory device with network on chip methods, apparatus, and systems

Info

Publication number
TW200943070A
TW200943070A TW098104986A TW98104986A TW200943070A TW 200943070 A TW200943070 A TW 200943070A TW 098104986 A TW098104986 A TW 098104986A TW 98104986 A TW98104986 A TW 98104986A TW 200943070 A TW200943070 A TW 200943070A
Authority
TW
Taiwan
Prior art keywords
interface device
systems
memory device
network
processor module
Prior art date
Application number
TW098104986A
Other languages
Chinese (zh)
Other versions
TWI539288B (en
Inventor
Joe M Jeddeloh
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200943070A publication Critical patent/TW200943070A/en
Application granted granted Critical
Publication of TWI539288B publication Critical patent/TWI539288B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Multi Processors (AREA)

Abstract

Apparatus, method and systems are provided such as those that can include a processor module, an interface device disposed above or below the processor module, the interface device including a plurality of routing elements, at least one memory device disposed above or below the interface device and including a plurality of memory arrays, the plurality of memory arrays coupled to the interface device using a plurality of interconnects provided in vias provided in at least one of the memory device and the interface device. In addition, the interface device communicatively can couple the plurality of memory arrays to the processor module using the plurality of routing elements and the interconnects.
TW098104986A 2008-02-19 2009-02-17 Apparatus, system and method for improving interconnecting memory devices TWI539288B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/033,684 US9229887B2 (en) 2008-02-19 2008-02-19 Memory device with network on chip methods, apparatus, and systems

Publications (2)

Publication Number Publication Date
TW200943070A true TW200943070A (en) 2009-10-16
TWI539288B TWI539288B (en) 2016-06-21

Family

ID=40956162

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098104986A TWI539288B (en) 2008-02-19 2009-02-17 Apparatus, system and method for improving interconnecting memory devices

Country Status (8)

Country Link
US (1) US9229887B2 (en)
EP (1) EP2257881B1 (en)
JP (1) JP5610293B2 (en)
KR (1) KR101543488B1 (en)
CN (2) CN103761204B (en)
SG (1) SG188133A1 (en)
TW (1) TWI539288B (en)
WO (1) WO2009105204A2 (en)

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Also Published As

Publication number Publication date
CN103761204A (en) 2014-04-30
US20090210600A1 (en) 2009-08-20
WO2009105204A2 (en) 2009-08-27
JP2011512598A (en) 2011-04-21
WO2009105204A3 (en) 2009-10-15
KR101543488B1 (en) 2015-08-10
TWI539288B (en) 2016-06-21
CN103761204B (en) 2017-03-01
CN101946245A (en) 2011-01-12
EP2257881A4 (en) 2011-08-31
US9229887B2 (en) 2016-01-05
KR20100115805A (en) 2010-10-28
JP5610293B2 (en) 2014-10-22
EP2257881A2 (en) 2010-12-08
SG188133A1 (en) 2013-03-28
CN101946245B (en) 2014-01-08
EP2257881B1 (en) 2015-08-12

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