JPS61196565A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS61196565A JPS61196565A JP3707585A JP3707585A JPS61196565A JP S61196565 A JPS61196565 A JP S61196565A JP 3707585 A JP3707585 A JP 3707585A JP 3707585 A JP3707585 A JP 3707585A JP S61196565 A JPS61196565 A JP S61196565A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- integrated circuit
- type
- stage
- metal electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 abstract description 28
- 239000002184 metal Substances 0.000 abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000000873 masking effect Effects 0.000 abstract description 4
- 239000000370 acceptor Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 238000004364 calculation method Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路に係り、半導体層上にｎ形層、
ｐ形層を形成し、かつ電極を設けることにより構成さ
れる半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and includes an n-type layer on a semiconductor layer,
The present invention relates to a semiconductor integrated circuit formed by forming a p-type layer and providing electrodes.
従来の技術 第１図は従来の半導体集積回路の断面を示す図である。Conventional technology FIG. 1 is a diagram showing a cross section of a conventional semiconductor integrated circuit.
同図中、１はｎ形のシリコン単結晶棒より切り出したウ
ェーハであり、ウェーハ１の表面部分にはｐ形Ｐ３ａ
、３ｂ 、３ｃが形成され、更にｐ形層３ａ内にｎ形層
４ａ 、４ｂが形成されている１、上記のウェーハ１上
には酸化膜（ＳｉＯ２）２が成長形成され、ドレイン、
ソースとなるｐ形１ｉ１３ｂ 、３ｃ及ヒｎ形Ｆ）４ａ
、４ｂには直接アルミ等の金属電極５ａ、５ｂ、５ｃ
が蒸着され、また酸化膜２上にゲートとなる金属電極６
ａ 、 ６ｂが蒸着形成される。上記の電極５ａを接地
し、電極５ｃ１．：電源−ＶＤＤを供給して、電極６ａ
及び６ｂを入力端子、電極５ｂを出力端子とするコンプ
リメンタ！ＪＭＯ８（Ｃ−ＭＯＳ）ｌｉｌ路がｍ成され
る。このようなＣ−ＭＯ８Ｉ造のＦＥＴ、 トランジ
スタ、拡散抵抗等による抵抗素子、ＰＮ接合容ｊ１９に
よる各階素子を組合せることにより半導体集積回路が構
成されている。In the figure, 1 is a wafer cut from an n-type silicon single crystal rod, and the surface portion of wafer 1 has p-type P3a.
, 3b, 3c are formed, and n-type layers 4a, 4b are further formed in the p-type layer 3a. 1. An oxide film (SiO2) 2 is grown on the wafer 1, and the drain,
Source p type 1i13b, 3c and h type F) 4a
, 4b are directly connected to metal electrodes 5a, 5b, 5c such as aluminum.
is deposited on the oxide film 2, and a metal electrode 6 serving as a gate is formed on the oxide film 2.
a, 6b are formed by vapor deposition. The above electrode 5a is grounded, and the electrode 5c1. : Supplying the power source -VDD, the electrode 6a
And a complementer with 6b as an input terminal and electrode 5b as an output terminal! JMO8 (C-MOS) lil path is formed. A semiconductor integrated circuit is constructed by combining such a C-MO8I FET, a transistor, a resistance element such as a diffused resistor, and each level element such as a PN junction capacitor j19.
発明が解決しようとする問題点
従来の半導体集積回路はウェーハ１の一方の表面上に平
面的に構成されており、その回路集積密度も限界に近付
いている。このような半導体装置回路の一つとしてマイ
クロプロセッサがあるが、従来においては１チツプに１
個のマイクロプロセッサが構成されているだけであり、
例えば１ワード３２ビツトのデータを３２個のマイクロ
プロセッサで並列処理して超高速演算を行なうような場
合、マイクロプロセッサの集積回路チップが３２個必要
となり、配線基板上の占有面積が大となる等の問題点が
あった。Problems to be Solved by the Invention Conventional semiconductor integrated circuits are constructed in a planar manner on one surface of a wafer 1, and their circuit integration density is approaching its limit. A microprocessor is one of these semiconductor device circuits, but conventionally, one chip has one
It consists of just one microprocessor,
For example, if one word of 32 bits of data is processed in parallel by 32 microprocessors to perform ultra-high-speed calculations, 32 microprocessor integrated circuit chips are required, which increases the area occupied on the wiring board. There was a problem.
また、互いに基準電圧が異なる（２”−１）個（ただし
、ｍは正の整数）のコンパレータによりＡ／Ｄ変換を行
なう並列型のＡ／Ｄ変換器の如き回路では、出力ディジ
タル信号のビット数（ｉ ）が大となるにつれてコンパ
レータの数が指数関数的に増大し、従来の平面的な半導
体集積回路では１チツプ上に構成できないことがある等
の問題点があった。In addition, in a circuit such as a parallel A/D converter that performs A/D conversion using (2"-1) comparators with different reference voltages (where m is a positive integer), the bits of the output digital signal As the number (i) increases, the number of comparators increases exponentially, and there are problems in that conventional planar semiconductor integrated circuits may not be able to be constructed on one chip.
そこで、本発明は集積回路を複数段構成にすることによ
り、上記の問題点を解決した半導体集積回路を提供する
ことを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit that solves the above problems by configuring the integrated circuit in multiple stages.
問題点を解決するための手段
本発明においては、半導体層の一面上のｎ形層ｎ形層及
び電極により構成される一の段の集積回路を複数段重畳
している。Means for Solving the Problems In the present invention, a plurality of stages of integrated circuits constituted by an n-type layer and an electrode on one surface of a semiconductor layer are stacked.
作用
本発明においては、半導体層の一面上に構成される一の
段の集積回路が複数段重畳されている。Operation In the present invention, a plurality of stages of one stage of integrated circuits configured on one surface of a semiconductor layer are stacked.
これによって単位面積当りの回路集積度が複数倍となる
。This increases the degree of circuit integration per unit area by several times.
実施例
第３図は本発明回路の製造過程の一実施例の断面を示す
図である。同図中、第２図と同一部分には同一符号を付
し、その説明を省略する。Embodiment FIG. 3 is a cross-sectional view of an embodiment of the manufacturing process of the circuit of the present invention. In this figure, the same parts as in FIG. 2 are designated by the same reference numerals, and their explanations will be omitted.
第３図において、金属電極５ａ〜５ｃ 、 ５ａ 。In FIG. 3, metal electrodes 5a to 5c, 5a.
６ｂの蒸着形成後、酸化膜（Ｓｉ ０２ ）２を再度成
長させ、酸化膜２により金属電極５ａ〜５ｃ。After the vapor deposition of 6b, the oxide film (Si 02 ) 2 is grown again, and the oxide film 2 forms the metal electrodes 5a to 5c.
６ａ 、６ｂ全体を被膜、する。この後、例えばエピタ
キシャル成長により０形シリコン単結晶のｎ形層７が形
成される。ここで、ウェーハ１をシリコン単結晶棒より
切り出す際に、第４図に示す如くウェーハ１の一部に凸
部１ａを設けておき、つ工−ハ１上に金属電極を被覆す
る酸化膜２を形成した後、更に例えば化学気相沈積（Ｃ
ＶＤ）法によってｎ形の多結晶シリコン層７ａを形成す
る。次に多結晶シリコン層７ａの凸部１ａに接触する部
分から凸部１ａより一面する方向に順次レーザ光を移動
しつつ照射し、多結晶シリコンを溶解することによって
凸部１ａを種としたｎ彫型結晶シリコンか７を形成する
ことが可能である。6a and 6b are entirely coated. Thereafter, an n-type layer 7 of 0-type silicon single crystal is formed, for example, by epitaxial growth. Here, when the wafer 1 is cut out from a silicon single crystal rod, a convex portion 1a is provided in a part of the wafer 1 as shown in FIG. After forming, further chemical vapor deposition (C
An n-type polycrystalline silicon layer 7a is formed by the VD method. Next, the polycrystalline silicon layer 7a is irradiated with laser light while moving sequentially from the part that contacts the convex part 1a in a direction facing the convex part 1a, melting the polycrystalline silicon and using the convex part 1a as a seed. It is possible to form a sculpted crystal silicon layer 7.
上記の如くして形成されたｎ形層７の表面に酸化膜１０
を成長させ、この酸化膜１０をマスキングにより一部の
み除去する。この酸化膜除去部分より７クセプタの拡散
を行なってドレイン、ソースとなるｐ形層８ａ、８ｂ、
８ｃが形成される。An oxide film 10 is formed on the surface of the n-type layer 7 formed as described above.
is grown, and only a portion of this oxide film 10 is removed by masking. From this oxide film removed part, seven receptors are diffused to form p-type layers 8a, 8b, which become drains and sources.
8c is formed.
この後、同様のマスキング及び拡散によりｐ形層８ａ内
にｎ形１ｆｉ９ａ 、９ｂが形成される。次に、金属電
極５ａ上部のみを開口したマスクを使用して、金属電極
５ａ上部のｎ形層及び酸化膜２を除去し、これによって
孔１１が形成される。孔１０の側壁には酸化１１！１２
が成長形成されて酸化膜１０に連続し一体化する。更に
ｐ形層８ｂ 、 ８ａ間、ｎ形層９ａ 、９ｂ間のゲー
ト部分の酸化膜がマスキングにより除去されて、ここに
清浄で絶縁性の良いゲート酸化膜が成長形成される。こ
の後金属電極５ａ及びｐ形層３ｂ、８ｃ、ｎ形層９ａ９
ｂ上の酸化膜が除去されてアルミ等の金属が蒸着され、
金属電極１３ａ、１３ｂ、１３ｃ及び金属電極１４ａ、
１４ｂが形成される。この後電極配線部以外の不要部分
の金属膜が除去される。上記の金属蒸着時に孔１１の酸
化膜１２上にも金属が蒸着されるため、金属電極５ａと
１３ａとは導通接続される。Thereafter, n-type layers 1fi9a and 9b are formed in p-type layer 8a by similar masking and diffusion. Next, using a mask with an opening only above the metal electrode 5a, the n-type layer and oxide film 2 above the metal electrode 5a are removed, thereby forming the hole 11. Oxidation 11!12 on the side wall of hole 10
is grown to continue and be integrated with the oxide film 10. Further, the oxide film in the gate portion between the p-type layers 8b and 8a and between the n-type layers 9a and 9b is removed by masking, and a clean gate oxide film with good insulation is grown there. After that, the metal electrode 5a, the p-type layers 3b, 8c, and the n-type layer 9a9
The oxide film on b is removed and metal such as aluminum is deposited,
Metal electrodes 13a, 13b, 13c and metal electrode 14a,
14b is formed. Thereafter, unnecessary portions of the metal film other than the electrode wiring portion are removed. During the metal deposition described above, metal is also deposited on the oxide film 12 in the hole 11, so that the metal electrodes 5a and 13a are electrically connected.
上記と同様にして金属電極１３ａ〜１３Ｃ２１４ａ、１
４ｂ全体を成長させた酸化膜１０で彼覆し、その上にシ
リコン単結晶のｎ形層を形成して第３段の回路が構成さ
れ、以下１ｉ１様にしてｎ（ｎは正の整数）段の回路が
構成される。Metal electrodes 13a to 13C214a, 1 in the same manner as above
The third stage circuit is constructed by covering the entire oxide film 10 with a grown oxide film 10 and forming an n-type silicon single crystal layer thereon. A circuit is constructed.
ここで、ウェーハ１上には複数個の集積回路が構成され
るが、各集積回路の周縁部は第５図（Ａ）に示す如く、
第１段２０に比して第２段２２の面積が小となるよう加
工され、同様に第ｎ段２４に比して第ｎ−１段の面が小
とされる。ただし、第５図（△）に示すものは第１図示
と同様２段構成のものである。第１段２０上の電極２１
ａ〜２１ｎ夫々は金属電極５ｂ、５ｃ、６ａ等の配線を
引き出したものであり、第２段２２上の電極２３ａ〜２
３ｎ夫々は金属電極１３ａ、１３ｂ、１３ｃ。Here, a plurality of integrated circuits are formed on the wafer 1, and the peripheral portion of each integrated circuit is as shown in FIG. 5(A).
The area of the second stage 22 is processed to be smaller than that of the first stage 20, and similarly, the surface of the (n-1)th stage is made smaller than that of the nth stage 24. However, the one shown in FIG. 5 (△) has a two-stage configuration similar to that shown in the first drawing. Electrode 21 on the first stage 20
a to 21n are wirings of metal electrodes 5b, 5c, 6a, etc., respectively, and electrodes 23a to 2 on the second stage 22.
3n are metal electrodes 13a, 13b, and 13c, respectively.
１４８等の配線を引き出したものである。なお、金属電
極６ａ 、６ｂ間は酸化膜２内で配線接続されている。148 etc. wiring is drawn out. Note that the metal electrodes 6a and 6b are interconnected within the oxide film 2.
勿論、ｎ形層７内に孔１１を設けて金属型ｉ５ａ、１３
ａ間を接続する代りに、金属電極５ａ、１３８夫々に接
続された電極２１ａ〜２１ｎ、２３ａ〜２３ｎのうちの
各電極を集積回路の外部で接続しても良い。Of course, a hole 11 is provided in the n-type layer 7 to form a metal type i5a, 13.
Instead of connecting the metal electrodes 5a and 138, each of the electrodes 21a to 21n and 23a to 23n connected to the metal electrodes 5a and 138 may be connected outside the integrated circuit.
ここで、例えばｎ＝３２としても第５図（Ｂ）に示す如
く第１段２０〜第３２段２４夫々に各１個のマイクロプ
ロセッサを構成する。各マイクロプロセッサは第６図に
示す如く、レジスタブロック３０．タイミング制御ブロ
ック３１．命令デコーダブロック３２．演算ブロック３
３及びパスライン３４より大略構成されている。パスラ
イン３４より供給される命令コードは命令デコーダブロ
ック３２で解読され、タイミング制御ブロック３１はこ
の命令デコーダブロック３２よりの信号に応じて制御信
号を生成しレジスタブロック３０゜命令デコーダブロッ
ク３２．演算ブロック３３夫々に供給する。これによっ
てレジスタブロック３０に格納されているデータが演算
ブロック３３に供給されて命令に応じた演算処理が行な
われ、レジスタブロック３０に転送されて格納される。Here, for example, even if n=32, one microprocessor is configured in each of the first stage 20 to the 32nd stage 24 as shown in FIG. 5(B). Each microprocessor has a register block 30. Timing control block 31. Instruction decoder block 32. Arithmetic block 3
3 and a pass line 34. The instruction code supplied from the pass line 34 is decoded by the instruction decoder block 32, and the timing control block 31 generates a control signal according to the signal from the instruction decoder block 32, and the register block 30.degree. instruction decoder block 32. It is supplied to each calculation block 33. As a result, the data stored in the register block 30 is supplied to the arithmetic block 33, where arithmetic processing according to the instruction is performed, and the data is transferred to the register block 30 and stored.
このように第１段２０〜第３２段２４夫々にマイクロプ
ロセッサが構成されるため、この半導体集積回路の大き
さは、従来の単一のマイクロプロセッサを構成したもの
と略同等の大きさで済む。Since a microprocessor is configured in each of the first stage 20 to the 32nd stage 24 in this way, the size of this semiconductor integrated circuit is approximately the same as that of a conventional single microprocessor. .
これによって本発明の半導体集積回路を１チツプ用いる
だけで１ワード３２ピツトのデータを３２個のマイクロ
プロセッサにより並列処理して超高速演算を行なうこと
が可能である。この場合、各マイクロプロセッサ間の配
線距離も、第１図示の孔１１内の金属蒸着によって、又
は例えば電極２１８．２３ａ等の金属蒸着を行なうこと
によって、従来より極めて短かくなり、演算速度が更に
速くなる。As a result, by using only one chip of the semiconductor integrated circuit of the present invention, data of 1 word and 32 pits can be processed in parallel by 32 microprocessors to perform extremely high-speed calculations. In this case, the wiring distance between each microprocessor is also much shorter than before by metal vapor deposition in the hole 11 shown in the first diagram or by metal vapor deposition on the electrodes 218, 23a, etc., and the calculation speed is further increased. It gets faster.
また、並列型のＡ／Ｄ変換器の如く、多くのコンパレー
タを必要とする回路であっても、本発明の多段構成とす
ることによって単一の半導体集積回路上にＡ／Ｄ変換器
の全回路及びその他の付随回路を構成することが可能と
なる。Furthermore, even in circuits that require many comparators, such as parallel type A/D converters, by using the multi-stage configuration of the present invention, all A/D converters can be integrated on a single semiconductor integrated circuit. It becomes possible to configure circuits and other ancillary circuits.
なＪ３、第５図（Ｂ）に示す第１段２０にマイクロプロ
セッサを構成し、第２段２２にインターフェース回路を
構成し、第３段にメモリを構成して、１チツプ上にマイ
クロコンピュータシスデムを構成しても良く、また、第
１段２０に３２ビツトのマイクロプロセッサ、第２段２
２に１６ビツトのマイクロプロセッサ、第３段に８ビツ
トのマイク［ｌプロセッサ夫々を構成して多機能プロセ
ッサシステムを構成しても良く、各段の回路を同一構成
とする必要はなく、上記実施例に限定されない。In the J3, a microprocessor is configured in the first stage 20 shown in FIG. A 32-bit microprocessor may be used in the first stage 20 and a 32-bit microprocessor in the second stage 20.
A 16-bit microprocessor is installed in the second stage, and an 8-bit microphone is installed in the third stage.A multi-function processor system may be constructed by configuring each of the processors, and it is not necessary that the circuits in each stage have the same configuration. Not limited to examples.
発明の効果
上述の如く、本発明になる半導体集積回路は、半導体層
の一面上に構成される集積回路を複数段重骨してなるた
め、単位面積当りの回路集積度が複数１８となって、１
チツプ内に構成される回路数が増大し、また、各段の集
積回路夫々にマイクロプロセッサを構成した場合各段の
マイクロプロセッサにより並列処理を行ない超高速演算
が可能となると共に、各段のマイクロプロセッサ間の配
線距離が短縮され演算の高速化が進み、配線基板上にお
けるチップの占有面積が小となる等の特長を有している
。Effects of the Invention As described above, the semiconductor integrated circuit according to the present invention has multiple stages of integrated circuits constructed on one surface of a semiconductor layer, so that the degree of circuit integration per unit area is 18. ,1
The number of circuits configured within a chip increases, and if a microprocessor is configured for each integrated circuit in each stage, the microprocessor in each stage performs parallel processing, making it possible to perform ultra-high-speed calculations. It has the advantage of shortening the wiring distance between processors, increasing the speed of computation, and reducing the area occupied by the chip on the wiring board.
第１図は本発明になる半導体集積回路の一実施例の断面
を示す図、第２図は従来の集積回路の一例の断面を示す
図、第３図は第１図示の集積回路のＷＪＪ造過程の断面
を示す図、第４図は第３図示のｎ形層の形成過程を説明
するための図、第５図は本発明集積回路の多段構造を説
明するための図、第６図はマイクロプロセッサの全体構
成を示す図である。
１・・・ウェーハ、２．１０．１２・・・酸化膜、３ａ
〜３ｃ 、 ８ａ 〜８ｃｍｐ形層、４ａ、４ｂ、７゜
９ａ 、９ｂ−ｎ形層、５ａ 〜５ｃ、６ａ、６ｂ。
１３ａ 〜１３ｃ、１４ａ、 １４ｂ−・・金属電極、
７ａ・・・多結晶シリコン層、２０・・・第１段、２２
・・・第２段、２４・・・第ｎ段、３０・・・レジスタ
ブロック、３１・・・タイミング制御ブロック、３２・
・・命令デコーダブロック、３３・・・演算ブロック、
３４・・・パスライン。FIG. 1 is a diagram showing a cross section of an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a diagram showing a cross section of an example of a conventional integrated circuit, and FIG. 3 is a WJJ structure of the integrated circuit shown in FIG. FIG. 4 is a diagram for explaining the formation process of the n-type layer shown in FIG. 3, FIG. 5 is a diagram for explaining the multi-stage structure of the integrated circuit of the present invention, and FIG. 1 is a diagram showing the overall configuration of a microprocessor. 1... Wafer, 2.10.12... Oxide film, 3a
-3c, 8a -8cm p-type layer, 4a, 4b, 7°9a, 9b-n-type layer, 5a -5c, 6a, 6b. 13a to 13c, 14a, 14b--metal electrode,
7a... Polycrystalline silicon layer, 20... First stage, 22
... second stage, 24... nth stage, 30... register block, 31... timing control block, 32...
...Instruction decoder block, 33...Arithmetic block,
34...Pass line.
Claims (2)
成し、かつ電極を設けることにより構成される集積回路
を一の段とし、該集積回路の段を該半導体層の面に垂直
方向に複数段重畳してなることを特徴とする半導体集積
回路。(1) An integrated circuit formed by forming an n-type layer and/or a p-type layer on one surface of a semiconductor layer and providing an electrode is defined as one stage, and the stage of the integrated circuit is formed on one surface of the semiconductor layer. A semiconductor integrated circuit characterized by having multiple stages stacked vertically.
ロプロセッサであることを特徴とする特許請求の範囲第
１項記載の半導体集積回路。(2) The semiconductor integrated circuit according to claim 1, wherein each of the integrated circuits configured in each of the plurality of stages is a microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3707585A JPS61196565A (en) | 1985-02-26 | 1985-02-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3707585A JPS61196565A (en) | 1985-02-26 | 1985-02-26 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61196565A true JPS61196565A (en) | 1986-08-30 |
Family
ID=12487431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3707585A Pending JPS61196565A (en) | 1985-02-26 | 1985-02-26 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61196565A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011512598A (en) * | 2008-02-19 | 2011-04-21 | マイクロン テクノロジー， インク． | Method, apparatus and system for a memory device having a network on a chip |
| US9047991B2 (en) | 2008-09-11 | 2015-06-02 | Micron Technology, Inc. | Methods, apparatus, and systems to repair memory |
| US9123552B2 (en) | 2010-03-30 | 2015-09-01 | Micron Technology, Inc. | Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same |
| US9524254B2 (en) | 2008-07-02 | 2016-12-20 | Micron Technology, Inc. | Multi-serial interface stacked-die memory architecture |
-
1985
- 1985-02-26 JP JP3707585A patent/JPS61196565A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011512598A (en) * | 2008-02-19 | 2011-04-21 | マイクロン テクノロジー， インク． | Method, apparatus and system for a memory device having a network on a chip |
| US9229887B2 (en) | 2008-02-19 | 2016-01-05 | Micron Technology, Inc. | Memory device with network on chip methods, apparatus, and systems |
| US9524254B2 (en) | 2008-07-02 | 2016-12-20 | Micron Technology, Inc. | Multi-serial interface stacked-die memory architecture |
| US9047991B2 (en) | 2008-09-11 | 2015-06-02 | Micron Technology, Inc. | Methods, apparatus, and systems to repair memory |
| US9852813B2 (en) | 2008-09-11 | 2017-12-26 | Micron Technology, Inc. | Methods, apparatus, and systems to repair memory |
| US10332614B2 (en) | 2008-09-11 | 2019-06-25 | Micron Technology, Inc. | Methods, apparatus, and systems to repair memory |
| US9123552B2 (en) | 2010-03-30 | 2015-09-01 | Micron Technology, Inc. | Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same |
| US9484326B2 (en) | 2010-03-30 | 2016-11-01 | Micron Technology, Inc. | Apparatuses having stacked devices and methods of connecting dice stacks |
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