TW200816082A - Filtering for VPU - Google Patents

Abstract

Included are embodiments for processing video data. At least one embodiment includes receive logic configured to receive the video data chosen from a plurality of formats and filter logic configured to filter the video data according to the instruction. Similarly, some embodiments include transform logic configured to transform the video data according to the instruction, where the instruction contains a mode indication in which the filter logic and the transform logic execute based on the format of the video data.

Description

200816082 S3U06-0022I00-TW 24598twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to processing video and graphic materials, and more particularly, to provide a video with a programmable core Processing unit. [Prior Art]

With the continuous development of computer technology, the demand for computing equipment has also increased. More specifically, many computer applications and/or data streams require the processing of video data. As video data becomes more complex, the processing requirements for video data increase. Currently, many computing architectures provide a central processing unit (CPU) for processing video and graphics data. Although the CPU can provide appropriate processing power for some video and graphics, the CPU also needs to process other data. Therefore, the need for CPU in processing complex video and graphics can adversely affect the performance of the overall system. In addition, many computing architectures include one or more execution units (EU) for processing data. More specifically, the EU can be used to process multiple = same type of data in at least one architecture. As with C P U, the demand for E U, dealing with complex g and graphical data can adversely affect the performance of the entire computing system. In addition, processing complex video and graphical data by the EU may increase the rate consumption beyond the acceptable threshold. In addition, the data = different agreements or specifications will limit the EU's processing of video and graphics data. Many computing architectures provide 32-bit commands, which is also required for multiple operations. Early, 仟于扪 200816082 S3U06-0022I00-^ 24598twfd〇c/p Therefore, the industry still has unresolved requirements [Summary] There are problems in the field to solve the above defects and deficiencies

The invention comprises a programmable video processing unit for processing video data according to the instruction - an include-receive logic circuit for receiving a view tree selected from a plurality of formats ^, a filter logic circuit for filtering the command according to the instruction The video is poor and the conversion sugar circuit, the ribs according to the instructions to filter data. The command contains a mode indicating smoke blocking to indicate that the filtering logic and the conversion logic operate in accordance with the format of the video material. Another embodiment of the present invention includes a Win-Europe unit H-touch logic circuit for processing video data of at least two formats for recognizing a format of video data; and a compensation logic circuit for performing a The dynamic compensation operates a discrete cosine inverse conversion logic circuit for performing a discrete cosine inverse conversion operation; and an integer conversion logic circuit for performing an integer conversion operation. The discrete cosine inverse conversion logic circuit and the integer conversion logic circuit are respectively turned off according to the identification result of the identification logic circuit. The invention also includes embodiments of a method for processing video material. At least one embodiment includes receiving an instruction; receiving video material selected from one of at least two formats; filtering the video material in accordance with the instruction; and converting the visually poor material according to the instruction. The instruction includes a pattern recognition field for indicating that the step of filtering and converting the video data operates according to the format of the video material. Other systems, methods, features, and advantages of the invention will be apparent to those skilled in the <RTIgt; It is contemplated that all such additional systems, methods, features, and advantages are included within the scope of the description and the disclosure. [Embodiment] FIG. 1 is an embodiment of a computing architecture for processing video data. As shown in Figure 1, the computing device can include a pool 146 of Execution Units (EU). The pool 146 of execution units may include one or more execution units for executing data in the different architecture of FIG. The pool 146 (referred to herein as "EUP 146") of the execution unit can be coupled to the stream cache 116 and receive data from the stream cache 116. The EUP 146 can also be coupled to the input port 142 and the output port 144. Input port 142 can be used to receive data from EUP controller 118 having a cache memory subsystem. Input port 142 can also receive data from L2 cache memory 114 and post-packager 160. The EUP 146 can process the received data and output the processed data to the output port 144. In addition, the EUP controller 118 having the cache memory subsystem can send the message to the memory access unit (MXU) A 164a and the two-corner and attribute configuration unit (playing iangie an ( j attribute setup) 134. The L2 cache memory 114 can also send data to the MXU A 164a ' and receive data from the MXU A 164a. The vertex cache memory (vertex cache) 112 and the stream cache memory n〇 It can communicate with MXU A 164a. 'Memory access port 1〇8 also communicates with Μχυa 164a. Memory access port i〇8 can be connected to bus interface unit (BIU) 90, memory interface unit ( Mem〇ry pool time

Unit, MIU) A 106a, MIU B l〇6b, MIU C 106c and MIU D 106d communication data, the memory access port i〇8 can also be coupled to]^乂1; 3 8 200816082 S3U06-0022I00-TW 24598twf .doc/p 164b 〇

The MXU A 164a is also connected to a command stream processor (c streamman (CSP) front end 12〇 and cSP back end 128. The CSP front end 120 is coupled to the 3D and state components 丨22, 3D and state components. 122 is connected to the EUP controller with cache memory subsystem 118 ° CSP - Uranium end 120 is also lightly connected to the 2D front component (pre c〇mp〇neni) 124, 2D front component 124 is coupled to 2D advanced First out (FIF0) component 126. csp _ front end 120 is also associated with dear and type texture processor 130 and advanced encryption system (AES) encryption/decryption component! 32 communication data. The back end j28 is coupled to the span tile generator (span_tile generat 136. The corner and attribute configuration unit 134 | the horse to the 3D and state component 122, the EUP controller 118 with the cache memory subsystem, and the span A tile generator 136. The span tile generator 136 can be used to send data to the zli cache 128, and the span tile generator 136 can also be coupled to the ZL1. 138 'ZL1 138 can send data to 2 : £1 cache memory 128. Red 2 140 can be coupled to Z (for example, deep buffer cache memory) and template (stencil, ST) cache memory 148. Z and ST cache memory 148 can send and receive data through write back unit I62, and can be connected to the frequency The wide (hereinafter referred to as BW) compressor 146c &gt; BW compressor 146 can also be coupled to the M^UB 164b MXUB 164b can be interfaced to the texture cache memory and control, 166. The texture cache memory and controller 166 can It is coupled to a texture filter unit (TFU) 168. The TFU168 can send data to the post-package device. The post-packager 160 can be coupled to the internal 200816082 S3U06-0022I00-TW 24598twf.doc/ The p-interpolator 156 can be coupled to the interpolator 158 and the texture address generator 150. The write-back unit 162 can be coupled to a 2D pro component 154, D cache 152, Z The ST cache memory 148, the input port 142, and the CSP back end 128. The embodiment of FIG. 1 processes the video material by utilizing the EUP 146. More specifically, in at least one embodiment, one of the execution units or Many can be used to process video data. Although this architecture can be applied to some should Use, but this frame may consume excessive power; in addition, this architecture may be difficult to process Η·264 data. 2 is an embodiment of a computing architecture similar to the architecture of FIG. 1 and incorporating a video processing unit (VPU). More specifically, in the embodiment of FIG. 2, a VPU 199 having a programmable core can be provided in the computing architecture of FIG. The VPU 199 can be coupled to the CSP front end 120 and the TFU 168. The VPU 199 can be used as a dedicated processor for video data. In addition, the VPU 199 can be used to process video data encoded by the Expert Group (hereinafter referred to as MPEG), VC_1, and EL264 protocols.

More specifically, in at least one embodiment, a shader code can be executed on one or more of the execution units (EU) 146. The instructions can be decoded and extracted from the scratchpad, and the primary and secondary opcodes can be used to determine the EU in which the operand is being delivered and the function by which the operation can be performed based on the operand. If the operation is of the SAMPLE type (for example, all VPU instructions are of the SAMPLE type), the instructions can be scheduled from the EUP 146. Although the VPU 199 can be used to reduce the use of TFU filter hardware, the VPU 199 can also reside with the TFU168. 200816082 S3U06-0022IOO-TW 24598twf.doc/p The EUP146 for SAMPLE operation constructs a 580-bit data structure (see Table 1). The EUP 146 extracts the SAMPLE instruction, which is placed in the least significant '512 bits of the EUP-TAG interface structure. Other relevant information that EUP146 inserts into this structure is REGJTYPE: this should be 0

ThreadID - used to post the result back to the correct shader program ShaderResID -

ShaderType - PS CRFIndex - Destination Scratchpad SAMPLE MODE - This is the vpu filtering operation to be performed ExeMode = Vertical This data structure can then be sent to the texture address generator (texture

Address generator, hereinafter referred to as TAG) 150. The TAG 150 can be used to check the SAMPLE-MODE bit to determine if the data block contains texture sample information or actual data. If the actual data is included, TAG 15〇 forwards the data directly to VPU 199, otherwise TAG 15〇 initiates texture extraction:

11 200816082

S3U06-0022I00-TW 24598twf.doc/p Threadld 6 547 542 ;: · batch -: &lt;.: ': drink &gt;do; and "; &lt; ·: grin: general; she"., ♦ ::::;&lt; Block Shader Res ID 2 551 550 ._mm Meaning ^:,::. Shed Type Shader Type 3 -, ,-, 553 » 552 :雠义显:·:Α Bu Lin Layer: , '二: Touch mm:,: 藤养么:义wmm娜.联::' ' r, fiber suture face / appearance / CRFindex 8 565 558 mmm^msm , ' 1 , 雠 drying _, 'λ, column徂瞧国圆 Sample Mode 5 _ .*' : , , '广rr:.' ?,, '圆^^^黎_纤纤:, 570, w _ art _ face circle _ &gt; 566 ύί_&Μ^ Μ,ΜηΓΒ :P1P*_ -^mmm 幼苏面mmmmmmB 丽rnnm exe exe mode 1 571 571 value Horizontal (horizontal) 1 value Vertical (垂直) 〇:: 涂离依骏琴杂钱_怒_ farff /, y 襕 position, Bx2 1 ,, , ' 顚 * * 572 ^ · Listen to the crane mine 572 Jvc2 modification. Note that for san^e Id, this flag is used to indicate whether i uses the sampler, 〇一无 s# and 1 has s# (for 12 200816082 S3U06-0022I00-TW 24598twf.doc/p Miscellaneous: 3⁄4 ,Ρ : ...' :: &lt;R&gt; 9 579 '573 Table 1: The EUP-TAG interface for video processing If SAMPLE_MODE is MCF, SAD, IDF-VC-1, H264-0 or IDF-H264-1 In one case, the texture data needs to be extracted, otherwise the data is in the data block. The TAG 150 is used to generate the information required by the address and passed to the texture cache controller (TCC) 166. Can be found in the least significant 128-bit of the Data Block: Bit [31:0] -U, V coordinate, this constitutes the address of the texture block (4x4x8 bits) Bit [102:96]-T# bit Yuan [106:103]-S# T#, S#, U, and V are sufficient information for the texture extracted from a particular surface. U, V, T#, S# can be from the SRC1 field of INSTRUCTION during decoding. Extracted, and can be used to fill the above blocks. Therefore, U, V, T#, S# can be dynamically modified during execution.

The SAMPLE_MODE and the least significant 128 bits of the information containing this information can then be placed in the VPU 199 command first-in first-out memory (hereinafter referred to as COMMAND HFO), and the corresponding data FIFO can be filled. Data (bits [383:128]) or 256 bits (maximum) that are forwarded by the texture cache. This data will be manipulated in the VPU 199, which is judged by the 寅' of c〇MMAND FIF〇. The result (Luxury 2S6攸) can be used with ThreadlD 13 200816082 S3U06-0022I00-TW 24598tw£doc /p and CRFIndex are passed back to the EUP 146 and the EU register as the return address. Additionally, the present invention includes a set of instructions provided by EUP 146 and available to VPU 199, the instructions of which can be formatted into 64 bits, although this is not necessary. More specifically, in at least one embodiment, the VPU instruction set can include one or more motion compensation filter (MCF) instructions. There may be one or more of the following MCF instructions in this embodiment: SAMPLE-MCF-BLR DST, S#, T#, SRC2, SRC1 SAMPLE-MCF-VC1 DST, S#, T#, SRC2, SRC1 SAMPLEJS4CFJH264 DST The first set of 32 bits of S, S#, T#, SRC2, and SRC1 SRC1 contain U and V coordinates, of which the least significant 16 bits are U. Since SRC2 may not be used or may be ignored, SRC2 may be any value, such as a 32-bit value containing a 4-element filter core, each element exposing a signed 8-bit element as follows. Chopper core (SRC2? ~3| 3| 2|2|2|2|2T2&quot; 11 〇19] si 7 Uhl 4 core [3] 2 2 2 2 1 1 1 1 1 3 2 1 0 9 8 7 6 5 Core [2] 4 3 Core [2] 2 0 9 0 4 Core [〇] 0 2 0 0 Table 2: MCF Filter Core In addition, the VPU 199 instruction set also includes in-loop deblocking filtering (Inloop Deblocking Filtering, The following is the instruction of IDF), such as one or more of the following instructions: · SAMPLE_IDF—VC1 DST, S#, T#, SRC2, SRC1 14 200816082 S3U06-0022I00-TW 24598twf.doc/p SAMPLE—IDF—H264 —0 DST, S#, T#, SRC2, SRC 1 SAMPLEJDF_H264 1 DST, S#, T#, SRC2, SRC1 SAMPLE IDF—H264—2 DST, S#, T#, SRC2, SRC1 For VC-1 IDF Operation, the TFU 168 can provide 8x4x8 bits (or _ 4x8x8 bits) of data to the filter buffer. However, for H.264, the amount of data transported by the TFU 168 can be controlled by the type of 264264 IDF operation. For the SAMPLE-IDF-H264-0 instruction, the TFU supplies 8x4x8 bits (or 4x8x8 bits) of data blocks. For SAMPLE IDF H264 1 - the instruction 'TFU 168 supplies a 4x4x8 bit data block, and A 4x4x8 bit data is supplied by the shader (EU) 146 (Fig. 2). In addition, with the SAMPLE-IDF-H264-2, both 4x4x8 bit data blocks can be supplied by the shader (located at ETJ) 146. Rather than from TFU 168. The 'VPU 199 instruction set also includes dynamic estimation (ME) instructions, which may include instructions such as those listed below: • SAMPLE-SAD DST, S#, T#, SRC2, SRC1. The above instructions can be mapped to the following primary and secondary opcodes and take the format described above. The details of the SRC and DST formats are discussed below in the relevant instructions section. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 , :S Λf ,乂' :Ί ι£^ %, Move S S2 S SRC2 SS 1 S 31 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 15 200816082 S3U06-0022I00-TW 24598twf.doc/p

Table 3: Dynamic estimation and corresponding opcodes, the set of bits in the basin locks the EU data path and does not allow another thread to enter the tube. LOCK JEG indicates the inversion of the predicate _ 〇 〇.

The s# and T# blocks are ignored by the VPU SAMPLE instruction. Instead, the T# and S# blocks encoded in SRC1 are used. Command '^ Minor Operation Code SSSAMPLE—MCFJBLR 0 0 0 0 0 0 0 0 SSAMPLE—MCF—VCM 0 0 0 0 0 0 0 1 SSAMPLE-MCFJH264 0 0 0 0 0 1 0 0 SSAMPLEJDDF-VC-1 0 0 0 0 0 1 0 1 SSAMPLE-IDFJH264—0 0 0 0 1 0 0 0 0 SSAMPLE IDF H264 1 0 0 0 1 1 0 1 1 SSAMPLEJDFJH264-1 2 0 0 1 1 0 1 0 0 SSAMPLE-SAD 0 0 1 1 1 1 1 1 Table 4: Dynamic Compensation Filtering and Corresponding Opcodes SAMPLE TCF MPEG2 Benefits from texture cache memory data instruction iSiPi Note SAMPLE TCF 14x4 0 0 0 — 0 SAMPLE TCF M4x4 0 0 0 —1 —_______ 16 200816082 S3U06-0022I00-TW 24$98twf.doc/p SAMPLE TCF MPEG2 0 0 1 0 Table 5 ··Transform coefficient filtering (hereinafter referred to as TCF) and the corresponding opcode SAMPLE instruction are shown in Figure 3. Execution path. In addition, the interface is as shown in Table 6 below. Other interfaces will also be in the job.

17 200816082 S3U06-0022I00-TW 24598twf.doc/p : , ': two ( V, /-:-:;, y iiS' e^hiode 1 571 wmmmsmmmmmm: Horizontal (water value flat) 1 value Vertical (vertical) :—— ' : ; * - - ~ 0 ? :r,':w:... 战_! .崎';.;:;w:'' '. Λ,:/ again:·® 言过m 逊6: The euP-TAG interface for video processing should note that the texture sample filtering operation can also be mapped to the _ arbitrage, in this case the value is 00 ΧΧΧ. The value 11 χχχ is currently reserved for future use. In addition, in this paper In at least one embodiment of the disclosure, some video functions can be inserted into the texture pipeline to reuse the L2 cache memory logic and some L2 to pass the (four), such as M] ^ dynamic estimation), MC (dynamic Compensation), TC (conversion coding) and ID (deblocking in the loop). The following table summarizes the data loading criteria from TCC 166 and/or TFU 168 for different sample instructions. (10) ς 1 ΑΛ η ^ / The main thinking depends on the 4 inch architecture,

Sample-MC-H264 can be used only for γ is not required. Y Thousand Faces, but for (10) Plane and 18 200816082 S3U06-0022IG0-TW 24598twf.doc/p Λ Directives to discuss Xinjiang ^^ Love ^1!1 Love Ιβ__ Discussion:, annotation, Y flat fe CrCb plane, SAMPLE —MCJBLR self-texturing memory 8x8x8 bit block is SAMPLE-MC-VC1 self-texturing memory 12x12x8 bit block is SAMPLE-MCJH264 self-texture memory memory 12x12x8 bit block whether SAMPLE-SAD From the 8x4x8-bit block of texture cache memory, V can be any alignment of 8x4x8 bits (or 4x8x8 bits) of SAMPLE-IDF-VC1 self-texturing memory, 32-bit alignment is SAMPLE JDF_H264 0 8x4x8 bits (or 4x8x8 bits) from texture cache memory, 32-bit alignment is 4x4x8 bits of SAMPLE IDF H264-1 self-texturing cache, 32-bit alignment is SAMPLE IDF H264 —2 No self-texturing memory data SAMPLE A TCF—14x4 no self-texturing memory memory SAMPLE-TCF—M4x no texture memory data SAMPLE-TCF M3P EG2 no self-texture Cache memory Material SAMPLE JMADD No self-texturing memory memory SAMPLE SMMUL No texture memory data Table 7: Data loading for video 19 200816082 S3U06-0022IO0-TW 24598twf.doc/p In this article In at least one embodiment of the disclosure, the gamma plane may comprise a HSF-YOY1Y2Y3_32BPE_VIDE02 tiled format. The CrCb plane includes interleaved CrCb channels and is considered to be in the HSF_CrCbJ6BPE_VIDEO tile format. If the CbCr interlaced plane is not required, the same format as the Y plane can be used for Cb or Cr. In addition, the following instructions have been added to the Shader Instruction Set Architecture (ISA).

SAMPLE MCF BLR SAMPLE MCF VC 1 SAMPLE MCF H264 SAMPLE—IDF—VC 1 SAMPLE—IDF-H264J) SAMPLE—IDF-H264-1 SAMPLE-SAD SAMPLE-TCF-MPEG2 SAMPLE-TCFJ4x4 SAMPLE-TCF-M4x4 SAMPLE-MADD SAMPLE IDF H264 2 DST, #cM, SRC2 DST, #ctrl, SRC2 DST, #ctrl, SRC2 DST, #cM, SRC2 DST, #ctrl, SRC2 DST, S#, T# DST, S#, T# DST, S# , T# DST, S#, T# DST, S#, T# DST, S#, T# DST, S#, T# SRC2, SRC1 SRC2, SRC1 SRC2, SRC1 SRC2, SRC1 SRC2, SRC1 SRC2, SRC1 SRC2 , SRC1 SRC1 SRC1 SRC1 SRC1 SRC1 for SAMPLE-IDF-H264_2 #你1 should be zero. SRC1, SRC2, and #ctrl (when available) can be used to form a 512-bit data field in the EU/TAG/TCC interface as shown in Table 8 below. Bit 0 20 200816082

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ο (N inch ^Τί v〇卜 CO ON 111 round ΐ 〇CS m ί VO 'V &gt; 卜:, 00 〇\ CN CN &lt; m &lt;N Τ ( (N CN port oo &lt;N On (N Τι

TnsssWIJIWW XlSlISdwvs tN—SZH丨srsdls “SZHISrsdIWS0丨 9ZHtsrsJ_s OVSTwldlMVcoGA 丨.iarwljwvw XI&amp;SISJNVS

f 11^5 Thick ztsmldorsdis r City χ—δι 丨HltlNVS ^oJluou 戏伞 w IJP#^^(N3es , Ioes : 6 竣嵴200816082 S3U06-0022I00-TW 24598twf.doc/p See Table 8, ΤΓ = transpose; FD = filtering direction (vertical; bS = Boundary Strength; bR = bR control, ye bit (YC = 1 in CbCr plane; YC = 于 in Y plane), and CEF = Chroma edge flag (Chroma Edge Flag. In addition, when 32 bits or (or fewer bits) are used for SRC1 or SRC2 (remaining undefined), a lane selection may be specified to reduce the use of the scratchpad. Format, but the following is an overview of the operation of the instruction in Table 1. The instruction name instruction format instruction operation SAMPLE_MCFJBLR SAMPLE_MCF BLR DST &gt; SRC2 &gt; SRC1 MC filter implementation SAMPLE-MCF-VC1 SAMPLE-MCF VC1 DST ^ SRC2 ^ SRC1 implements SAMPLE-MCF-H264 SAMPLE MCF H264 DST ^ SRC2 &gt; SRC1 for MC-1 of VC-1. For the MC of H.264, apply SAMPLEJDF-VCl SAMPLE-IDF VC1 DST ^ SRC2 -&quot;SRCl deblocking operation SAMPLEJDF —H264—0 SAMPLE IDF H264 0 DST ^ SRC2 ^RCr H.264 deblocking operation. 4x4x8 (vertical filter) or 8x4x8 block is provided from texture cache memory 166. SAMPLE-IDF-H264-1 SAMPLE_IDF-H264-1 DST, SR&quot;t2, SRC1 Η 264 operation. A 4x4x8 bit block is provided from the shader, and another 4x4x8 bit block is provided from the texture cache memory 166. This allows the construction of an 8x4 (or 4x8) block. SAMPLE_IDF-H264-2 SAMPLE IDF H264- 2 DST, #cM, S anti-C2, SRC1 H.264 Two 4x4 blocks are provided by the cover 23 200816082 S3U06-0022I00-TW 24598twf.doc/p, 8x4 blocks. SAMPLE_SAD SAMPLE-SAD DST, S#, T #, SRC2, SRC1 Perform four absolute difference sum (SAD) operations on the reference (SRC2) and the prediction data. SAMPLE-TCF—Ι4χ4 SAMPLE TCF 14x4 DST, #ct5, SlTC2, SRC1 transform coding implementation SAMPLE-TCF—Μ4χ4 SAMPLE-TCFM4x4 DST, #ctrl, SRC2, SRC1 variable SAMPLE-TCF—MPEG2 SAMPLE-TCF MPEG2 DST, #ctrb SiTc2 , SRC1 variable SAMPLE - MADD SAMPLE - MADD DST, #ctri, SRCW, SRC1 See SAMPLE SIMMUL SAMPLE - SIMMUL DST, #ctS, SRC2, SRC1 Perform scalar matrix multiplication. #ctrl is an immediate value of 11 bits. This can be 〇 (for example, the #ctrl signal will be ignored). See also below ^ *----- Table 10: Instruction overview • In addition, for SAMPLE-MADD, #ctrl can be an immediate value of η bits, in addition to two 4x4 matrices (SRC1 and SRC2) addition. One or more elements of either matrix may be a 16-bit signed integer, and the result (DST) is a 4 X 4 16-bit matrix. The matrix can be placed in the source/destination register as shown in Table 11, which can be an individual unit within. In addition, the SRC1 and #ctrl data are available for access on the 1st day of the cycle, and the SRC2 can be accessed in subsequent cycles. Therefore, an operation can be issued every two cycles. #Ctrl[〇] indicates whether to perform a saturation (SAT) operation. 24 200816082 S3U06-0022I00-TW 24598twf.doc/p #ctrl[l] Indicates whether to perform rounding (r〇unding, r) operations. #ctrl[2] indicates whether to perform a 1-bit right shift (10) wave, g) operation. #ctrl[10:3]Ignore. .

Table 11: Registers for Source Matrix and Destination Matrix In addition, the logic guidelines associated with this material can include the following: #Lanes := 16; #Lanewidth :― 16;

If (#ctrl[l]) R = 1; ELSE R = 0;

If (#ctrl[2]) S = 1; ELSE S = 0; IF (#ctrl[0]) SAT - 1; ELSE SAT = 0;

For (I := 0; I &lt;#Lanes; I += 1){

Base := I * #Lanewidth;

Top Base + #Lanewidth - 1;

Sourcelfl] := SRC1 [Top..Base];

Source2[I] := SRC2[Top..Base];

Destination^] := (Sourcel[I] + Source2[I] + R) » IF (SAT) Destination[I] = MIN(MAX(Destination[I],0),255); DST[Top..Base] = Destination[I]; Referring again to Figure 9, the multiplication of the scalar matrix is performed. #ctrl为ii bit 25 200816082 S3U06-0022I00-TW 24598twf.doc/p Element immediate value, this value can be 〇 (that is, the #ctrl signal will be ignored). This instruction is in the same group as SAMPLE-TCF and SAMPLEJGDF_H264_2. The logic guidelines associated with this directive can include the following: #Lanes := 16; #Lanewidth := 16; MMODE = Control a 4[17:16]; SM = Control"[7:0]; SP = Control_4[15: 8]; //Use only the least significant 5 bits

For (I : 2 0; I &lt;#Lanes; I += 1){

Base := I * #Lanewidth;

Top := Base + #Lanewidth - 1;

Source2[I] SRC2[Top..Base];

Destination^] (SM * Source2[I]) » SP; DST[Top..Base] = Destination^];} This is implemented using the FIR-FILTERJBLOCK unit in the VPU for performing MCF/TCF. SM is the weight applied to all lanes (for example, W[0] = W[l] = w[2] = W[3] = SM), and Pshift is SP. When this is done, the sum adder in FiRjpILTERJ3LOCK is crossed, the four results from the 16x8 bit multiplication can be shifted, and the least significant 16 bits of each result are collected together into 16 16-bits. The result is passed back to eu. 3 is an embodiment of a flow diagram illustrating the process for processing video material in the computing architecture of FIG. 2. More specifically, the command stream processor can send data and instructions to the EUP 146 as illustrated in the embodiment of FIG. The EUP 146 is accordingly available to read instructions and process the received data. 26 200816082 S3UG6-0022I00-TW 24598twf.doc/p EUP146 can then send the instructions, processed data, and data from the Eup Texture Address Generation (TAG) interface 242 to the Texture Address Generator (TAG) 150. The TAG 150 can be used to generate the address of the processed data. The TAG 150 can then send the data and instructions to the texture cache controller (TCC) 166. The TCC 166 can be used to capture the lean material used for the texture unit (tfu) 168. The TFU 168 may filter the received resource ′ based on the received command and send the filtered data to the video programmable unit (VPIJ) 199. The VPU 199 can process the received data according to the received instructions and send the light processed data to a post wrapper (ppstpacker, psp) 16〇. pSp collects pixel packets from components such as TFU ι68. If the brick is complete and sub-complete, the PSP 160 can package multiple bricks and send the brick back to the EUP 146 using the specific identification symbol sent to the pipeline. 4A is an embodiment of a functional flow diagram illustrating data flow in a computing device, such as a computing device having the computing architecture of FIG. 2. As illustrated in the embodiment of Figure 4A, the encrypted data stream can be sent to the CSP 120, 128&apos;==decryption component 236. In at least one embodiment, the encrypted bit stream can be uncompressed and written back to the video memory. The variable length decoder (VLD) hardware can then be used to decode the decrypted video. Decryption component 236 can decrypt the received bitstream to form encoded bitstream 238. The encoded bit stream 238 can be sent to a VLD, a Huffman decoder, a complex a variable length decoder (CAVLC), and/or a binary arithmetic encoder (c〇) Ntext Based Binary Arithmetic Coder 'CABAC) 240 (referred to herein as "Solution 27 200816082 S3U06-0022I00-TW 24598twf.doc/p). Decoder 240 decodes the received bit stream and decodes the bit Yuan sent to DirectX Video Acceleration (DirectX Video

Acceleration, DXVA) data structure 242. In addition, the data received at the DXVA data structure 242 are external mpeG-2 VLD back-scan, • inverse quantization and inverse DC prediction, and external VC-l VLD back-scan, inverse ‘anti-DC/AC prediction. This data can then be retrieved from the DXVA data structure 242 via image header 244, memory buffer 0 (MBO) 246a, MB1 246b, MB2 246c, .., MBN 246η φ, and the like. The data can then enter jump blocks 250, 252, and 254 to continue in Figures 4B and 4C. Figure 4B is a continuation of the functional flow diagram of Figure 4A. As shown, the skip blocks 250, 252, and 254 from Figure 4A receive data at the inverse scan inverse Q component 264 and the inverse DC/AC prediction component 262. This data is processed and sent to switch 265. The switch 265 determines whether the data is sent via the intra/interter input and sends the selected data to the jump block 27A. Additionally, the data from the skip block 260 is sent to the coded pattern block reconstruction component 266. 4C is a continuation of the functional flow diagram of FIGS. 4A and 4B. The data from jump blocks 272, 274 (Fig. 4A) is received at filter component 280 as shown. This data is filtered by the Mc filter 282 according to any of a number of protocols. More specifically, if the data is received in the MpEG_2 format, the data is constructed with a % pixel offset, and a tw〇 pass filter can be used to perform both vertical and horizontal filtering. If the data is received in vc-i format, the 4-tap (4_tap) filter is used; when the data is 1/2-degree, it operates in bilinear mode, when the data is 28 200816082 S3U06-0022I00-TW 24598twf When .doc/p is 1/4 accuracy, it operates in bicubic mode. On the other hand, if the poor material is received in the H.264 format, a 6-tap filter can be used; when the data is sampled as a quarter-pixel, the luminance interpolation is used, and when the data is sampled, the chrominance interpolation is used. The chopped data is then sent to the rebuild reference component 284' and the filter and waver component 28&apos; associated data is sent to the switch component 288. Switch component 288 also receives zeros. The switch component can be based on the received Intm/Inter data to determine which data will be sent to the addition, benefit 298. In addition, inverse conversion component 296 receives data from coded pattern block reconstruction component 286 and receives data from switch 265 (Fig. 4B) via jump block 276. The inverse conversion component 296 performs 8χ8 discrete cosine inverse conversion (Πχ:τ) for MPEG_2 data, 8χ8, 8χ4, 4χ8, and/or 4x4 integer conversion for vc] data, and 4χ4 integer conversion for η·264 data, according to the desired The conversion is performed, and this data is sent to the adder 2 fierce. The adder 298 sums the data of the inverse conversion component 296 and the switch 288, and sends the summed data to the in-loop filter 2f6. The in-loop filter 296 filters the received data and filters it. The material is sent to the reconstruction framework component 290. The reconstruction framework component 290 sends the data to the reconstructed McCaw component 284. The reconstruction framework component 290 can ship the data to a deblocking and detling filter 292, which can send the processed data to a de-interlacing component 294 for deinterlacing. The data is then available for display. 5A is a diagram illustrating components that may be used to provide dynamic compression (MC) and/or discrete cosine transform (DCT) in a VPU, such as in the computing architecture of FIG. 2, 200816082 S3U06-0022I0Q-TW 24598 twf.doc/p Functional block diagram of an embodiment. More specifically, as shown in FIG. 5A, the BB brother's bus A can be used to send 16-bit data to the round-up PEb of the PE3 314d, and the bus A also sends the data to the delay component 3Ό0. To send 16-bit data to the second input of PE 2 314c. Bus A also sends this tribute to Z1 delay component 302 to send 16/bit data to PE 1 314b, which is also sent to ζ-ι delay component 304, which then enters PE 〇 314a and delay component 3 〇 6. After passing through the B1 delay component 3〇6, the lower 8 bits of bus A are sent to PE 0 314a, which is delayed by ΖΓ1 306 and sent to pe 1 314b and Z·1 delay component 310. After reaching the ζ-ι delay component 31〇, the lower octet of this data is sent to the pe 2 314c and the Z·1 delay component 312; after reaching the Ζ-ι delay component 312, the lower 8 bits of the data are sent to PE 3 314d. In addition, bus B transmits 64-bit data to each of PE 3 314d, PE2 314c, PE 1 314b, and PE 0 314a. Processing element 0 (processing Elelment, PE 〇) 314a facilitates the filtering of received data. More specifically, you can use one of the filters. When PE 0 314a, PE 1 314b, PE 2 314c, and PE 3 314d ^ adder 330 are combined, this can form a 4-tap / 8-tap F j R filter. A portion of the bait is first sent to the ζ-3 delay component 316. The multiplexer 318 selects the data to output the input data from the field input response component (FIEW Input Response, FIR) to the selection of the multiplexer 318, which is sent from the multi-mode 318 to the adder mo. Similarly, data from PE 1 314b is sent to multiplexer 322, some of which is first received at z-2 delay component 32. The multiplexer 322 30 200816082 S3U06-0022I00-TW 24598twf.doc/p selects the received data from the received FIR input and selects the data I to be sent to the adder 330. The data of PE 2 314c is sent to multiplexer 326, some of which is first sent to rl delay component 324. The data to be sent to the adder 330 is selected and sent from the data of the pE 3 314d to the adder 330. Also input to the adder 330 is a feedback loop of the N shifter 332. This beaker is received at multiplexer 328 via Z1 delay component 326. Also _ received the rounded data at 328. The multiplexer 328 selects the received data via the 1 input at the selection of the multiplexer 328. The multiplexer 328 sends the selected data to the adder 33, the adder 330 adds the received data and sends the added data to the N shifter 332, which is sent to the output. Figure 5B is a continuation of the diagram of Figure 5A. More specifically, as illustrated in the embodiment of Fig. 5B, data from the memory buffers 34A, 34B, 34C, and 340d is sent to the multiplexer 342a. The multiplexer 342&amp; sends 16-bit data to the skip blocks 344a and 346a. Similarly, multiplexer 342b receives data from memory buffers 340b, 340c, 340d, and 340e, and sends the material to jump blocks 344b and 346b; multiplexer 342c receives data from 340c, 340d, 340e, and 34〇f. And the data is sent to 344c and 346c; the multiplexer 342d receives the data from 34〇d, 34〇e, 34〇f and 34〇g and sends the data to the jump block 344 (1 and 346d; the multiplexer 342e from 340e) , 340f, 340g, and 340h receive the data and send the data to 344e and 346e; multiplexer 342f receives the data from 340f, 340g, 340h, and 340i and sends the data to 344f and 346f; multiplexer 31 200816082 S3U06-0022I00-TW 24598twf.doc/p 342g receives data from 340g, 340h, 340i, and 340h and sends the data to jump blocks 344g and 346g; multiplexer 342h receives data from 340h, 34〇i, 340j, and 340k and sends the data to 344h and 346h; multiplexer 342i receives data from 340i, 340j, 340k, and 3401 and transmits the data to jump blocks 344i and 346i. Figure 5C is a continuation of the diagram of Figures 5A and 5B. More specifically, self-multiplexer 342a Information (via jump block 348a) Sended to the memory buffer B, the slot 350a; the data from the multiplexer 342b (via the jump block 348b) is sent to the memory B, the slot 350b; the data from the multiplexer 342c (via the jump block 348c) is sent to the memory B, slot 350C; data from multiplexer 342d (via jump block 348d) is sent to memory B, slot 350d; data from multiplexer 342e (via jump block 348e) is sent to memory B, slot 350e; The data of the multiplexer 342f (via the jump block 348f) is sent to the memory B, the slot 350f, and the data from the multiplexer 342g (via the jump block 348g) is sent to the memory B, the slot 350g; the data from the multiplexer 342h (via jump block 348h) sent to memory B, slot 350h; data from multiplexer 342i (via jump block 348i) is sent to memory B, slot 350i. Similarly, self-jump block 362j-362r data (from Figure 5D, discussed below) is sent to Transpose network 360. Transpose network 360 transposes the received data; and sends it to memory buffer B, which sends the data to Jump blocks 366j-366r. Figure 5D is a continuation of the Figures 5A-5C. More specifically, data The multiplexer 369a is received from the jump block 368a (Fig. 5B via the multiplexer 342a) and the jump block 368j (Fig. 5C via the memory buffer B), 32 200816082 S3U06-0022I00-TW 24598twf.doc/p The data is selected by the vert signal and sent to the FIR filter block 〇370a via bus a (see Figure 5A). Similarly, multiplexers 369b-369i receive data from jump blocks 368b-368i and 368k-368r, which are sent to pIR filter blocks 370b-370i and processed as described with respect to Figure 5A. The data output from the FIR filter block 〇370a is sent to the skip blocks 372b and 372j; the FIR filter block 370b is output to the jump blocks 372c and 372k; the FIR filter block 370c is output to the jump blocks 372d and 3721; and the FIR filter block 370d outputs Up to jump blocks 372e and 372m; FIR filter block 370e is output to jump blocks 372f and 372n; FIR filter block 37〇f is output to jump blocks 372g and 372A; FIR filter block 370g is rotated to jump blocks 372h and 372p The FIR filter block 370h is output to the skip blocks 372i and 372q; the FIR filter block 37〇i is output to the skip blocks 372j and 372r. As discussed above, the data from the skip block 372j_372r is received by the transposition network 360 of Figure 5C. Jump blocks 372b-372j continue in Figure 5E. Figure 5E is a continuation of the Figures 5A-5D. More specifically, as illustrated in the embodiment of Figure 5E, the data from the skip block 376b (via the FIR filter block 370a of Figure 5D) is sent to the memory buffer c, slot 38 〇 b. Similarly, the data from the skip block 376c (via the FIG. 5D2 FIR filter block 370b) is sent to the memory buffer c, slot 380c; the data from the skip block 376d (via the FIR filter block 370c of FIG. 5D) is sent to the memory. Buffer C, slot 380d; data from jump block 376e (via FIR filter block 370d of FIG. 5) is sent to memory buffer c, slot 38〇e; data from jump block 376f (via Figure 5D) FIR filter block 37〇e) is sent to δ 己 体 体 体 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 370f) sent to the memory buffer c, the slot 380g; the data from the jump block 376h (via the FIR filter block 370g of FIG. 5D) is sent to the memory buffer c, the slot 380h; the data of the self-jumping block 376i The FIR filter block 370h) of FIG. 5D is sent to the memory buffer C, slot 380i; the data from the skip block 376j (via the FIR filter block 370i of FIG. 5D) is sent to the memory buffer c, slot 380j. The multiplexer 382a receives data from the memory buffer C, the slots 38〇b, 38〇c, and 380d; the multiplexer 382b receives data from the memory buffer slots 380d, 380e, and 380f; the multiplexer 382c is self-memory The buffer c, the slots 380f, 380g, and 380h receive the data; the multiplexer 382d receives the data from the memory buffer C, the slots 380h, 380i, and 380j. Once the data is received, the multiplexers 382a-382d send the data to the ALUs 384a-384d. The adder 382d receives the data and the value "" to process the received data and send the processed data to the shifters 386a-386, respectively (i, the shifters 386a-386d shift the received data and The shifted data is sent to Z-blocks 388a-388d, and the data is then sent from z-blocks 388a-388d to multiplexers 390a-390d. Additionally, Z-block 388a receives the data from jump block 376b and transmits the data to multiplexed 390a; Z block 3881) self-jump block 376 (: receives data and sends the data to multiplexer 390b; Z block 388c receives the data from jump block 376d and sends the data to multiplexer 39〇c; z block 388d receives the data from the skip block and The data is sent to multiplexer 390d; multiplexer 39〇a39〇d also receives the selection input and sends the selected data to the output. Figure 5F is an embodiment of the general diagram of the components of Figures 5A-5E. More specifically 34 200816082 S3U06-0022I00-TW 24598twf.doc/p As explained in the embodiment of Fig. 5F, the data is received at the memory buffer a 34. This data is at the multiplexer 342 and the memory buffer A 34 〇^ Other information - multiplexing. multiplexer 342 selection data And the selected data is sent to the memory buffer B 35. The memory buffer B 35〇 also receives data from the automatic transmission network 360. The memory buffer B 35〇 sends the data to the multiplexer 369 'multiplexer 369 The data is also received from the multiplexer 342. The multiplexer 369 selects the data and sends the selected data to the FIR filter, wave 370. The FIR filter filters the received data and sends the filtered data to the memory buffer. The device c 38G, the Z component 388, and the transfer network 360. The memory buffer C38 transmits the data to the multiplexer, and the multiplexer 382 selects the selected data from the data received by the memory buffer c 38 to the ALU 384. The ALU 384 calculates the result from the received data, and sends the calculated data to the shifter 386. The bit data is sent to the multiplexer 39, and the multiplexer receives the poor material from the z component ^, the multiplexer Several results are selected and sent to the output. The components shown in Figures 5A-W 5F can be used to provide dynamic compression and/or discrete cosine transform (DCT). More specifically, depending on the data format and/or data format Set, the data can be returned n = r?rr. In addition, depending on the format, the lean material may be received from EU 146 and/or TFU 168. As a non-limiting example, in actual operation, the Figure VIII component may be used to receive information about the pending The operation (for example, the operation of ^^ scattered cosine to change). In addition, it can also be connected to the same as H.264, VC heart-like, etc. (example is not as good as an embodiment, to 35 200816082 S3U06-0022I00 -TW 24598twf.doc/p = For the 264 format, dynamic compensation (MC) data can pass through the FIR filter in multiple cycles and then enter the memory buffer for conversion to the % pixel format. As discussed in more detail below, other operations or other materials in the 264·264 format may be useful for the same or non-identical use of the components of Figure 5F. Alternatively, the multiplication delta can be used as an array of multipliers to perform 16 16-bit multiplications and/or as vector or matrix multiplication crying. An example of this is the SMMUL instruction.

6 is a functional block diagram of a pixel processing engine that can be used in a computing architecture, such as the computing architecture of FIG. 2. More specifically, as illustrated in the embodiment of Fig. 6, the bus bar (before the shift register) and the bus bar = 5 Α) send the 16-bit data to the multiplexer 4〇〇. The multiplexer*(8) receives the negative signal from the FIR filter 37G and selects a 16-bit data to send the data to the multiplexer 4〇6. In addition, multiplex = 02 can be used to receive bus A data (after shift register) and to order. The multiplexer 402 can select the result from the 6-tap data at the selection point, and the 16-bit 兀 result can be sent to the 16-bit unsigned adder 〇4. The 16-bit 兀 unsigned adder 4〇4 can also be used. Receive data from bus a (before the shift register). The 16-bit unsigned adder 404 can sum the received data and send the result to the multiplexer 406. The multiplexer 406 can be selected from the inverted 6-tap data received from the selected port, and the selected data is sent to the 16x8 multiplier 410, which can also receive the mode data. The 24-bit result can then be sent to shifter 412 to provide a % bit result. 36 200816082 S3U06-0022I00-TW 24598twf.doc/p

Figure 7A is a block diagram of the functionalities of the components that can be used in a VC-1 in-loop filter, such as in the variant architecture of Figure 2. As shown in the embodiment of FIG. 7A, the multi-work 420 can receive "丨,, and value" at the input port, and the value of the work can also receive the A0 absolute value &lt; pquant or not as a selection input. Similarly, multiplexer 422 can receive "丨,, value, and "〇,, value, and A3 &lt; A0 490c absolute value or not. Multiplexer 424 can receive "J,, value, 〇 value as input, and The clip value is not equal to 〇 or not (from shifter 468 of Figure 7C) as a selection input. Additionally, the data output from multiplexer 420 can be sent to logic OR gate 426, which can send the data to multiplexer 428. The multiplexer 428 can also receive fllter_otherJ lean as input. More specifically, as shown in FIG. 7A, a filter-other-3 signal can be generated. If the signal is not zero, it indicates that the other two columns of pixels need to be filtered. Otherwise, the 4x4 block may not be filtered (modified). The multiplexer 428 selects the output data based on the processed pixel data 3 received at the selection input. Figure 7B is a continuation of the Figure 7A. More specifically, as illustrated in the embodiment of FIG. 7A, the absolute value component 43 receives the 9-bit input A1 490a (from FIG. 7D), and the absolute value component 432 receives the 9-bit input A2 49〇b (from FIG. 7D). ). By calculating the absolute value of the received data, the minimum component 434 determines the minimum value of the received data and uses this data as output A3 and sends it to the 2's compliment component 436. 2 Carry Complement Component 436 calculates the 2-bit complement of the received data and sends this data to subtraction component 438. The subtraction component 438 subtracts this data from the input data A 〇 490c (from Figure 7D) and then sends it to the shifter 44 移位 to shift the 37 200816082 S3U06-0022I00-TW 24598 twf.doc/p result to the left by two bits and send To adder 442. In addition, the rounding of the subtraction component 438 is input to the adder 442, thus allowing the circuit to perform an operation multiplied by 5 without using a multiplier. Adder 442 sums up the received data and sends the result to shift &apos;state 444. The shifter 444 shifts the received data to the right by three bits and sends the data to a clamp comp〇nent 446. Clamp component 446 also receives the clip value clip (self-shifter 468, Figure 7C) and sends the result # to the output. It should be noted that the result of the filter can be negative or greater than 255. Thus, the clamp component 446 can be used to clamp the result to an unsigned δ bit value. Therefore, if the input d is negative, then d will be set to 〇. If d&gt; clips the value of clip, then d can be set to the clip value ciip. Figure 7C is a continuation of the Figures 7A and 7B. As shown in Fig. 7C, the example 'P1 data 450a, P5 data 450e, and P3 data 450c are transmitted to the multiplexer 452. The multiplexer 452 receives the selection input and selects the data for narration to the $method component 460. The multiplexer also sends the output data to the selection input of multiplexer 454. Multiplex 1 § 454 also receives input data from P4 450d, P8 450h and P6 450f. The multiplexer 454 sends the output data to the subtraction component 46A. Subtraction component 460 subtracts the received data and sends the result to shifter 466. Shifter 466 shifts the received data one bit to the left and sends the result to jump block 474. Similarly, the multi-work 456 receives the wheels P2 45〇b, P3 450c, and P4 450d. The multiplexer 456 receives the selection input from the multiplexer 454 and sends the selected data to the subtraction component 464. The multiplexer 458 receives the selected rounds from the multiplexer 456 and receives input data from the P3 450c, P7 45〇g, and p5 emblems. The multiplexer sends the output data to subtraction component 464, subtraction 38 200816082 S3U06-0022I00-TW 24598 twf.doc/p, and 464 subtracts the received data and sends the data to shifter 470 and adder 472 . The shifter 47 shifts the received data to the left by two bits and transmits the shifted data to the adder 472, which adds the received data and sends the result to the skip block 48A. In addition, subtraction component 462 receives the data from P4 450d and P5 450e, subtracts the received data, and sends the result to shifter 4. Shift Zhai 468 shifts the received data to the right by one bit, and outputs this data as a Hung Clip data clip for input to the clamp component 446 and the multiplexer.

In addition, 'P4 450d is sent to jump block 476 and p3 45〇e data is sent to jump block 478. X Figure 7D is a continuation of the Figures 7A-7C. More specifically, as in the embodiment of Figure 7D, subtraction component 486 receives data from skip block 482 and jump block 484. Subtraction component 486 subtracts the received data and sends the result to shifter 488. The shifter 488 shifts the received data to the right by three bits and sends the result to A1 490a, A2 490b, and AO 490c. In addition, the multiplexer 496 receives the input data "〇,, and "d". This operation may include:

If (Do-filter) { P4[I] = P4[I] - D[I] P5[I] = P5[I] +D[I] } The multiplexer 496 selects the desired result via the do-filter selection input. . The result is sent to the subtraction component 5〇〇. Subtraction component 5 also receives data from jump block 492 (via jump block 476, Figure 7C), subtracts the received data and sends the result to P4 45〇d. 39 200816082 S3U06-OO22IOO-TW 24598twf.doc/p The multiplexer 498 also receives "〇" and "d" as inputs and do-fllter as a selection input. The multiplexer 498 multiplexes this data and sends the result to the adder 502. Adder 502 also receives data from jump block 494 (via jump block 478, Figure 7C), adds the received input, and sends the result to P5 450e. Figure 8 is a block diagram of a logic block that can be used to perform a sum of absolute difference (SAD) calculation in a computational architecture, such as the computational architecture of Figure 2. More specifically, as in the embodiment of Fig. 8, component 5〇4 receives a portion of 32-bit data a[31:0] and a 32-bit data B file. The component 5〇4 is judged if (C)s = Not (S) + 1 then A - B or not, and the output is supplied to the adder 512. Similarly, the 'component 506 receives the A data and the B data, and sends the output to the adder 512 based on a determination similar to the component 5〇4, except that the a data and the B data received by the component 5〇6 are [23:16]. In addition to the portion of the bit, the poor material received relative to the component class is the [31:24] bit portion. Similarly, component 5〇8 receives the data of the [15··8] bit portion, performs a similarity to components 5〇4 and 5〇6, and sends the result to adder 512. The component receives the [7:〇] bit; ^ 504'506 508 sends the result to the adder 512. In addition, components 5M, 516, 518, and 52〇 receive the 32-bit (fourth) portion of := 63:32] (as opposed to (4) where the component is smeared [31.G]. More specifically, the data of the m.wi/six-A and Ή 15 T 131.24] sections of the data A and the data B are received. The component performs the red-hand calculation as discussed above and sends the 8-bit result to 40 200816082 S3U06-0022I00-TW 24598twf.doc/p adder 522. Similarly, component 516 receives the data for the [23:16] bit portion, performs a similar calculation, and sends the resulting data to adder 522. The component 518 receives the data in the data A and the data B in the pseudo-bit portion as described above, processes the received data, and transmits the result to the adder 522. The component 520 receives the data A and the [7: 〇] bit unit in the data 3 as discussed above.

The data is processed, the received data is processed, and the result is sent to the adder 522 〇 W component 524-530 receives the A data and the 32 bits of the [95:64] bit portion of the B data. More specifically, component 524 receives [31:24] bits, component 526 receives [23·16] bits, component 528 receives [15:8] bits, and component 530 receives [7:0] bits. data of. Upon receipt of this material, component 524 530 can be used to process the received lean material, which can then be sent to adder 532 as described above. Similarly, component 534_54() receives the 32-bit data of the [127:96] bit portion of the a and B data. More specifically, component 534 receives the A data and the data of the [31:24] bit portion of B. Component 536 receives the data of the [23:16] bit portion, component 538 is connected = [15·8] The data of the bit portion, component 540 receives the data of the [7:〇] bit portion. The received data is processed as discussed above and sent to adder 541. In addition, adders 512, 522, 532, and 542 add '' the received data' and send the 10-bit result to adder 544. Adder 544 adds the received data and sends the 12-bit data to the output. Figure 9 is a flow diagram similar to another embodiment of the process shown in Figure 8 that can be used to perform an absolute difference sum (s) meter. More specifically, as shown in Fig. 9, the definition of 'i' is the block size BlkSize and the suma initialization 41 200816082 S3U06-0022I00-TW 24598twf.doc/p is "0" (block 550). First determine if i is greater than "〇" (block 552), if i is greater than "〇", then vecx[i] = Tabelx[i], vecy[i]= Tabely[i], vectx = mv-x+vecx[i And vecty = mv_y + vecy[i] (block 554). The address can then be calculated using vectx and vecty, and 4x4 memory data (byte alignment) can also be extracted from Predlmage (block * 556). 128-bit predictive data can be sent to SAD 44 (see Figure 8), such as

As explained in block 558. Additionally, block 560 can receive the block data and calculate the bit address. At block 560, 4x4 memory data may also be extracted from the Rephness and byte alignment performed. The 128-bit Ref[i] data can then be sent to the SAD 44 (block 558). The sum value can be sent from SAD 44 to block 562 where the sum value suma is increased by "1" and i is decreased by "丨". It can then be determined if the sum value suma is greater than the threshold (block 564). If so, the process can be stopped; on the other hand, if the right sum value suma is not greater than the threshold, then the process can return to block 552 to determine if i is greater than 〇. If i is not greater than 〇, the process can end. Figure 10A is a block diagram of various components that may be used in a deblocking operation, such as may be performed in the computer rack of Figure 2. As shown in the embodiment of FIG. 1A, ALU 580 receives input data p2 and p〇 and sends the data to absolute value component 586. The absolute value component 586 calculates the absolute value of the received data and the output data ap' decision component 590 determines if % is less than p and sends the data to jump block 596. The ALU 58〇 also sends the data to the jump block 594. Similarly, ALU 582 receives data from q〇 and q2. After calculating the result, alu 582 develops the bait material to an absolute value 588, and the absolute value component determines the absolute value of the received data and sends the % to the decision component view. Decision Group 42 200816082 S3U06-0022I00-TW 24598twf.doc/p 592 determines if aq is less than p and sends the data to jump block 598. The ALU 600 receives the data from q〇 and p0, calculates the result, and sends the result to the absolute value component 606. The absolute value component 6〇6 determines the absolute value of the received data&apos; and sends it to decision component 612. Decision component 612 determines if the received value is less than a and sends the result to the AND gate (4). The ALU 602 receives the data from the ρ 〇 and calculates the result and sends the result to the absolute value component 608. The absolute value component 6〇8 determines the absolute value of the received data and sends this value to decision component 614. Decision component 614 determines that the received dump is profit, is in beta, and sends the knot to and out (four). The auj 604 receives the data from q〇 and ql, calculates the result, and sends the result to the absolute value component 610. Absolute value component 610 determines the absolute value of the received data and sends the result to decision component 616. Decision component 616 determines if the received data is less than β and sends the result to AND gate 62. In addition, the gate 620 receives the data from the component 618, and the determining component receives the data and determines whether the data is not equal to zero. Figure 10B is a continuation of the diagram of Figure 10A. More specifically, ALU 622 receives data from pi and ql, calculates the results, and sends the data to ALU 624. ALU 624 also receives data from jump block 646 (via ALU 580 of Figure 1A) and 4-bit data at the carry input. The ALu 624 then counts the results and sends the result to the shifter 626, which shifts the received data to the right by three bits. The shifter 626 then sends the data to the clip 3 ( clip3 ) component 628 ' dip3 component 6 also receives data from the skip block 630 (via the ALU 744 of Figure 10D, described in more detail below). The clip3 component 628 sends the data to the multiplexer 634 and sent to, not (not), gate 43 200816082 S3U06-0022I00-TW 24598twf.doc / p 632. Non-gate 632 reverses the received data, and sends the inverted data to multiplexer 634. multiplexer The 634 also receives the "data" at the selection input and sends the selected data to the ALU 636. The ALU 636 also receives data from the multiplexer 640. The multiplexer 640 receives the data from q〇 and p0, and receives the data from the color 叩Select input. The carry input of ALU 636 receives data from multiplexer 642. Multiplexer 642 receives "1" and "〇,, and !left-t〇p data. ALU 636 sends the result to SAT (0,255) 638, SAT ( 〇, 255 ) 638 sends the data to jump block 644 (continued at multiplexer 79 ,, Figure 10E) 〇 In addition, ALU 648 receives data from q〇 and p0 and receives a bit at the select input. Data, ALU 648 calculates the result and sends this data to shifter 65 0. The shifter 650 shifts the received data to the right by one bit and transmits the shifted data to the ALU 652. Similarly, the multiplexer 656 receives the data from pi and ql and the !left-t〇p Select input, multiplex determines 656 the result, and sends the result to shifter 658. The shifter shifts the received data one bit to the left and sends the shifted data to ALU 652, ALU 652 calculates the result The data is sent to the ALU 6 illusion. The ALU 662 also receives data from the multiplexer 660, and the multiplexer 66 receives the data from q2 and p2 and from the hop block 680 (via the non-gate 802 of Figure 〇E) 〇ALU 662 The data is sent to the shifter 6 and the data is shifted to the right by one bit, and the shifted data is sent to the clip 3 component 668. The clip3 component The 668 also receives the tc〇 and sends the data to the ALU 670. The ALU 670 also receives 44 from the multiplexer 656. 200816082 S3U06-0022I00-TW 24598twf.doc/p A bill of materials, the result is sent to the multiplexer 672 The multiplexer 672 also receives data from the 868 device and receives data from the hop block 678 (via the map) 10E multiplexer 754) and sends the data to jump block 674. Figure 10C is a continuation of Figures iA and Figure 10B. As in the embodiment of FIG. 1C, multiplexer 682 receives data from p2, pl, and !leftJ〇p, and sends the selected lean material to adder 706. The multiplexer 684 receives pi and p 〇 with !left one top and sends the result to the shifter 7 〇〇. The shifter 7 shifts the received data one bit to the left and sends it to the adder 7〇6. Multi-tool 686 from p〇 and ql and! leftJ〇p receives the data. The multiplexer 6% sends the data to the shifter 702, which shifts the received data to the left by the 'bit' and transmits the shifted data to the adder 7〇6. Duplex Cry (10) Receives data from q0 and ql and !leftJ〇p and moves the selected data to the left by two bits: and develops it to adder 706. The multiplexer_self and ^t_t〇P receive the data and send the data to the adder 7〇 q 7〇6 also receives the 4 input method of the carry input terminal 7〇8. U and will start to jump block. Similarly, multiplexer 691 receives 2 alternative results will be fine to _tGp and send the selected result to addition P ' P〇 from q〇, ql and ! Left~top receives caution button, .... 694 hours to adder _. Duplicate crying pro- stipulations (4) Select a result to send it to select the desired result; send = two: q2 and · 丨1efu〇p 'and receive the 2-bit of the carry input and ": two also 45 200816082 S3U06- 〇〇22I〇〇.tW 24598twf.doc/p „ / worker 712 receives P3, q3, and !left-t0P and sends the result to Xi Li TM 722. Shift state 722 shifts the received data one bit to the left and sends it to adder 726. The multiplexer 714 receives p2, q2, and !left_top' and sends the selected result to the shifter 724 and the addition cry _ 726. The shifter 724 shifts the received data one bit to the left and sends the result of the shift to the adder 726. The multiplexer 716 receives qi and !left_top and sends the selected result to the adder 726. The multiplexer 7i8 接收 receives p0, 矽, and 丨left_t〇P, and sends the selected result to the adder 726. The multiplexer 72 receives p0, q0, and 丨left_t叩 and sends the selected result to the adder 726. The adder 726 receives the four bits at the carry input and adds the received data, and the summed data is sent to the skip block 73. Figure 10D is a continuation of the Figures 10A-10C. More specifically, as in the embodiment of FIG. 10D, alpha table 750 receives in (jexA and output a. beta table 748 receives hidexB and outputs the data to zero extension (Zer〇Extend) component 752, which outputs p. Similarly, multiplexer 736 receives "1" and "〇," and data from jump block 732 (via decision block 59 of Figure iA), and selects the result to send it to ALU 740. Multiplexer 738 also Receive "1" and ''〇, and data from jump block 734 (via decision block 592 of Figure iA) and send the selected result to ALU 740. ALU 740 calculates the result and sends the data to multiplexer 742 The multiplexer 742 also receives the "Γ and chroma edge flag data, and selects the result and sends it to the ALU 744. The ALU 744 also receives the teG, calculates the result te, and sends the result to the jump block 746. 46 200816082 S3U06-0022I00-TW 24598twf.doc/p Figure 10E is a continuation of the Figures 10A-10D. More specifically, as in the embodiment of Figure 10E, the multiplexer 754 receives the relationship "ChromaEdgeFlag = 0" &amp;&amp;(ap&lt;p)" related materials, and The relationship "ChromaEdgeFlag==0) &amp;&amp;(%&lt;β), 'relevant data, and receives data from non-component 802, and sends the selected data to jump block 756 (to multiplexer 672 of Figure 10B) ).

In addition, the multi-mode 780 receives information related to the relationship "chromaEdgeFlag=0) &amp;&(ap&lt;p) &amp;&(abs(pO-qO)&lt;((a»2)+2)" And the information related to the relationship "ChromaEdgeFlag==〇"&amp;&(aq&lt;p)&amp;&amp;(abs(p0_q0)&lt; ((α»2) +2))", multiplexer 78〇 The selection input is also received from the non-component 8〇2, and the desired result is selected accordingly and sent to the multiplexers 782, 784, and 786. A multi-mode 757 receives data from pi, qi, and non-component 8〇2, sends the selected lean material to shifter 763, which shifts the received data one bit to the left and sends it to the addition. 774. The multiplexer 759 receives p0, q0 and data from the non-component 802 and sends the selected data to the adder 774~. The multiplexer 761 receives data from ql, pl, and non-component 8〇2 and is developed to add 11 774. Addition 11 774 also receives the two bits of data at the carry input and sends the output to multiplexer 782. The law-shift: Receiver data is received from the jump block 758 (the data added via the map is shifted to the right by three bits, then the shifted secondary 782 is received. The shift 11 766 is received from the jump block 760; the adder 698 of the file ) and shift the received data to the right by two digits, and read the recorded data to station the multiplex H784. Transfer ^ 47 200816082 S3U06-0022I00-TW 24598 tw£doc/p 768 Receive data from jump block 762 (adder 726 from Figure 1〇c) and shift the received data to the right by three bits, then shift the shift The data is sent to the multiplexer 786. As also discussed above, multiplexer 782 receives data from shifter 764 and adder: 782 and multiplexer 780, selects the result from this data, and sends i - to multiplexer 790. Similarly, multiplexer 784 is redundant from the shifter; multiplexer 780 and multiplexer 776 receive the data. The multiplexer 776 receives pi, ql, and data from the non-component 802, and then sends the selected result to the multiplexer 798. The multiplexer 786 receives the data from the shifter 768, the multiplexer 78, and the multiplexed cry. Multiplexer 778 receives p2, q2a, and data from non-components 8〇2. The multi-mode 786 sends the selected data to the multiplexer 8 (8). As discussed above, multiplexer 790 receives data from multiplexer 782. In addition, multiplexer 790 receives data from jump block 772 (via SAT component 638 of Figure IB) and multiplexer 794. The multiplexer 794 receives data of p〇, q〇 and non-component 802. The multiplexer 79〇 also receives the bSn &amp; nfllterSampleFlag data as a selection input and sends the selected data to the buffers 808 and 810. Similarly, multiplexer 798 receives data from multiplexer 784, jump block 755 (which is multiplexer 674 of Figure 10B), and multiplexer 792, and selects the input bSn &amp; nfilterSampleFlag data. The multiplexer 792 receives the data of P1, qi, and non-components 8〇2. The multiplexer 798 sends the tribute to the buffers 806 and 812. Similarly, the multiplexer 8 receives data from the 868 and receives the bSn &amp; nfilterSampleFlag data as a selection input. In addition, the multiplexer 8 receives data from the multiplexer 788. § 788 receives data from p2, q2, and non-component 802. Multiplex 48 200816082 S3UO6.O022IOO.TW 24598twf.doc/p 800 selects the desired data and sends the data to buffers 806 and 814. Buffers 804-814 also receive data from non-component 802 and send the data to p2, pi, p〇, q〇, ql, and q2, respectively. 11 is a flow diagram illustrating an embodiment of a process that may be used to execute data in a computing architecture, such as the computing architecture of FIG. 2. The texture block of the embodiment of Figure 11 - odd block 880 of address generator TAG and even block 882 (see also 150 of Figure 2) receive data from output port 144 (Figure 2). Then Xin generates the address for the received data' and the process proceeds to Texture Cache Memory and Controller (TCC) 884, 886 (see also Figures 2, 166). The data can then be sent to cache memory 890 and Texture Cache First In First Out (TFF) 888, 892, which can be used to act as a delay queue/buffer. The data is then sent to the texture filtering unit 894, 896 (Texture Filter Unit, TFU, see also Figure 2, 168). Once the data has been filtered, TFU 894 and 896 send the data to γρυ 898, 900 (see also Figure 2, 199). Depending on whether the instruction requires dynamic compensation filtering, texture cache memory filtering, mutual deblocking filtering, and/or absolute difference sum, the data can be sent to different VPUs and/or different parts of the same VPU. After processing the received data, the VPU 898, 900 can transmit the data to the outputs of the input ports 902, 904 (see also Figures 2, 142). Embodiments disclosed herein can be implemented in hardware, software, firmware, or a combination thereof. At least one embodiment disclosed herein is stored in a memory and implemented in software and/or firmware executed by an appropriate instruction execution system. If implemented in hardware, as in an alternative embodiment, the embodiments disclosed herein may be implemented in any one or combination of the following techniques: • with 49 20081 9 no tw 24598_· for data signals Discrete logic circuit for logic function logic gate, special application integrated circuit (ASIC) with appropriate combination logic gate, programmable gate array (PGA), field programmable gate array (FPGA), etc. It should be noted that the flowcharts included herein represent software and/or hardware: the architecture, functionality, and operation of possible embodiments. In this regard, each block may be interpreted as representing a module, section, or portion of code that includes one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative embodiments, the functions noted in the blocks may be unusual and/or non-existent. For example, two blocks of consecutive presentations may be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending on the functionality included. It should be noted that the program of the program in this article (which may include an ordered list of executable instructions for the actual work) can be embodied in the instruction: device or device (such as the secret of the computer) Anything that is used or combined with any of the items described above may be defamatory, with or without a command execution system, a skirt or device extraction instruction. In the context of this document, "computer-readable medium" - any component of a program that transmits or transmits a mail order, a device, or a program for its use. Computer readable or semiconductor system, magnetic, optical, electromagnetic, infrared-read only;:=))(=^^^ 50 200816082 S3U06-0022I00-TW 24598twf.doc/p Remembrance (EPROM or flash memory) (Electronic), optical fiber (optical), and portable compact disk read-only memory (CDROM) (light). Additionally, the scope of certain embodiments of the disclosure may include media embodied in hardware or software. The functions described in the logic embodied in • • should also (4) conditional language (such as) especially “may (eanH. might or may), unless otherwise specifically stated or otherwise understood in the context of use, otherwise The use of certain features, elements, and/or steps in the present invention is intended to be inconsistent with respect to certain embodiments. Therefore, such conditional language is not intended to suggest that features, components, and/or steps are always It is required by one or more specific embodiments, or implies that one or more specific embodiments are necessary, including with or without the user's logic for decision making in the case of a user's rotation or prompting', in any particular embodiment. Whether these features will be included or implemented The elements of the above-described embodiments are merely illustrative of the possible embodiments of the embodiments, and are merely illustrative of the principles of the disclosure, without departing from the spirit of the disclosure and the scope of the disclosure. Many variations and modifications are possible in the above-described embodiments. All such modifications and variations are intended to be included within the scope of the disclosure herein. [Simplified Schematic] Figure 1 is a calculation for processing video data. Embodiments of the architecture. Figure 2 is an embodiment of a computing architecture incorporating a video processing unit (VPU) similar to the architecture of Figure 2. Figure 3 is a process for processing video and graphics data, such as in the computing architecture of Figure 2. Flowchart embodiment. 51 200816082 S3U06-0022I00-TW 24598 TW/doc Figure 4A is a functional flow diagram embodiment of a data flow in a computing device, such as a computing device having the computing architecture of Figure 2. Figure 4B is a A continuation of the functional flow diagram of Figure 4A. Figure 4C is a continuation of the functional flow private diagram of Figures 4A and 4B. Figure 5A is a dynamic compression (MC) that can be used to provide dynamic compression, such as in the computing architecture of Figure 2. And/or a functional block diagram of a component embodiment of a discrete cosine transform (DCT) operation.

Figure 5B is a continuation of the diagram of Figure 5A. Figure 5C is a continuation of the Figures 5A and 5B. Figure 5D is a continuation of the Figures 5A-5C. Figure 5E is a continuation of the Figures 5A-5D. Figure 5F is an embodiment of a general view of the components of Figures 5A-5E. Figure 6 is a functional block diagram of a pixel processing engine that can be used in a computing architecture, such as the computing architecture of Figure 2. , 7A is a functional block diagram illustrating the components that can be used in a VC] in-loop filter, such as in the different architecture of Figure 2. Figure 7B is a continuation of the Figure 7A.计算 Calculation Architecture) Process of Neutralization Calculation FIG. 7C is a continuation of the diagrams of FIGS. 7A and 7B. FIG. 7D is a continuation of the diagrams of FIGS. 7A-7C. Figure 8 is a block diagram of components that can be used in a computing architecture, such as Figure 2 to perform absolute differences and calculations. Figure 9 is a flow diagram similar to Figure 8 that can be used to perform an absolute embodiment. The figure illustrates that it can be used in a deblocking operation. FIG. 10B is a continuation of the diagram of FIG. 10A. FIG. 10C is a continuation of the diagram of FIG. 10A. FIG. 10C is a continuation of the diagram of FIG. 10A. FIG. Continuation of Figure 10D. Figure 10D is a continuation of the Figures 10A-10C. Figure 10E is a continuation of Figures 10A-10D. Figure 11 is a diagram that can be used in a computing architecture, such as the computing architecture of Figure 2. Flow chart of an embodiment of the process of data. [Explanation of main component symbols] 88, 102: Internal logic analyzer

90, 104: Bus interface unit BIU

106a, 106b, 106c, 106d: memory interface unit MIU 108: memory access port 110, 116: data stream memory 112: vertex cache memory 114: L2 cache memory 118: with cache memory EUP Controller 120 of the Subsystem: Command Stream Processor (CSP) Front End 122: 3D and Status Component 124: 2D Pre-Component 126: 2D First In First Out (FIFO) Component 128: CSP Backend/ZL1 Cache Memory 130: Definition and Model Texture Processor 132: Advanced Encryption System (AES) Encryption/Decryption Component 134: Triangle and Attribute Configuration Unit 53 200816082 S3U06-0022I00-TW 24598twf.doc/p 136: Span Brick Generator 138: ZL1 140 : ZL2 142, 902, 904: Input port 144: Output port 146: Set unit EUP/BW compressor 148: Z and ST cache memory

150: texture address generator TAG 152: D cache memory 154: 2D processing component 156: front wrapper 158: interpolator 160: post wrapper 162: write back unit 164a, 164b: memory access unit 166, 884, 886: texture cache memory and controller tcc

168, 894, 896 · Texture Filtering Unit TFU 199, 898, 900: Video Processing Unit Vpu 234: Encrypted Bit Stream 236: Decryption Component 238: Coded Bit Stream 240·VLD, Huffman Stone Horse , CAVLC, CABAC 242: EUPTAG interface 244: image header 54 200816082 S3UU6-0022I00-TW 24598twf.doc/p 246a, 246b, 246c, 246n: memory buffer MB 250, 252, 254, 256, 258 , 260, 270, 272, 274, 276, 344a~i, 346a~i, 348a~i, 362j~r, 366j~r, 368a~r, 372b~r, 376b~j, 474, 476, 478 , 480, 482, 484, 492, 494, 594, 596, 598, 630, 644, 646, 674, 678, 680, 708, 710, .730, 732, 734, 746, 755, 756, 758, 760, 762, 770, k 772: Jump Block 262: Anti-DC/AC Prediction Component® 264 · Anti-Scan Anti-Q Component 265: Switch 266: Encoding Pattern Block Reconstruction Component 280: Filter Component 282: MC Filter 284: Reconstruction Reference Component 286: Encoding Pattern Block Reconstruction 288: Switch Component • 29〇: Reconstruction Framework Component 292: Deblocking and Delooping Filter 294: Deinterleaving Component 296: Inverse Transform Component/ In-loop filters 298, 330, 442, 472, 502, 512, 522, 532, 542, 544, 698, 706, 726, 774 · Adders 300, 302, 304, 306, 308, 310, 312, 324 : Z] delay component 55 200816082 S3U06-G〇22I00-TW 24598twf.doc/p 314a, 314b, 314c, 314d: PE 316: Z_3 delay component 320: Z_2 delay component 318, 322, 326, 328, 342, 342a~ I, 369, 369a~i,

382, 382a~d, 390, 390a~d, 400, 402, 404, 406, 408, 420, 422, 424, 428, 452, 454, 456, 458, 496, 498, 634, 640, 642, 656, 660, 672, 682, 684, 686, 690, 691, 692, 694, 696, 712, 714, 716, 718, 720, 736, 738, 742, 754, 757, 759, 761, 776, 778, 780, 782, 784, 786, 788, 790, 792, 794, 796, 798, 800: multiplexer 332: N shifters 340, 304a~1: memory buffers 350, 350a~i: memory B, Slot 360: transposed network 370, 370a~i: FIR filter blocks 380, 380b~j: memory buffer c, slots 384, 384a~d, 580, 582, 600, 602, 604, 622, 624, 636, 648, 652, 662, 670, 740, 744, ALU 386, 386a~d, 412, 440, 444, 466, 468, 470, 488, 626, 650, 658, 664, 700, 702, 704, 722, 724, 763, 764, 766, 768: shifter 388, 388a~d · · Z block 410: multiplier 426: logic or gate 56 200816082 〇ju υυ-υ u22I00-TW 24598twf.doc/p 430, 432, 586, 606, 608, 610: absolute value component 434: minimum component 436 : 2 Carry complement component 438, 460, 462, 464, 486, 500: subtraction component 446 · · clamp component 450a~h : P1~8 data 490a : A1 490b : A2

• 490c: AO 504, 506, 508, 510, 514, 516, 518, 520, 524, 526, 528, 530, 534, 536, 538, 540: components 590, 592, 612, 614, 616, 618: decision Component 620: and gates 628, 668·· clip3 component 632: non-gate 638: SAT component • 748: β table 750: α table 752 • service extension component 802: non-components 804, 806, 808, 810, 812, 814: Buffers 880, 882: Texture Address Generator - TAG Blocks 888, 891: Texture Filtering First In First Out Components TFF 890: Cache Memory 57

Claims (1)

200816082 S3UU6-UU22I00-TW 24598twf.doc/p X. Patent application scope: • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • One of the formats of the video, wherein the instruction converts the Weibo data; the rate and the conversion logic are based on the surface information: the heterogeneous format carries the 14-wave logic 2. As described in the patent scope 1, the filter can be executed as the filter logic circuit A dynamic compensation filter falls. ^ The programmable video processing unit of the rUf patent range 2, in the bean format, operates in a two-pass mode of one-two vertical filtering and horizontal filtering. The program video processing unit of Shen Nawei 2 series, when the vc-i format is 1/2 degree in the basin, the filtering logic circuit: (6) is taken off, and the Lai type is V (H format 1/) The production logic is operated in a double-cube mode. 5. If you apply for the general-purpose video processing unit, the =-type indication is H. 264 format quarter-pixel, the occupational wave The logic circuit operates in the party mode; the mode indicates that the block is Η·264 format 八8守, far; the wave logic circuit operates in a chromaticity mode. ” =#6·, as described in the patent application scope The programmable video processing unit, wherein the mode indicates that the interception bit is in the MPEG-2 format, the conversion logic circuit performs a two-segment 58 200816082 s^uuo-uu22I〇〇-TW 24598twf.doc/p scattered cosine inverse conversion operation. The programmable video processing unit of claim 1, wherein the mode indicates that the interception is in the VC-ι and Η·264 formats, the conversion logic circuit performs an integer conversion operation. The programmable video processing unit of 1 is further included A deblocking logic circuit for performing intra-loop filtering. 9. A programmable video processing unit comprising: An identification logic circuit for identifying a format of the video data; a dynamic compensation logic circuit for performing a dynamic compensation operation; a discrete cosine inverse conversion logic circuit for performing a discrete cosine inverse conversion operation; and, an integer conversion avoidance The circuit is configured to perform an integer conversion operation. The discrete cosine inverse conversion logic circuit and the integer conversion logic circuit are respectively turned off according to the identification result of the identification logic circuit. 10. The programmable video processing unit according to claim 9, wherein the identification result in the bean is V (the inverse conversion logic circuit of the M and the 264 264 format is closed. _ Zheng Yuxian 11. If the patent application scope 9 The programmable video processing bean, (4) When the identification result is Xia-2 format, the integer logic circuit is turned off: 兮 # # # #9 9 The programmable video processing unit, in: Hai identification I. For both V (M and Η. 264 formats), the more self-human logic circuit is used to perform the intra-wave operation in the first loop. 3 Ghost 13. The identification node in the programmable video as described in claim 9 _PEG_2 Grid; cut, the levy _ road = line = 59 200816082 W2I00-TW 24598twf.doc / p in a two-way mode. I4. In the programmable video as described in claim 9 the identification result is V (M In the format, the _ ^ ς column mode is _ : bilinear mode and bicubic mode ^ is in the lower I5 · as described in the scope of claim 9 in the process... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The method includes: receiving an instruction; receiving video data selected from at least one of two formats; filtering the video data according to the instruction; and converting the video data according to the instruction; wherein the instruction includes a pattern recognition field and a video The data step is mixed with Wei Xun: the format and conversion of the miscellaneous. 17 The steps of filtering the T-data as described in the scope of application 16 include execution-dynamic supplementation method, which is the mode recognition method, in the dual-pass mode. The operation of the video data processing method described in Patent Requirement No. 17, wherein the dynamic compensation wave operates in the format when the work s does not block the Yangshuo style. 1/4 quasi-degree OA, , ^ and cubic chess type. The video data processing method described in the patent Zhuo Yuwei 17, wherein 60 200816082 uuo-uu22I00-TW 24598twf, doc / p the mode indication field is U. 264 When the format is quarter-pixel, the dynamic compensation filter is operated in a brightness mode; the mode indicates that the block is H 264 format octet 4, and the motion compensation chop operation operates in a chrominance mode. Wai video data processing method of claim 16, beans ^ == _ is MPEG-2 format 'of the step depends on the cooked containing a guess 22. If the pattern of the patent application is as described in claim 16 of the patent, the pattern recognition block is a spell-1 and 11 264 prescription, and the middle step includes executing the m 4 format of the towel, and the conversion 23 is as claimed in the patent scope 16 The inclusion-execution domain Wei wave is included. &amp; 视^顺财法,更包 61