TW200803525A - Deblockings filter for video decoding, video decoders and graphic processing units - Google Patents

Abstract

An exemplary video decoder comprises: an entropy decoder; a spatial decoder; combining logic; and an inloop deblocking filter. The entropy decoder receives an incoming coded bit stream. The spatial decoder receives the output of the entropy encoder and produces an encoded picture comprising a plurality of pixels. The combining logic combines a current picture with a prediction picture to produce a combined picture. The inloop deblocking filter receives the combined picture. The inloop deblocking filter comprises: logic configured to filter a predefined pixel group; and logic configured to filter each of the remaining pixel groups in the plurality after the predefined pixel group, according to a corresponding set of taps in a plurality of sets of taps, if the predefined pixel group meets a criteria.

Description

200803525 IX. Invention description: _ - . V: ·< . [Technical field of violent storm] .!,: Winning:: The invention relates to image compression and decompression, and especially Weng Guan. :. ^ The graphics of the feature are processed first. ·: "r; . :. -: ,·:,- ·: · ;*" ' > :.· . -, * , . , : ·: /, [Prior Art] ~: ' ^仏The human t-brain is used for various entertainment purposes. Road;:: Ω 矣埤 用品 5 5, roughly divided into two categories: those using computer-generated graphics, (computer-generated graphics), such as computer games; and those using compressed video streams, For example, pre-recorded programs onto digital video discs (DVDs), or digital programming from cable television or zinc-based companies to a set-top box. The second type also includes a coded analog video stream', for example, implemented by a digital video recorder (DVR). φ Computer graphics are usually generated by a graphics processing unit (GPU). A graphics processing unit is a special type of microprocessor built on computer game consoles and some personal computers. A graphics processing unit is optimized to quickly perform three-dimensional primitive objects, such as triangles, quads, and the like. These basic objects are described by a plurality of vertices, where each vertex has an attribute (e.g., a color) and texture can be applied to the base object. The result is a two-dimensional array of 6Client's Docket N〇.: S3U06-0023 TT's Docket No: 0608-A41202-TW/fmal/林璟辉/2007/05/31 6 200803525 pixels), display On a computer monitor or monitor. The encoding and decoding of video data streams involve different kinds of operations, such as discrete cosine transform (discrete\ci^ine transform), motion estimation (motion: "太#: motion compensation: motion compensation, go to the box dare :H wave: (^uocking f 11 ter). These calculations are usually made up of general-purpose CPUs (Cpu). Special hard-wired logic circuits:,|Specially applied to the integrated circuit (AS』c, Application specific integrated circuit), therefore, requires multiple computing platforms to meet their entertainment needs. Silver: There is a need for a single computing platform that can handle computer graphics and video encoding/decoding. ^ [Summary] The embodiment provides a system and method for video frame-removing block effect. - The lining transcoding _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Whether to standardize the logic of the standard (4); set to # to achieve the standard first record of the pixel group of the pixel group; and set to achieve the standard, according to the complex array filter unit (set f taps) - the corresponding group filter 'wave unit' is a logic circuit that sequentially filters the remaining pixel groups in the plurality of pixel groups. An exemplary video decoder comprises: "entropy decoder, 4 de-combination logic circuits And - the in-loop de-blocking chopper. The picking = t ̄ ̄ - inputting the bit stream. The spatial decoder receives the entropy solution containing a plurality of pixels - _ slice. The combination S Docket No: 0608-A41202-TW/fmal/林璟辉/2007/05/31 200803525 The logic circuit combines a current picture with a predicted picture to generate a combined picture. The evaluation channel pairs the demodulation filter to receive the combined picture.靡 & inner square block effect 翁 器 contains: set a pair of predetermined pixel group filter _ logic # 丨 ;; friend meal 铖% the predetermined pixel group reaches a standard _, grain data, in the complex wave 箪 yuan The flashing = the corresponding group of filtering units, the logic circuit of the residual image group filtering is applied to the complex group image. The V y special T pain after the exemplary servant processing unit includes a main processing interface and a video, Acceleration unit. The main processing interface receives at least one The acceleration command. The, -, * video power idle unit, for: at least ": video acceleration command. The video acceleration unit includes a loop-in-square block effect filter. Included: a logic circuit configured to determine whether a pixel of a predetermined pixel group of a plurality of pixel groups reaches a first standard; a logic circuit configured to filter pixels of the predetermined pixel group when the first standard is reached; and setting When the first criterion is reached, the logic circuit for filtering the remaining pixel groups in the plurality of pixel groups is sequentially sequenced according to a corresponding group of filtering units in the set of taps. [Embodiment] A computing platform for video encoding/decoding Fig. 1 is a block diagram of an exemplary computing platform for graphics and video encoding and/or decoding. The system 100 includes a general purpose CPU 110 (hereinafter referred to as a main processor), a graphics processing unit (GPU) 120, a memory 130, and a bus bar 140. The graphics processing unit 120 includes a video acceleration unit (VPU) 150 that speeds up video encoding and/or decoding, as will be described later. Graphics processing unit 120 SClienfs Docket N〇.:S3U06-0023 TT's Docket N〇:0608-A41202-TW/fiml/林璟辉/2007/05/31 〇200803525 Video acceleration system can execute instructions on _ processing unit (10) . : China and Weixun speeded up Wei Weipu in memory 130: 3⁄4 Α ^: Ϊ Decode 16 々 t t 夷 器 1 1 1 1 1 1 1 1 1 1 1 1 1 Two:::丨,士f. ,: After a view of the device such as 180^, !^ 16〇, a, b_* ^^100 Figure, at the early mo main processor software (h〇st (3) Chi coffee so smart to perform video crane and / Or decoding, the graphics processing unit lion responds to these commands by accelerating a portion of the decoded gas 160. In some embodiments, only a small portion of the decoder 16 is executed on the main processing cry, and most of the solutions are (10) The execution by the _ processing unit (10) is under the overload of the driver. In this way, the computationally intensive bl〇cks that are often executed are unloaded to the graphics processing unit 120. The more complex operation is performed by the main processor '11执行 Execution. In some implementations, 'a dense computing function implemented by the graphics processing unit 12 包含 includes in-loop deblocking filtering, wave hardware acceleration logic (inl〇〇p debl〇cking filter hardware acceleration logic) 400, also known as in-loop block effect filter 400 or deblocking filter 4〇〇, which will be described later in conjunction with Figure 4. Another example of dense operation function is to determine the boundary strength of each filter (BS) ,boundar y strength) The above structure thus makes the following operations flexible. On the main processor HO, the decoder 160 performs some special functions of performing a shader program on a large block (for example, marc〇bl〇ck). Deblocking effect or 9Clienfs Docket N〇.:S3U06-0023 Open TT's Docket No:0008-A41202-TW/final/Lin Huanhui/2007/05/31 200803525 Boundary strength); or in the graphics processing unit 丨160, use dry r · 〗 · Most of the decoders on the screaming 扪 扪 官 官 官 官 : : : (: pipellni) 盥 盥 盥 盥 id id id id id 闽ΰ 闽ΰ , , , , , , , , , , , , , , , , , , ,亓] 9η child to block effect processing 傣 talk about the drinker 160: can be (thread) : :: # (four) • ' : , .., person ':: : - , 'V' „ ·:· - . ::::-;· ;·^;- : ·:: ,-. · Specially explain the video acceleration of the processing unit 120

$, yes and no, ‘this $known to the familiar components. 々 ·.〉:: ;-"· -;· ' V - ' ...... ' Video solution 2 picture system, the video decoder 16 〇 block diagram. In the special embodiment of Figure 2, the decoder (10) applies the touch-264 video compression gauge t "'the familiarizer should understand that the decoder (10) of Figure 2 is a preliminary representation of a video solution, the video solution Μ also said that it depends on the operation of other types of decoders of H 264, such as SMPTE V (M and mpeg_2 specifications. In addition, although it is shown as part of the graphics processing unit 12Q, those skilled in the art should also understand The disclosed portion of the decoder 160 can also be implemented in a manner other than a single processing unit, for example, a logic circuit that is independently present, a portion of a special application integrated circuit (ASIC), etc. The input bit stream 205 is firstly Entropy decoder (eni:r〇py dec〇der) 210. Entropy coding has the advantage of statistically statistic;redundancy: some patterns appear more often than other patterns, so shorter ones appear more often Code representation. Entropy coding includes Huffman coding and run-length encoding. After entropy coding, the resource lOClienfs Docket N〇.:S3U06-0023 TT's Docket No:0608-A41202-TW /fmal/林璟辉/2007/05/31 200803525 is processed by a spatial decoder (spa1; ial dec〇der) 215, which has a point of τ, in fact, the adjacent pixels in a graphic are usually _如·, Have

: Figure _ is buried as a smaller sub-region _, called a large square. The 10 compression specification uses a large block size of 16x16 pixels, while the other pressures use other sizes. The large squares in the graph 235 are combined with the information of the previously decoded graph items, which is called inter-prediction (inter predicrfci〇n) processing, or combined with the information of other large squares of the graph 235, called intra-picture prediction prediction) deal with. The input bit stream 2〇5 is decoded by the entropy decoder 2〇5, and inter-plane or in-plane prediction is applied according to each type of pattern. One - -: · _ When applying inter-picture prediction, the entropy decoder 21 generates a motion vector • (m〇ti〇n vector) 245 output. The motion vector 245 is used for the temporary two code, which has the advantage of T. In fact, many images in a series of graphs will have the same value. The change from -graphic to other graphics is encoded as moving in 245. Motion compensation block 250 combines one or more previously decoded graphics 255 with motion vector 245 to produce a prediction pattern (265). When applying the inter-plane prediction, the space-compensation block 270 combines the information from the adjacent large blocks with the large blocks in the graphic 235 to produce a predicted pattern (275). The combiner 280 will use the graphic 235 and the mode selector (m〇de seiect〇r) 285 1 IClient's Docket N〇.: S3U06_0023 TT's Docket No: 0608-A41202-TW/fmal/林璟辉/2〇〇7/〇5/31 The mode selector 285 uses the entropy decoded bitstream to determine the predictive graph (265) produced by the combiner 11 200803525-280 using the motion compensation block 250 or the predicted circular 4 swim generated using the spatial compensation block 270 5). , Bu, ' '"· , 3⁄4 : r..ry-y:.: > .: .. ir :, edit, program caused by discontinuity along the big square edge g and along the generous side ' ' ...· . . - 1 ν] ν'. : '·:'1 :::::: / 5 -·· ;;. . $ · The inside of the block is not continuous with the edge of the square (^r1; Ifac1:). As a result, in the decoding of the picture, the box has an "edge" and there is no such thing. Go to the block effect filter, '·· . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : The filter produces the decoded pattern _5 "Shu Lu' code next graph. : , : κ As discussed in connection with Figure 1, part of the decoder 160 is executed on the main processor n〇, and the decoder 16〇 There is also the advantage of providing video acceleration by graphics processing unit 120. In particular, in some embodiments, deblocking filter 290 uses one or more instructions provided by graphics processing unit 120 for relatively low usage. Filtering of computational cost. Deblocking chopper to block effect filter, waver 290 system - multi-cell filter, waver (multi_tap, which adjusts the pixel value of the edge of the sub-block based on the neighboring pixel value. It can be implemented according to decoder 16G The compression specification uses different embodiments of the deblocking chopper 290. Each specification uses different filter parameters, such as the size of the sub-block, the number of pixels updated by the job ambiguity, and the frequency of the ferrite application (eg, column or Every bank In addition, each specification uses a different filter ϋ length structure. Those skilled in the art should understand the multi-cell filter, and the structure of the specific unit will not be discussed here. By V (M rule · 定之方方12Client's Docket N〇.:S3U06 -0023 TT,s Docket No:0608-A41202-TW/final/林璟辉/2007/05/31 200803525 The block filter embodiment will be explained in conjunction with Figure 4. First,

·, W·' .:1"· :-,· ·.;-5'V.. ,.: Sub-block of the UP device: Yu Sulu umbilical combined with the third figure. , Spoel 3 shows the neighbors: nearly 4x4 sub-blocks (31〇, 320), definition = column R1 - R4 read the threat between the A it ^ , M VC-1 » ^ ^::: W P4V ^ Ii| is determined by the particular set of calculations and comparisons of pixels in the predetermined group. The skilled artist Lin _ these materials and ratios (4) are - (4) a set of taps ' and detailed calculations and comparisons will be discussed later in conjunction with Figure 5. The updated value is also based on the calculations performed on the predetermined group of pixels. The VC-1 filter processes the rightmost sub-block in an analogy manner, and determines if the primes 6, 7, and 8 reach the -standard' if the standard is reached. In other words, the [1 filter is a predetermined column of the predetermined column (10), and the pixels P4 and P5 are calculated according to the values of the predetermined pixels of the other groups in the same column. The value of P4 is based on the values of P, P2, P3, and P5. According to p6, p7, p8. The VC-1 conditionally updates the same group of predetermined pixels of the remaining columns based on the values calculated for the predetermined group of pixels (edge pixels p4, p5) '^ of the predetermined column (R3). As a result, P4 in R1 is updated based on ρι, p2, 兕 in R1. However, only P4 and P5 in R3 are updated. Similarly, P5 in R1 is updated based on P6, P7, and P8 in R1, but only P4 and P5 in R3 are updated. Columns 2 and 4 are also treated in a similar manner. On the other hand, some pixels of a pixel in a predetermined third column are BClienfs Docket N〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 13 200803525 Filtered Or updated, when the other pixels in the third column reach a standard. ', the iron 4 wave is involved in the comparison and calculation of these other pixels, counted in the / ':.:. Sound I Sen 2 (10) implementation: using a groundbreaking technology, Kang on the irrigation three i: according to the wave Miscellaneous and other storms filter. These pioneering sores will be combined with: 4, 5, 6A, 6D, and more detailed instructions. • · . , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Same-picture rotation (10): After the degree can also explain the line processing: horizontal edge. Those skilled in the art will also appreciate that although VC-1 uses the third column of the four columns as a predetermined column for determining the conditional update of other columns, the principles of this disclosure may be applied to embodiments using other predetermined columns (eg, The first column, the second column, etc.) can also be applied to other embodiments that form different numbers of sub-blocks. Similarly, those skilled in the art will appreciate that although VC-1 checks the value of a group of neighboring pixels to set the value of the pixel to be updated, the principle of exposing Φ can be applied to other pixels that have been tested and other pixels. The example has been set. For an example, Ρ2 and Ρ3 can be tested to determine the updated value of Ρ4. As another example, Ρ3 can be set according to the values of Ρ2 and Ρ4. The video acceleration unit 150 in the graphics processing unit 120 is an in-loop deblocking filter (IDF). For example, a block-effect filter in the loop of the VC-1 specification implements a hardware acceleration logic circuit. A graphics processing unit instruction implements this hardware acceleration logic circuit, which will be described later. The conventional method of implementing a VC-1 loop deblocking filter is to process each column/row in parallel because the same pixel calculation is in a 14Clienfs Docket N〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/ Fmal/林璟辉/2007/05/31 14 200803525, each column/row of sub-blocks is executed. This conventional method filters two adjacent 4x4 sub-blocks per cycle, but requires __increasing _:increased gate w, count. Relative 'push it:: hardware acceleration logic circuit 4 〇〇? _: miscellaneous: y:y:...:: column/row pixels, and if these: the wounded _ _ _ want:: to the standard, In the order of the order, r '*: handle the remaining: the three columns/rows that are not:. : This open _ mine _ ^, logical scale, which replicates the function of each column / line.乂(:-1: In-loop de-blocking chopper accelerating logic circuit 4 〇〇 sequence processing each of the two * 10 adjacent ^ 4x4 sub-blocks filtered. This longer filtering time and graphics processing unit 120 The instruction cycle is consistent, and the faster filtering of the conventional method is actually faster than the required speed, resulting in waste on the logic gate. Figure 4 is the hardware acceleration of the deblocking filter in the VC-1 loop. The hardware of the logic circuit 400 describes a list of virtual codes. Although not using a virtual hardware description language (HDL), such as Verilog and VHDL, a virtual code is used, and those skilled in the art should be familiar with these virtual codes. These individuals should be aware that when described in actual HDL, these codes should be compiled and then synthesized into the number of logic gate configurations that make up the portion of video acceleration unit 150. These individuals should be aware that these logic gates can be implemented in a variety of techniques, For example, a specific application integrated circuit (ASIC), programmable logic gate array (pga) or field programmed logic gate array (FPGA). 410 segments of this code Module definition (mocjule definition) vc-i loop deblocking filter hardware acceleration logic circuit 4 (10) has many input parameters. The sub-block to be filtered is the block parameter ISClicnVs Docket No.: S3U06-0023 TT's Docket No :0608-A41202-TW/fmaI/林璟辉/2007/05/31 200803525

(Block parameter) is regulated. If the vertical parameter (Vertical parametei^; 'true: (True), then the acceleration logic circuit 400 will see the side of the parameter as a good thing, see the "3rd picture", and perform the vertical edge 摅,: 3⁄4 storm w if vertical) rr error acceleration logic circuit 40G parameter view surface • reference block (: see, 3), (and perform horizontal edge _ filter _ edit:;, * Cheng Hao: type Pan Heng 7 area Fly ': Start f loop:) 'Set this back. The value of the parameter variable is the first time this time passes through this loop. When the circle is rounded, the reference is set to 3", so the 3u line is processed first. After the continuation of the replies to the iteration setting " loop parameters are 1, 2 and: 4. These parameters are taken in the vc-1 loop. The block effect filter state hardware acceleration logic circuit 400 is repeated 4 times, each time processing 8 pixels 'one of which can be a horizontal column or a vertical line, each column system It is processed by the line acceleration logic circuit 500 (see Figure 5). In some embodiments, the line acceleration logic circuit 5 is implemented as an HDL sub-module and will be described in conjunction with FIG. Section 430 tests the vertical parameters to determine the execution of vertical or horizontal edge filtering. Based on this result, the 8 elements of the row array variable are initialized from the row of the 4x8 input block or the 8x4 input block. Section 440 determines if the third line is processed by comparing the loop parameter to 3. If the loop parameter is 3, the other two control variables,

ProcessingPixel3 and FILTER—OTHER—3 are set to true. If the loop parameter is not 3 ', ProcessPixel3 is set to true. Section 450 illustrates another HDL module, VCl-IDC-FiIter-Line, which applies the current line. (As described in Figure 3, the row filter updates the edge pixel values based on neighboring pixel values.) 16Clienfs Docket N〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/final/林璟辉/2007/05/31 16 200803525 and: The parameters supplied to the submodule contain the control variable

Force side 丨::Pr〇CessingH Spring: In the example, the block effect in the ¥:C bucket circuit: the filter 靡 靡 hard disk ^ weight reduction π amount of input parameters, a quantity is also slow • -^r ^;. Ιλ·.~, r·^ ·"" :士,,Λ,秦模模_ After processing Weng Lie, vc-w. • Two hardware acceleration logic: The circuit 40.0 intercepts the new value in section 420 with a loop parameter, y: the instrument continues the stack. On behalf of the circle. According to this method, the third line of the input block is *^ ϋ· 5 ^ ΙΊτ ^ » 2 # ^ $ 4 η 〇 Figure 5 is a list of hardware description language code of the acceleration logic circuit 500, which is implemented. The above submodules. The section 51 of the code is a group of rights. The row acceleration logic circuit 500 has a number of input parameters. The line system to be filtered is defined as the line input parameter. Processingpixel3 is an input parameter. If the behavior is in the first or third column, it is set to true by the higher layer logic. The parameter FILTER_OTHER-3 - the start is set to true by the higher layer logic φ path, and is adjusted by the line acceleration logic circuit 500 according to the pixel value. Section 520 performs various pixel value operations as determined by VC-1. (Because the calculation can be understood with reference to the specification of VC-1, these operations will not be described in detail.) Section 530 is tested by the higher layer VC-1 loop de-blocking wave-boosting hardware acceleration avoidance circuit 400. processingPixe 13 parameters. If ProcessingPixel3 is true, then section 530 initializes a control variable DO-FILTER to a predetermined value, true. The various results of the operations in the middle of the segment 520 are used to determine if the other 3 rows are to be processed. If the pixel operation result indicates that the other 3 lines are not processed, set DOJPILTER to 17Clienf s Docket N〇.:S3U06-0023 TT's Docket No:0608_A41202-TW/fmal/林璟辉/2007/05/31 17 200803525 False 0 If ProcessingP This x_l: is false, and section 540 uses the input parameter u FILTER_0THER___. Decoupling, in-loop de-blocking filter hardware acceleration logic path _§ lung set Zantai to set the value of D0_FILTER. : If DO-FILTER is: true, segment 550: test the edge of the FILTER new talk variable __P4MP5.:X: 参; see Figure 3 section 560 test the traitorous & Shame 13 parameters, and update ^丨% FI LTER_0THER_3 as appropriate. The FI LTER_0THER_3 variable is used to convey status information for different examples in this model group. If ProcessingPixel_3 is true, then section 550 updates the FILTER_OTHER-3 parameter with the value of DO_FILTER. This technique allows the higher layer module (ie, VCl-InloopFilter) used to describe the module to provide the FILTER-OTHER-3 value updated by the VC-1-INLOOPFILTER_LINE low-level module of this example to another VC-1JNL00PFILTER— LINE. Those skilled in the art will appreciate that the virtual code of Figure 5 can be synthesized in a variety of ways to produce a logic gate arrangement that implements line acceleration logic circuit 500. One of the arrangements is illustrated in Figures 6A-D, which together form a block diagram of the row acceleration logic circuit 500. Those skilled in the art should be familiar with the block-effect filter algorithm and logic circuit structure in the VC-1 loop. Therefore, the elements of Figures 6A-D will not be described in detail. The features of the row acceleration logic circuit 500 will be selected in detail. Those skilled in the art will appreciate that the operations involved in the VC_1 loop deblocking filter include the following, where P1-P8 refers to the position of the pixel in the column/row being processed. 18Client's Docket N〇.:S3U06-0023 TT s Docket No:0608-A41202-TW/final/林环辉/2〇〇7/〇5/31 18 200803525 AO Αΐ A2 (2*(P3 - P6) - 5 *(P4 - P5) + 4) >> 3 (initial (矜:一P4) - 5*(P2 - P3) + 4) » 3 Λr: Λ - Wr; · -;P8)-5,( P6 - P7) + 4) »3 Draft;: Sense _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The line acceleration logic circuit 5〇^ in the layer &A layer uses the 甩 logic circuit to sequentially calculate Yao and Ba Bu. Instead of using the circumstance to process each input sequentially, the logic gate and/or power consumption is reduced. Multiple modes 605, 610, and 620 are used to select different inputs from the pixel register p_8 at different timings, and these input lines are provided to the common logic circuit blocks. Logic circuit blocks 625 and 63() each execute a logic block 635 by multiplying the left shift clamp by _ 2 4 by the left shift by 1 bit followed by an adder 645. The adder 65 加 adds the output of the left shifter 635, a constant 4 and the negative of the 645 output. Finally, logic circuit block 655 performs a right shift of 3 bits. In the first timing cycle, an input T = 1 is supplied to each of the multiplexers 605, 610, and 615, and the value of A1 is calculated and stored in the register 66. On the second day of the sequence, an input = 2 is provided to each of the multiplexers 6〇5, 610, and 615, and the value of A2 is calculated and stored in the register 665. In the third timing cycle, an input T = 3 is supplied to each of the multiplexers β 〇 5, β ΐ〇 and gig, and the value of Α 0 is calculated and stored in the register 670. The values of the registers 660, 665, and 670, Al, Α2, A3, will be accelerated by the partial line of the sixth line. 19Clienfs Docket No.: S3U06-0023 TT's Docket No: 0608-A41202-TW/fiml /林璟辉/2007/05/31 19 200803525 'Use, will be explained later. The output of the P4 register (671) and the output of the P5 register (673) will be used by the section _ _ ☆ ' of the branching acceleration logic circuit 500 of FIG. 6C, which will be described later. · ; ' , * ί · , * ; . ^ , ——- * / ', _ h Those who are familiar with this skill should also know to go inside the JCrl circuit. Block Min Yingshi: ~~ Filter, Linger is involved in the extra operation of the following:::::: :: α wave:·? ^ ^ ^ ^ m - ^ ^ * · / _ »* t{ ·, «*·, « 1 if (CLIP >0) ... :-r ,.; a . .-,-· .; . ' ' ·;·;. > .. .... . ' if (D < 0) D = 0 if (D > CLIP)

D = CLIP • — — _} - - - ~ . - ——- - ..- .... else if (D > 0) D = 0

If (D < CLIP) D = CLIP Part 6B of the line acceleration logic circuit 500 from the part of Figure 6A 20Client's Docket No.: S3U06-0023 TT, s Docket No: 0608-A41202-TW/fmal/林璟辉/ 2007/05/31 20 200803525 Line acceleration logic circuit 5 (10) receives the input and calculates D (675). Referring again to Figure 6A, GLIB:(:6:77:) is generated as follows: Pixels P4 and P5 are subtracted by logic circuit block 679. The result is shifted right by logic circuit block 680 (the whole number - '. The eLIF is generated by identification: 67, 7; 'v returns to the first ^ A1 and can be temporarily stored in the i-th cycle. __0雅得, the second cycle from the scratchpad: _5; 〇, A0 period from the scratchpad 670. According to the culvert, in the west 13⁄4] 3⁄4 cycle, the partial row acceleration logic circuit 500 of FIG. 6 calculates D (6Ϋ5) according to the above equation:: The row acceleration logic circuit 500 uses (675) to update Ρ4 , Ρ5 image A : prime position. In particular, P4 = P4-D and P5 = P5 + D. Although the 6A, 6B diagram was previously combined with a single column / row (for example, a single set of pixel positions P0-P8), a child The operation of the third column/row of the block affects the behavior of the other three columns/rows of the sub-block. The row acceleration logic circuit 500 implements this behavior using a groundbreaking method. When the independent filtering operation starts from the front-parallel-complete In conjunction with the description of FIGS. 6A and 6B, the partial line acceleration logic circuit 500 shown in the 6C and 6D diagrams conditionally selects the position to be updated. In other words, the VC-1 circuit. The inner deblocking filter hardware acceleration logic circuit 400 determines whether the original value is written back or the new value is written back. In contrast, a conventional method, a VC-1 loop deblocking filter is used. The loop is looped, so the independent filter and wave nose are conditionally executed. As explained earlier, Fig. 4 explains that the virtual code of the line acceleration logic circuit 500 operates in a loop: an example appears in a repeating section 420. An instantiation section 450. In addition, the example of the row acceleration logic circuit 500 uses two parameters, ProcessingPixel3 and 21Client's Docket N〇.: S3U06-0023 TT's Docket No: 0608-A41202-TW/fmal/林璟辉/2007/05/ 31 21 200803525 FILTER—0THER—3. These parameters of row acceleration logic circuit 5〇〇 are as follows: Perform conditional update of pixels P4 and P5. See figure, temporary Qin U:, write 〗 lacquer : 681 results, in which the subtractor 6S1 has _ round for the sake of Wei.:.% with the same: sample: 'temporary storage: | 〇 P (four) eight adder. The result of 'paint: 丨 has 4 loses 々 673) 丨, for 〇 or D ( 675 >, depending on the value of the value, the update value of P4 is the original P4 value (if p (LFILTER is false), or P4-D. Similarly, the updated value of P5 is the original p5 value do • do_fTM ,, those skilled in the art should understand that when processing a sub-block In the case of 3 columns, the standard for updating P4 with P4-D is: ((ABS(AO) < PQUANT) OR (A3 < ABS(AO)) OR (CUP Divination) DO-FILTER 683 is from Figure 6D The partial line acceleration logic circuit 500 is tested to verify these conditions. The multiplexer 687 provides an input to the idle 697. If ABS(AO) < PQUANT selects a true round, the others are false. Multiplexer 689 repair provides another input to 0R gate 697. If A3<ABS(A0) selects a true output, the other is false. Multiplexer 691 provides another input to 〇R gate 697, if CLIP ! =〇 selects a true output, others are false. The DO-FILTER 683 is provided by the multiplexer 693, which uses the control input Processing-Pixel-3 (695) to select the output of the output 0R gate 697 or the input signal FILTER-OTHER-3 (699). Input

Processing—Pixel—3 (695) and FILTER—OTHERJ3 ( 699) previously combined with Figure 4 and illustrated by the higher layer 22Client's Docket N〇.:S3U06-0023 TT's Docket No:0008-A41202-TW /fmal/林璟辉/2007/05/31 22 200803525 The virtual code of the block-effect filter hardware acceleration logic circuit 400 in the VC-1 loop has been described. Go back to the first: 3⁄4.3⁄4)3⁄4, when processing the 3rd row/column (1st lap), Processing_Pi 1st dream _: 95' private set to true, others are false. Based on the praise of PQUANT, AB weak A0, the record - the intermediate variable D0_FILTER, regardless of the shovel is apricot. Finally: FILTH^0THER_3 (699): The value is set from this. The result of the logic of the logic circuit part of the logic circuit is G0: for every 4 cycles, 4: adjacent column/row, the pixel position is set as filtered; value (according to A0-A3, PQUANT) , CLIP deity number) or again: write the original; the value of this. The VC-1 deblocking acceleration unit 400 pioneered the combination of parallel and sequential, as previously described. Parallel processing provides faster execution and reduces latency. Although the parallelization increases the number of logic gates, the amount of increase is offset by the aforementioned sequential processing. The conventional method of using the aforementioned sequential processing does not increase the number of logic gates. Some embodiments of graphics processing unit 120 include a hardware acceleration unit for H.264 deblocking, and the deblocking function is used by the S1 processing unit for use. The graphics processing unit 12A will be described in detail in conjunction with FIG. 8 and enhances the specification of the graphics processing unit instructions that provide the H.264 deblocking acceleration function. Principle of the multi-blocking effect of the graphics processor The instruction set of the graphics processing unit 120 is included in the software executing part 23Client's Docket N〇.:S3U06-0023 TT,s Docket No:0608-A41202-TW/fmal/林璟辉/2007 /05/31 23 200803525 The sub-decoding state 160 can be used to speed up a deblocking filter. Here is a pioneering technique. 多重Multiple graphics processing unit commands for more than one. Turn inside the square effect filter lion ^ Originally, the fine Meena wave must be _ fixed to the opposite direction = the prime filter Wei Yuxu 4 fiber left to right and then from top to bottom). And, ^ Previous _ __ secret pixel _ behind the pixel was taken to the secret ^ into. : The main idiot handles the pixel value stored in the tightly understood memory gel, which makes it like t - ft - « . ^ it #^ 4. ft ^^ ^ The block effect waver 290 uses a single-shaped processing unit to accelerate partial filtering It cannot be properly coordinated during processing. The conventional graphics processing unit stores the pixels: two texture caches, and the graphics processing unit pipeline design does not follow the one-to-back read and the write texture fast. It is disclosed herein that some embodiments of graphics processing unit 120 provide multiple graphics processing unit instructions that can be used to speed up a particular deblocking filter. Some of these instructions use texture cache as the pixel data source, while some instructions use the graphics processing unit execution unit as the # source. The in-loop deblocking effector 290 suitably uses these different graphics processing unit instructions to achieve read and write pixels one after the other. The following figure is flowed through the graphics processing unit 1 (4) (4), and then the deblocking acceleration command 'provided by the processing unit 120' and the in-loop deblocking filter 290 are used. Graphic Processing Unit Flow Figure 7 is a diagram of the data flow of the graphics processing unit 120, wherein the instruction stream is 24Clienfs Docket N〇.: S3U06-0023 TT's Docket No: 0608-A41202-TW/fmal/林璟辉/2007/05/31 24 200803525 The arrow on the left side of Figure 7 is used, and the image or graphics flow system is flanked by the arrow on the right; the bursting of the _ release graphics processing unit 12 〇 潞 潞 潞 潞 魏 魏 魏 应 应 应 征 : : : : : : : : : : : : : · Winning and losing refers to 7 Huan, the emblem decodes the instruction, and generates the cold charge _ Cheng Hao: repair the miscellaneous:::J:·_, speed up the video encoding and /: or decode the instruction 0,: . : h : ' · · . . . . ' : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ) Λ ^ ^ ^ pixel^ shading) and other problems. Thus, the instruction material 730 is applied to a pool 740 of shader execution units. The rendering execution unit must use a texture filter unit (TFU) 750 to apply a texture to a pixel. The texture data is taken from texture cache 760, which is behind the main memory (not shown). Some instructions are sent to the video accelerator 150, the operation of which will be described later. The data generated by Lu is then processed by a post-packer (post-packer 770), which compresses the data. After post-processing, the data generated by the video acceleration unit is provided to the execution unit pool 740 ° video encoding/decoding acceleration instruction, such as the aforementioned deblocking filtering instruction, Many aspects are different from the conventional graphical instructions described above. First, the video acceleration command is executed by the video acceleration unit instead of the shader execution unit. Second, the video acceleration instructions do not use their texture data. However, the image data used by the video acceleration command and the graphics command are all 2-dimensional arrays. The graphics processing unit 120 also utilizes this advantage, using the pattern art: filter ^ 浑 : : 750 download to the video acceleration unit: 150 image data,: let the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Speed unit 150 operates _ test stability. Excavation b, meaning in the 7th picture, video plus hard speed unit 150 Pan: Laonqin first maple _ single:: win Qi: with the post-packer 770 meaning 7 M: g, ,-· ; Early Yuan.. 750: Inspect the instruction poor material from the damage order 720. : The coordinates of the body I file. In an embodiment of the application: .... This:: Yes, those skilled in the art should be familiar with this. When the instruction 720 is a video acceleration command, the captured instruction material further instructs the texture filtering unit 750 to skip the texture filter (not shown) in the texture filtering unit 750. According to this method, the texture filtering unit 750 is manipulated as a video acceleration command to download image data to the video acceleration unit 150. The video acceleration unit 150 receives the image resource skew from the texture filtering unit 750 on the data path, and the command material 730 on the command path, and performs an operation on the image material based on the command material 730. The image data output by the video acceleration unit 150 is fed back to the execution unit 740 after being processed by the post wrapper 770. Deblocking Instructions An embodiment of the graphics processing unit 120 described herein provides a VC-1 deblocking filter and an L 264 deblocking filter hardware acceleration. The VC-1 deblocking filter is accelerated by a graphics processing unit instruction ("IDF_VC-1"), while the H.264 deblocking chopper is composed of three 26Client5s Docket No.: S3U06-0023 TT, s Docket No: 0608-A41202-TW/fmal/林璟辉/2007/05/31 26 200803525 graphics winter "Jesus _64, 〇3 L Bu, Tu 2 -:.-?· V- : . ... force, fan, tc , :.;*': fly two.).3⁄4 -.3⁄4 processing single "IDF_H264 one Γ Γ Γ 的 的 的 的 的 夺 夺 夺 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ : Orders, miscellaneous tricks, the building can be regarded as the special parameters of each command. Bo: The set p is embedded in:: Dijon Qin: The order is shared by some _ 漱 漱 漱 雨 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 t t t t t t t Those who are familiar with this skill should understand that this sound can be used to make the angular operation scales (0pc〇d6) and the instruction format code. These issues will not be discussed here, Λ: ^ ^ ' - · '- Table 1: IDF-H264 instruction parameter parameter size operation element description FieldFlag (Input) 1-bit if FieldFlag = 1 Bay 1J Field Picture, Other Frame Picture TopFieldFlag (Input) 1-bit v, - - If TopFieldFlag = 1B 1J Top-Field-Pictxire, Other Bottom-Field-Picture If FieldFlag· PictureWidth (Input) 16-bit is set, for example, 1920 PictureHeight (Input) 16-bit for HDTV, for example, 1080 for 30PHDTV YC Flag 1-bit Control-2 Y plane or chroma plane 27Client's Docket N〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 27 200803525

Field 1-bit Control-1 Direction t, 'one:: CBCR Flag 1-bit Control-1 ••Gb·:: or, Cf Base ss 32-bit. · · *, -· :·, : · : • . , :二·' . ·二.-· ;> , '> ' ·· : In the IDF must ' (In_ ”; Yuan is not. _ II: § § 己 '丨思思The child of the body, the block number... • ., . Basic address: BlocKddress 13.3 SRC1[0:15]^ For IDFJH6420: (Input): Grid: U The entire sub-block (for basic, SRC1[ 31:16] = Address) Texture coordinates are slightly V ForH)F—H64—1: The remaining squares of the sub-blocks (for basic bit addressing) are not used in IDF_H64_2 DataBlockl 4x4x8- at IDF—H64J The unused bit SRC2[127:0] is used for IDF-H64J: the upper or left half of the sub-block, according to the FilterDirection SRC2[127:0] encoded according to the Control 2 parameter for EDF-H64-2: One (even) register pair DataBlock2 4x4x8- is not used in IDF_H64_0 〇 or bit jDF__H64 1 for SRC2[255:128] for IDF H64 2: second 28Client5 s Docket N 〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 28 200803525 (odd) register to Sub-block (Output) ' > ,, 128' Weng, ” -· .....·. ' .' .. d· .n ., _ 8x4x8-bit sub-block of block effect (128' _: meta), " • > : . ; ' The wheel ginseng: the number is negotiated by the texture filtering unit 75a_m. The BaseAddress parameter indicates the starting point of the texture and texture in the texture cache _. The upper left square of this area is given to

BaseAddress parameter. Picturefjeig and the picturewidth input parameter are used to determine the range of the square, the lower left coordinate. Finally, the video graphics can be progressive (progessive) or interlaced. For interlaced scanning, it consists of two directions (upper and lower). The texture filtering unit 750 uses FieldFlag and TopFieldFlag to properly process the interlaced scanned image. The deblocking 8x4x8 bit output system is provided for a target temporary cry, and is also written back to the execution unit pool 740. Writing the deblocking output back to the execution unit pool 740 is a "m〇dify in place" operation, which is necessary in some decoder implementations, such as Η·264 where the pixel value in the box is 'right Below, it is calculated based on the previous results. However, the 1 decoder does not have this limitation relationship like H.264. in? (:-1, for each 85 (8 vertical (first vertical and then horizontal) filtering. All vertical edges can thus be performed in parallel on the enamel, 4x4 edges are filtered later. Parallelization can be utilized because there are only two pixels (one edge one) is updated, and these pixels are not used to calculate other edges. Since the block effect data is written back to the execution unit 29Client's Docket N〇.:S3U06-0023 TT's Docket N(x0608_A41202-TW/fmal/林璟辉/2007/ 05/31 29 200803525 Pool 740 instead of texture cache 760, provides a different IDFJI264 one finger, so that this sub-block is taken from different positions. This can be seen in the j. See, in llockAddress In the narrative, Data Block! and Qiu·: 轻轻脚_β_: Wolf: Yuan i sub-Leng block HDF-Η264-1 instruction from the texture cache 76〇撷 • Abandon two green clothes: , instrument and: ^^禄# 'Yuan Tear: Move the half to one. A,... :::: With the code, the device 1 is changed to the function of the JDFJ1264-X command. The following is a detailed description of the supply of pixel data to the video acceleration. Zhang Yuan, before, the texture filtering unit 750 and the competing unit pool 740 convert the remaining resources Processing of the material. The image data is replaced by the above-mentioned command parameters, and the coordinates of the sub-block address to be extracted from the texture cache 76 or from the execution unit pool 740 are provided to the texture filtering unit 75. The image data includes brightness (Y ) and chroma (Cb, Cr) plane. A YC flag loses eight parameters. The number defines the Y plane or CbCr plane to be processed. When processing the twist (Y) data, as indicated by the YC flag parameter, the texture The filtering unit 750 retrieves the sub-block and provides the 128-bit as an input to the VC-1 in-loop deblocking filter hardware acceleration logic circuit 4 (10) (eg, the block input parameter of the VC-1 accelerator example of FIG. 4). The generated data is written to the target register as a group of 4 - register quad (ie, DST, DST+1, DST+2, DST+3). When processing chroma data, such as YC flag As indicated by the standard parameters, the cb and Cr blocks will be accelerated by the block-effect filter hardware in the VC-1 loop. 30Clienfs Docket N〇.:S3U06-0023 TPs Docket No:0608-A41202-TW/fiml/林璟辉/2007/ 05/31 30 200803525 The circuit 400 is processed continuously. The generated data is written. Texture cache 760. In some embodiments, this occurs in each cycle, with 256 bits per cycle. j; and , %% - some video acceleration units compact 'balance bar, interlaced Sweep planes, each: save as one width and half length. : Touching 遽 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Unit puller buffer. In particular, the texture filtering unit 霄50 writes a 4x4 Cb block to the buffer^ and then writes 2 blocks to the buffer. Each &x# Cb block is firstly used by the vc-i loop. The hardware acceleration logic circuit 4 is processed, and the generated data is written to the texture cache 760. Next, the 8x4 Cr block is processed by the vc-l loop to the block effect filter hardware acceleration logic circuit 400, and the resulting data is written to the texture cache 760. The video acceleration unit 150 uses the CbCr flag parameters to manage this sequential processing. % Use the squared back and the ground. In conjunction with the previous description of Fig. 1, the decoder 160 executes on the main processor 110 but also utilizes the video acceleration command provided by the graphics processing unit 120. In particular, the H.264 loop deblocking filter, the embodiment of the waver 290 uses a specific IDF_H264_x combination to process the edges, extracting some sub-blocks from the texture cache 760 and executing from the execution unit pool in the order specified by H.264. 740 Take some more. With proper combination, these IDF_H264_x instructions achieve one pixel read and write. Figure 8 is a block diagram of a 16x16 large block for H.264. This big 3 lClienfs Docket N〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 31 200803525 The square is cut into 16 4x4 sub-blocks, each of which will perform the deblocking effect . Figure 8:: Medium: The "Fan Linzi box can be defined by column and line (for example, ri, Η· 264 determinator: first box, vertical edge at the processing level edge, as shown in the eighth __靡_胸声;.1. Hu. : because _#___ block: effect: Ying Debo: applied to a pair of sub-blocks: .?> edge sub-square. Filtration „:.heart edge a=[block to left 〇fRl,ClH [R1?C1} ; [block to left of R2,C1] | [R2,Cdl; v ;.:: ->,-;- Γ [block to 13⁄4 of R3,C1] I [R3;C1]; [block to left of R4?C1] | [R45C1]":; edge b=[Rl,Cl] j ; tR2,C2l;[; Il2,Cl!;|[R2,C^;.:.; [R3,C1]| [R3,C2] ; [ R4,C1] | [R4,C2]; edge c=[Rl,C2] | [ R2,C3] ; [ R2,C2]丨[R2,C3]; [R3,C2] | [R3,C3] ; [ R4,C2]丨[R4,C3]; edge d=[Rl,C3] | [R2,C4] ; [ R2,C3] | [R2,C4]; [R3,C3] | [R3,C4] ; [ R4,C3] | [R4,C4]; edge e-[block to top of R1,C1] | [R1,C1] ; [block to top of Rl,C2] | [R1,C2]; [block to top of R1,C3] | [R1,C3]; [block to top of R15C4] | [R15C4] edge f=[Rl,Cl] | [R2,C1] ; [ R1,C2] 1 [R2,C2]; [R1,C3] | [R2,C3]; [R1,C4] 1 [R2,C4] edge g=[R2?Cl] | [R3,C1] ; R2,C2] | [R3,C2]; [R2,C3] | [R3?C3]; [R2?C4] | [R35C4] edge h=[R3,Cl] | [R4,C1] ; [R3, C2] | [R4,C2]; [R3,C3] | [R4,C3]; [R3?C4] | [R4>C4] For the 1st pair of sub-blocks, all download from texture cache, because there is no 32Clienfs yet Docket N〇.:S3U06-0023 TTs Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/3} 32 200803525 There are pixels that have been changed due to the application of the filter. Although the filter of the vertical edge (a) of the vertical edge (a) can change the pixel value of (R1, C1), the second column of the vertical edge is actually the same as the vertical edge of the bottle::1 column. Therefore, the poor ^ also intercepts & texture cache 760. Since the two phases: the adjacent columns; the vertical edges of the i are not common "" 像 with the parameter '. age is not right (edge c) and the fourth pair _ edge., :, IDF-m64^x command to determine The pixel _: Λ . 拽 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ID =address of (R1,C1); IDF—H264—0 SRCl=address of (R2,C1); IDF—H264—0 SRCl=address of (R3,C1); IDF—H264—0 SRCl=address of (R4 Next, the in-loop deblocking filter 290 processes the second vertical edge (b) starting from (Rl, C2). The leftmost 4 in the 8x4 sub-block defined as (Rl, C2) The pixel overlaps with the rightmost pixel of the (R1, C1) sub-block. These are processed by the vertical edge filter of (R1, C1) and may also be updated, and the overlapping pixel system is thus read from the execution unit pool 740 instead of the texture. Take 760. However, the 4 pixels on the far right of the (Rl, C2) sub-block are not filtered yet, so read from texture cache 760. Sub-blocks (R2, C2) to (R4, C2) are also the same. The deblocking filter 290 processes the second set of vertical edges by commanding the order of idF_H264_x below to complete the result: IDF - H264 - 1 SRCl = address of (R1 - C2); IDF_H264_1 SRCl = address of (R25C2); 33Clienfs Docket No.:S3U06-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 33 200803525 IDF-H264-1 SRCl=address of (R3,C2); IDF_H264_1 SRCB= address of ( R45C2); When dealing with the 3rd: group vertical, straight seam: _ when _ from .iR1, C3). In (phantom, C3) 8x4 sub-block: the pixels in the inner side exposed g overlap, because: rain, however, in (R4, C2:), thus reading from texture cache 7.6 transport edge _ café ' G2) sub-square read right _ 孰 Xu unit ί 74 〇 instead of texture cache 76 〇. Cheng # > sample most _ edge win 4:: 値 pixels have not been crossed, 0:: sub-block ❹k, C2:) to (_, C2) is the same. The last set of vertical edges will have a similar situation ^ Therefore, the loop calls the block effect filter 290 By ordering the following n) F-H264-X sequence, the two vertical edges are: IDF H264 1 ...... — IDF H264 1 —- — IDF H264-1 H>F-H264 IDF —H264—1 IDF—H264—1 IDF—H264—1 SRCl=address of (R1,C3); SRCl=address of (R2,C3); SRCl=address of (R3,C3); SRCl=address of (R4 , C3); SRCl=address of (R1, C4); SRCl^address of (R29C4); SRCl=address of (R3?C4); 】DF—H264—1 SRCl=address of (R4,C4); Horizontal edge (eh). At this point, the deblocking filter has been applied to each sub-block in the large square, so each pixel may have been updated. Therefore, each sub-block sent to perform horizontal edge filtering is read from execution unit pool 740 instead of texture cache 760. Therefore, the in-loop deblocking filter 290 processes the horizontal edges by ordering the following H)F_H264_x: IDF-H264-2 SRCl^address of(Rl5Cl); 34Client's Docket No.:S3U06-0023 TT's Docket No:0608 -A41202-TW/fmal/林璟辉/2007/05/31 34 200803525 IDF—H264—2 SRCl=address of (R2,C1);

b “珥匕1 2 SRCl=address of (R3,C1); /SRCl-address of (R49C1); ΐ V 〇f(R2,C2); 73⁄4 SRGl^address of (R3?C2); IDF^ H264^2 SRGl=address of (R4?C2); IDF-_;H264_2 SRC 1 ^address of (R1 ,C3); Any procedure, sequence: Ming. or flow chart: The block in the middle should be understood as Representing a module, section, or portion of code that contains one or more executable instructions for implementing a particular logic circuit function or step in a program. Those skilled in the art that should be aware of other implementations It is also included in the scope of the disclosure. In other implementations, the functions may be performed in the order shown or disclosed, including substantially synchronous or reverse, depending on the function involved. The genus and method may be implemented in software, hardware or a combination thereof. In some embodiments, the system and/or method is implemented in software stored in memory and executed by a suitable processor located in a computing device (including Not limited to a microprocessor, microcontroller, network processor, reconfigurable processor, In other embodiments, the system and/or method is implemented by a logic circuit, including but not limited to a programmable logic device (PLD), a programmable logic gate array (PGA), a programmable gate Array), on-site spoke-type logic gate array (FPGA 'field progrannnable gate 35CUent's Docket No. :S3U〇6-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 35 200803525 array Or an application specific circuit (ASIC). In other embodiments, these logical statements are done at the -_processor or _: the GPU (Gpu). /-· The systems and methods disclosed herein can be embedded. Any computer readable. Media touch _ _ knot an instruction execution system, equipment 卜 々 々 々 々 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The computer-readable medium (comput-readable itiediumr can be used to accommodate, store, communicate, transfer or transmit the privately-readable medium from the instruction execution system) A tool that is coupled to a system of instructions. The computer readable medium can be, for example, a non-limiting electronic or magnetic, optical, electromagnetic, infrared, or semiconductor technology system or medium. A specific example of a computer readable medium of electronic technology (non-limiting) may include: a line having one or more electrical (electronic) connections; a random access memory (RAM, random a Ccess mem〇ry); Read memory R (R0M, read, 1 y memory); - Can erase the programmable read-only memory (EPROM or flash memory). Specific examples of computer readable media that use magnetic technology (without limitation) may include: a portable computer diskette. Specific examples of computer readable media that use optical technology, without limitation, may include: a fiber optic and a portable CD-ROM. The invention is illustrated and described herein by way of example only, and is not intended to Many different modifications and structural changes are made within the scope and scope of equalization. Because 36Clienfs Docket N〇.:S3U06-0023 TT’s Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 36 200803525

I v, preferably, the scope of the attached patent application is broadly and in a manner consistent with the field of the present invention: v: 2 is proposed before the patent application scope of the flap ^: :- :VV ·: ·-' . ., -S '-: . ;; ; % . ! ^ ··· ...·, f, .*······, _',,,,.. - Μ -,. ' A brief description of the schema] The first one is decoded with a 1-shaped nose. 3⁄43⁄43⁄43⁄43⁄43⁄4 - a block diagram of the platform. :: ~ :... :: 2nd picture 〒^ '...3i i says ^vcri:i wave, it;|V • j 4 shoulder system 1 _ VC-1 circuit acceleration logic circuit 400 hardware description A wide list of virtual codes: Figure 5 is a list of hardware description language code for the acceleration logic circuit of Figure 4.

The 6A-D diagram forms the _ square diagram of the acceleration logic circuit in the 4th and 5th diagrams. A Figure 7 is a data flow diagram of the graphics processing unit 12 of Figure 1.苐8 is a block diagram of 16x16 large squares used by H·264. [Description of main component symbols] 100~ system, 110~ general purpose CPU, 120~ graphics processing unit (GPU), 130~memory, 140~ bus, 150~video acceleration unit (Vpu), 160~soft decoder, 170~ Video Acceleration Drive. 205~ input bit stream, 210~en entropy decoder, 215~space decoder, 220~inverting quantizer, 230~inverted discrete cosine transform, 235~ graphics, 245~moving vector, 250~moving compensation, 255 ~ Previously decoded graphics, 265~Pre-37Client5s Docket N〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 37 200803525 'Measurement graphics, 270~space compensation, 280~addition , 290~ go to the square effect filter, 295~decoded jug *.. * * * 310-320~# adjacent 4x4 sub-blocks, 330~ vertical borders. -·:· ι-;. '' iV :·;. ·;· :·:. ^·: /·/.· . ' ; . ···; ,-· 400~loop·inside body effect Filter g hardware acceleration logic, θ will 3; _. ; ί\λ,·γ·: * ' Module definition section,: 420 meaning: variable generation back to _, 430~ test vertical parameter frost 养, 440~tb compared to the loop parameters and: 3 sections, 450 ~ Example section. . . . -': · · - · -.;...:;···'· :' :· ·., 二,.:,: ,.. . ', · · > - . • ...500~ Line acceleration logic circuit, "51〇^模伞 definition section, 520~ image rejection value;; operation section, 530~ comparison loop parameter and 3 section, 540~ test DOJFILTER section, 550~update status area Section 605-610-615 - 620 ~ multiplexer, 625-630-679 ~ subtractor, 635-640-655-680 ~ logic circuit block, 645-650 ~ adder, 660-665-670 ~ temporary storage 671~P4 register output, 673~P5 register output. 681~subtractor, 685~adder. 687-689-691-693~Multiplexer, 697~OR gate. 710~ instruction stream Processor, 720~instruction, 730~instruction data, 74〇~ 执4亍早元池, 750/^" texture filtering early element, 760~ texture cache, 77〇~/纟 wrapper. i 38Clienfs Docket N 〇.:S3U06-0023 TT's Docket No:0608-A41202-TW/fmal/林璟辉/2007/05/31 38

Claims (1)

200803525 ^ X. The scope of application for patent: : Bu; a circuit 'used to determine a plurality of intermediates: .:.; group _ field to _ standard; i ^ food ^ y article: stupid logic circuit, report Less skill soil 2. A deblocking filter according to claim 1 of the patent scope, wherein _ a plurality of pixel groups form a square pixel block, and the plurality of images: the prime group comprises a column of pixel squares. Each of the images is as described in the third aspect of the patent application. A plurality of pixel groups form a square pixel block, and the plurality of pixel groups: the prime group includes a row of pixel squares. For example, in the deblocking filter of claim 1, the third logic circuit further includes: - a fourth meaning circuit, which is set to be updated according to the second predetermined pixel group in the remaining pixel group One of the first predetermined pixel groups in each of the remaining pixel groups. 5. If you apply for a patent range! The deblocking effect of the term according to the wave $f of the second logic circuit further comprises: ~ - the fifth logic circuit is arranged to filter the pixels of the pre-population group in parallel when the standard is turned over. 6. The deblocking filter according to item 1 of the patent application scope, wherein the 39Client's Docket No.: S3U06-0023 TT's Docket No: 0608-A41202-TW/fmal/林璟辉/2007/05/31 39 200803525: block effect Qian Bo n is the secret sub-block to the edge to remove the object. '众,鸭炅一*·-.,·〆' .·,;上_: :, ^ 7·If applying for a patented painting: item 4, a t :: '...: two' ' block effect filter State, in which the deblocking filter makes a lot of graphics processing instructions for the apricots +, / 'miao Tian,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,.: 8. In the case of the name, please refer to the 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A video decoder comprises: a second: an entropy decoder that receives an input encoded bit stream; a spatial decoder that receives the output of the entropy decoder and generates a coded picture of the plurality of pixels; The logical f path is set to combine - the current picture and - generate a combined picture; and & & the first loop in the loop to receive the combined picture, the in-loop deblocking filter includes: a county-based predetermined pixel occupational wave; and a third logic circuit configured to set a predetermined pixel group to a standard, according to a corresponding group of filtering units in the complex array chopping unit, remaining in the plurality of pixel groups Each pixel group under the filter. 10. The video gamma repeller of claim 9, wherein the plurality of pixel groups form a square pixel block, and each pixel group of the plurality of pixel groups comprises a column of pixel squares. 〃 11. The video decoder of claim 9, wherein the plurality of pixel groups form a square pixel block, and each pixel group of the plurality of pixel groups is 40Clienfs Docket N〇.; S3U06-0023 TT'sDocketNo ^OS-AAUC^-TW/fmal/林璟辉/2007/05/31 200803525 Contains a row of pixel squares. Where Mf Α Α : First to the town to lead the cold.. Like: νΊ ":13⁄4.3⁄4: The video decoder of the ninth application patent scope._第:显铁缉_龟' 戮 灭 在 在 在 在 在 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到 达到::Knowing to read the summer of the Li Hengwei J item winter video decoder, the album also contains The fifth logic circuit 'is set to be based on the remaining pixel groups: = the predetermined pixel group of the flute, taking care of the remaining pixel groups - the first predetermined ^^ 14. As claimed in claim 9 The video maser is a filter that is defined in accordance with the VC-1 standard. The graphics processing unit comprises: a main processing interface, receiving at least one video acceleration command; and a video acceleration unit for responding to at least the video acceleration command, the video acceleration unit comprising a loop a block effect filter, the intra-blocking filter, the wave device comprises: a first logic circuit, configured to determine whether a pixel of a predetermined pixel group of the plurality of pixel groups reaches a first standard; And setting, when the first standard is reached, first filtering the pixels of the predetermined pixel group; and a third logic circuit 'set to, when the _th criterion is reached, according to one of the corresponding group of filtering units in the complex array filtering unit, The remaining pixel groups in the plurality of pixel groups are sequentially filtered. 16. The graphic processing unit of claim 15 of the patent application, wherein the complex 41Clienfs Docket N〇.: S3U06-0023 TT's Docket No: 0608-A41202-TW/fmal/林璟辉/2007/05/31 41 200803525 : and the image of the plurality of pixel groups, the image of the 15th woman-shaped processing unit 'where the plural number contains - line:: image class meaning mixed " thief _ standby pixel logic: road = patent scope first 嶋Ft_器' 'It, tender: Pre = prime = _ left view group feelings. - the first - difficult pixel group. ― Effect Filter 2 == Video Decoder ’ where _ 42Clienfs Docket N〇.:S3U06-0023 TT’s Docket No:0608-A41202-TW/final/林璟辉/2007/05/31 42