TW200421180A - Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating - Google Patents

Abstract

Processing circuits that are associated with the operation of the threads in an SMT processor can be configured to operate at different performance levels based on a number of threads currently operated by the SMT processor. For example, in some embodiments according to the invention, processing circuits, such as a floating point unit or a data cache, that are associated with the operation of a thread in the SMT processor can operate in one of a high power mode or a low power mode based on the number of threads currently operated by the SMT processor. Furthermore, as the number of threads operated by the SMT operator increases, the performance levels of the processing circuits can be decreased, thereby providing the architectural benefits of the SMT processor while allowing a reduction in the amount of power consumed by the processing circuits associated with the threads. Related computer program products and methods are also disclosed.

Description

200421180

TECHNICAL FIELD The present invention relates to a general architecture of a computer processor, and in addition, to a synchronous multi-fiber computer processor, a related computer product, and a method of operating the same. The previous technology, Simultaneous Multi-Threading (hereinafter referred to as SMT-), is a multi-threading method using hardware, which allows 'multiple threads' to issue instructions during the mother cycle. Processor architecture. Unlike other hardware multi-fiber architectures where only a single hardware context (i.e., floc) can be launched in any given cycle, the synchronous & fabric architecture allows all thread contexts to compete at the same time And share processor resources. The synchronous multi-fiber processor can make good use of the cycle that was originally wasted to execute instructions that can reduce the effect of the long latency action in the synchronous multi-fiber processor. In addition, as the number of batts increases, the overall performance also increases, so the power consumption of the multi-batch processor may also increase. FIG. 1 is a block diagram of a conventional synchronous multi-fiber processor. The action of the conventional synchronous multi-fiber processor in Figure 1 is in Dean M.

Tullsen; Susan J. Egger; Henry M. Levy; Jack L.

Lo; Rebecca L. Stamm et al .; Exploiting Choice:

Instruction Fetch and Issue on an Imp 1 ementab1e Simultaneous Multithreading Processor, The 23rd

As disclosed in Annual International Symposium on Computer Architecture, pp. 191-202, 1996, and this publication

13145pif.ptd Page 6 200421180 V. Description of the Invention (2) It is stated here that the above papers will be incorporated by reference for explanation. The architecture and actions of the processor are familiar with the synchronization of related technologies. The details will not be repeated here. θ is well known, so the embodiments of the present invention provide a processing circuit, a product, and / or a method for producing a synchronous multi-processor operation based on a plurality of operating computer programs. In the embodiment, the same as in the multi-float;:, and; the == invented as a floating-point unit called PQlnt related: in the high-power mode or low-power mode: :: by the multi-float synchronization The number of processors operated by the processor = flat. Therefore, while reducing the power consumed by the processor, a synchronous multi-processor processor rack is provided: Bu: The processor can also use the same power but higher performance. Ί Power but more efficient It is known that the performance of the synchronous multi-fiber processor is higher in some embodiments according to the present invention. 'When the same ::; ΠΓΓ number system is less than or equal to a critical value, the processing circuit system operates at an efficiency level, and When the number of processors of the processor = 3 is greater than the critical value, the processing circuit system is configured to operate at a first efficiency level. In some embodiments according to the present invention, a two-way performance level may be constructed to be based on the number of bats currently operated by the synchronous multi-batch processor. Page 7 13145pif.ptd 200421180 V. Description of the invention (3) Where according to the present invention Part of the real ... the critical value is less than or increased to the -th-efficiency level. A second efficiency level that can provide the efficiency = average efficiency == circuit efficiency level provided to at least one processing circuit. Drop to below the first. In some embodiments according to the present invention, when synchronizing: the number of bats that are operated exceeds the effect of the first trip to the third efficiency level which is lower than the second efficiency level. The present invention provides various embodiments with varying levels of efficacy. By way of example, +, in some embodiments according to the present invention, the processing circuit is available. Memory (tag memory) and a data memory (data mem〇r〇 show a paper fast = memory circuit (cache memory circuit). Among them, when the memory is fetched, the circuit operates at the first-performance level Data memory; then access the cached data (cached dat =) which is accessed at the same time as the tag memory. To get the memory circuit is based on a second performance level below the first performance level. The data memory can provide cached data for hit tags. 丨 ~ 蔽 In some embodiments according to the present invention, the cache memory can be used as a data cache to store data. Fetch memory (data ache 9 memory), and an order cache memory (instruction cache memory) used to store instructions on related data at least Fu Ling page 8 13145pif.ptd 200421180

5. Description of the invention (4) In some embodiments according to the present invention, when operating, the data memory can be more structured to provide cache data that can be manipulated horizontally by the tag memory. Non-hit (m i s s) In some embodiments according to the present invention, the electric unit is processed. In some embodiments according to the invention φ, > the path may be a floating point τ τ hand black account-r only the first floating point unit, and when the synchronous multi-processor processor ^ 疋 may be a number system less than or equal to At a critical value, the first floating-point unit operates at a first efficiency level. In addition, the synchronous multi-intelligence: the frame is composed of a second floating-point circuit, and when the synchronous multi-float processing °, including the number of flocks is greater than the critical value, the second device Operate at the second efficiency level. ". The road frame constitutes a control circuit in some embodiments according to the present invention, so as to respond to the number of loops made at a synchronous multi-processor chip # at an efficiency level, and increase or decrease the synchronous multi-Is respectively. Number of completed jobs. 'The processor is currently operating. In some embodiments according to the present invention, the y circuit can respond to the number of second processing values currently operated by the synchronous multi-fiber processor, which is lower than the first performance level. t has increased to this threshold. Operating at the second level of efficiency In some embodiments according to the present invention, the t-frame constitutes a response when a new line is added to reduce the number of lines in the same cattle / such level control circuit system from less than or equal to a critical value (two ^ When the processor is currently operating, the efficiency level is reduced in some embodiments that provide at least two processing circuits that are greater than the critical value. In the embodiment of the present four-lane system, the synchronization is more

13145pif.ptd Page 9 200421180 V. Description of the invention (5) __ When the number of flocs currently operated by the flocculation processor exceeds all the ascendmg threshold values, it will be processed ^ two values :: reduced to plural descending (descending) The efficiency level is equal to water. In some embodiments according to the present invention, the efficiency water rack constitutes a response. When the I-system circuit currently operated by the synchronous multi-flop processor is at or equal to a critical value and increases to a value greater than the critical value, in the morning, From a small-first processing level of the processing circuit, i is provided to a second-processing circuit that is lower than the second-second performance level '. At this level

In other embodiments according to the present invention, the efficiency level is controlled to the processing circuit in the synchronous multi-fiber processor according to the current performance of the synchronous multi-fiber processor. 1. In other embodiments according to the present invention, when the J-floor can be used, will it be synchronized with the multi-fiber processor? Electric :: Electric Synchronized Multi-Flood Processor. The efficiency level is provided to the processing circuit according to one of the current operations of the synchronous multi-fiber processor. In other embodiments of the invention, Ding Guan Guan and the synchronous multi-fiber processor include: tags The memory and the data memory can be two, and the number of operations currently performed by the zeta second processor, the data memory = take synchronous access' or after the access to the mark memory to allow the above-mentioned sum of the present invention and Other purposes, features, and advantages can be made clearer

200421180 V. Description of the invention (6) '------- ^ _ It is easy to show it. The following is a description of the preferred embodiment and the accompanying drawings. The detailed description is as follows: The accompanying drawings detail preferred embodiments of the present invention. In the following, the same reference numbers represent the same description and implementation of the original slave / invention 'to fully understand and study the present invention and / or advantages. Other characteristics ^ Those familiar with related arts should know that although the first and second words used here describe various elements, these elements are not limited to this specific-name: nouns are used to distinguish elements. Therefore, the first 70 pieces discussed here can also be a second element in another chapter. Similarly, the second element 4 discussed herein may also be the first element in another chapter, as long as it does not deviate from the spirit of the present invention. /, Those skilled in the art know that the present invention can also be implemented in the form of a circuit, a computer program product, and / or a computer program product. Therefore, the present invention can be implemented by hardware, software, or hardware, and some software. In addition, the present invention can be implemented in the form of a computer program product having computer code stored in the medium on one or two removable media. Any computer-readable medium including a hard disk, cd-ROMs, optical storage device, or magnetic storage device can be applied to the present invention. '® The computer code or code used by the present invention for performing calculations, such as JAVA' Smalltalk iLC + + ^ JavaScript ^ Visual Basic ^ TSQL, Perl object-oriented programming language, or in various other programming languages 200421180 5 2. Description of invention (7). The software embodiments of the present invention are not limited to having to be implemented in a certain programming language. Some code can also run entirely on one or more systems used by an intermediate server. The code can be executed entirely on one or more computer systems, or partly on a server, and the other part on a client configured in a client device Execution 'or even can be used as a proxy server located at an intermediate point of the communication network. In the latter example, the client device may be connected to a server on a local area network (LAN) or wide area network (WAN), such as the Internet, or via the Internet, such as through an Internet service Suppliers). The invention can be implemented with various protocols running on different types of computer networks. The following describes the operation of the present invention in detail with reference to block diagrams and flowcharts for describing methods, systems, and computer program products according to embodiments of the present invention. Those skilled in the art should know each block shown in the block diagrams and flowcharts, and the various combinations of block diagrams and flowchart blocks, which are implemented by brain program instructions. These computer program instructions can be provided by a synchronous cry circuit, a special purpose computer, or other programmable data processing devices, to generate a machine instruction that can be executed by a computer's processor or other processing device. The ancient trick Okazaki "V + & Performs the various functions specified by the block diagram and / or the private map block or combination of blocks. The second, the second and the second brain "program, type instructions can be stored in a computer readable memory," V computer or other programmable data processing: work, thereby making it stored in Lei Dingding>% _ Set the slave mode to the instructions in the computer readable memory, which can generate

200421180 V. Description of the invention (8) An article of manufacture that includes instructions that can perform various functions specified by block diagrams and / or flowchart blocks or block combinations ° These computer program instructions can load a synchronous multi- A processor circuit or a programmable data processing device executes a series of operating steps to perform a computer-implemented process on a computer or other programmable device, thereby executing on the computer or other programmable device Implements various functions specified by block diagrams and / or flowchart blocks or combinations of blocks. An embodiment of the present invention provides a processing circuit related to a flocking operation in a synchronous multi-fiber processor. Among them, the processing circuit frame structure operates at various performance levels according to the number of batters currently operated by the Synchronous Buffer Processor. Those skilled in the art should know that these various performance levels can include different circuit operation rates and / or various precisions. In some embodiments according to the present invention, the processing circuit according to the present invention may operate at different clock rates, and / or use different devices such as different types of 装置 s devices) to provide different: In some embodiments of the invention, the unit or data is fast and can operate in a low power mode based on a synchronous multi-ocean point rate. It is expected that when ② the clock is increased, it may be reduced. Therefore, it is necessary to reduce the number of processing related to flocking and provide advantages in the synchronous multi-fiber processor architecture. dry

200421180 V. Description of the invention (9) '' As the heat-study related artisans know that the embodiments of the present invention can demonstrate the parallel-level computing capability of thread-level, that is, a plurality of threads can be used to execute the contained content in parallel. Multiple processing. As used herein, the term " thread " (thread) may be an individual process with related instructions and data. A thread may represent a process, which is part of a parallel computer program with multiple processes. A thread may represent a process that can communicate with Other programs are independent and independent computer programs. Each program can have a related dynamic, such as related instructions, data, program counters (Pr0gram c〇unter), and /

Related states defined by iff registers. Among them, the relevant state of the floe may contain sufficient information required for a processor to execute the floe. ^ According to some embodiments of the present invention, an efficiency level step multi-flop processor can be configured to be provided to be used to process control circuits at the same level. One can be provided: for example, the "efficiency circuit m" Operation, can also provide-the second efficiency level to the processing operation per # π in a power mode. In other examples according to the present invention, the performance level control circuit provides other levels of efficiency between intermediate levels). " Yu Nan power and low power are the roots of the operation: the local haircuts: the body's-cache memory; that is, in the high power mode) the body is at the first level of efficiency (also hits, both When it can be used in the same way, you can access the tag memory and data memory at the same time regardless of whether the tag memory is accessed.

200421180 V. Description of the Invention (ίο) The hit rate of the signed memory may be quite high, so simultaneous access to the data memory can provide better performance. On the other hand, the cache memory can also be operated at the second performance level (that is, in the low power mode), where the data memory ^ ^ is accessed in response to hitting the tag memory. Therefore, when a tag mismatch (tag m1SS) occurs, part of the power consumption associated with accessing the data memory can be avoided. In addition, when a tag hit occurs, there may be a deviation between accessing the tag memory and accessing the data memory. β Second meal In other embodiments according to the present invention, the processing circuit related to the blobs operated by the synchronized blobs may be an instruction cache "° (instruction cache) > ^ JL #« ι ^ ^ „points雷 踗 式 敏 iw # · Time /, other types of processing circuits, such as floating ", circuit 4 integer / manned-storage circuit (integer / 1Qad_store In addition 'each-processing circuit can be at different performance levels:]: two 'In some embodiments according to the present invention, the cache is 5! It is not as good as the floating-point circuit and the integer / load-storage circuit, so it can operate at different levels at the same time. 丨 In other implementations according to the present invention, you can use ( For example, the floating-point circuit and the integer two: electricity :) the same type, so that some circuits can be designed to specifically use ::: operate at different performance, while other processing circuits can be used to operate at the first performance level. For example, in some embodiments where the gate is used to place the synchronous multi-amplifier & s < at the second performance level, with a high power mode ==: part of the floating-point rotation, the frame constitutes another floating-point circuit. , Then 俜 ¥ ^ ^ ζ ^ $ The system structure operates in low power mode. 200421180 V. Description of the Invention (ll) Figure 2 shows a block diagram of a synchronous multi-fiber processor according to an embodiment of the present invention. Please refer to Figure 2 when the When a new batch is created in Synchronous Multi-Blot Processing, the batch management circuit 205 will configure a set of processing circuits for the newly created batch. The configured processing circuit may include a program counter 2 1 5. The floating-point register 2 4 5 and a set of integers temporarily store 5 | 2 5 0. Other processing circuits can also be configured for the newly created floc. Those skilled in related arts will be allocated to the floc when it is finished The processing circuit used should be released so that it can be re-configured for subsequent use in other processes. In its operation, a fetch circuit 21 () is first based on the programmed counter 21 5 The provided position information fetches an instruction from a 4 command cache 2 2 0 and outputs it to a decoder 2 2 5. The decoder 2 2 5 outputs a decoded instruction to a temporary Register rename circuit renaming circuit) 230. According to the type of instruction output from the register rename circuit 230, the renamed instruction will be output to a foreign point instruction queue (floating p〇int instructi〇n called ⑽㈧235 or an integer instruction queue ( integer instruction q ^ eUe) 240. For example, if the type of instruction output by the register update circuit 23 () is a floating-point instruction, the instruction will load the floating-point instruction queue 235, and if * is temporarily stored The type of instruction output by the processor update circuit 23 is an integer instruction ', and the instruction will load the integer instruction queue 24. The instruction output from the floating-point instruction queue 235 or the integer instruction queue 240 is loaded into a relevant register so that it can be executed by a corresponding path 255 or integer / load-store circuit 26. More specifically, floating point

200421180 V. Description of the invention (12) The 々 令 will list 2 3 5 from the floating-point instruction, check, * $, ^ Π in the floating-point temporary number 245: Send to a group of foreign-point temporary registers " 5. ΐ Λ can access the floating-point asset stored in the data cache 265, so that when the two-path 255 (from the floating-point register 245) executes the instruction, it can refer to the storage in ―Shell Cache 2 6 The data in 5. The hum Chuchuan order will be sent from the integer instruction list 240 to the integer register 250. The integer is stored in the Bayi storage circuit 260 and can be stored in the integer register 26. It can also be stored Take these instructions. Integer / man-in-storage circuit 入 Λ 入 / so that the positive number stored in the integer register 2502 & order can refer to the integer data stored in the data cache m for data Λ Embodiment of the invention 'The management circuit 205 mentions the data cache 265 2 ^' The two are more specific, that is, the performance level can control the data cache, the efficiency level or the second efficiency level (that is, in the high-power mode) ). For example, the flocking management circuit 205 can be # 2, A ^ = level, so that the data cache 265 is low in high power mode: Provides a second level of performance, so that the data cache 265 can be operated at 265 =. Those skilled in the art should know that although the data cache can be used here at the first or second efficiency level, according to the present invention In some embodiments, other performance levels can also be used. Fig. 3 is a block diagram showing a flocking management circuit according to an embodiment of the present invention. Please refer to Fig. 3, the flocking management circuit 3005 is from the operating system ( operating system), or one that is related to a trumpet of the invention description (13), which is established in a synchronous multi-flop processor. The management circuit 305 is configured to use the processing circuit established by the read allocation circuit 330 according to the present invention, and configure the processing circuit to be used by the synchronous multi-fiber processor.

It is used to improve the performance of the V system: 05. It also includes an efficiency level control circuit 340. The processing circuit is established by a synchronous multi-fiber processor. The current flat control circuit 34 can be processed according to the synchronous multi-floc: :-The number of batts' provides the efficiency level to the processing circuit. It is clear that when the number of batts currently operated by the 4γI two-synchronous multi-fiber processor is increased, the water control circuit 3 4 0 may provide a decreasing level of performance to the processing circuit related to the blobs operated by the multi-synchronous device. By responding to the establishment and termination of the blobs operated by the same processor, the performance level control circuit 340 may increase or decrease an internal count, thereby determining the number of blobs currently operated by the synchronous processor. When a person skilled in the art knows that the efficiency level provided to the processing circuit according to the present invention may have a system default value such as the first efficiency level (or high power mode). Therefore, when the floc is added, The efficiency level provided to the processing circuit can be reduced to reduce the efficiency and power consumption of the processing circuit. Those skilled in the art will know that the performance level can be provided to the processing circuit through a Xunmai line, where the signal line can conduct at least the first ^ A signal with two states of energy level and second performance level. For example, just after initializing (initia 1 i ze) the synchronous multi-fiber processor, the number of flocks operated by the synchronous multi-fiber processor is zero, which provides The system preset value for the performance level of the processing circuit is the first performance level preset by the system (high power mode

13145pif.ptd Page 18 200421180 V. Description of the invention (Formula 14)). When the floc is added and its total number finally exceeds a critical value, the performance level can be changed to a second performance level by changing the state of the signal used to indicate which performance level is to be used. Fig. 4 is a block diagram showing an efficiency level control circuit according to an embodiment of the present invention. Please refer to FIG. 4, a counter circuit 405 can receive information from the operating system or the flocculation circuit described with reference to FIG. 3 to determine the number of flops currently operated by the synchronization processor. If the received information is related to the creation of a new flop, for example, the counter circuit 405 will deduct the synchronous multi-flop processor that has previously started four flops, and then the counter circuit 405 will increase its count to reflect the synchronization The fact that the number of flocs currently operated by the multi-fiber processor is five. The counter circuit 405 can provide the number of clocks operated by the synchronous multi-channel controller to a comparator circuit 410. A cut-off value will also be included in the same value. The operating unit of the processing unit is provided with a *, which is provided together with the power of the comparator. The cut-off value can be used to indicate that the efficiency level of the number of units is exceeded, that is, ^ ^ ^ ^? When the number of I currently operated by the device is less than the threshold of Cen Yi% η Temple Temple, the effect provided to the processing circuit is: Ϊ Ϊ: ΐ The first-efficiency level of the high power mode. However, when the number of operations performed by the two or more processors exceeds a critical value, the performance level can be reduced to reduce the power consumption of the synchronous multi-processor. Ping is used to explain the flow chart of the efficient water supply system based on the embodiment of the present invention. Poetry and moxibustion go Chu e Banxi Mengkao Ke ## As shown in Figure 5 of the reference brother, when the synchronization Xiyang treatment family has just been initialized, the same boat did. ♦ The number of current operations of Tian Ming j ν Xige processor Zero (block 500). When the card is printed and printed by Feng Xi, but the processing is set up and finished in the door processor. 13145pif.ptd Page 19 200421180 V. Description of the invention (15) 'The multi-chip processor currently operated by the card_ Will decrease (block 505). For example, 'when the synchronous multi-flop processor currently operates four flocks, the value of N is four. When a batt is newly established, the value of N is increased to 5 ', and when one of the following blobs ends, the value of N will change to 4. • Righteousness

The number of batters currently operated by the synchronous multi-battle processor will be compared with that of a bat (block 51). If the number of J currently operated by the synchronous multi-fiber processor is less than or equal to the critical value ', the performance level control circuit will provide the first performance level to the processing circuit allocated to the flock (block 515). For example, if the processing circuit configured for the cache is the cache entry L described with reference to FIG. 2, the / Λ record: the body can access the tag memory and the data memory at the same time = (that is, it operates in the power mode) ). On the other hand, if the number of loops currently being operated by the Synchronous Multiplexer is greater than the critical value (block 510), the: level control emperor] circuit will provide a second level of performance for the processing of the loop: block (block 520 ). For example, in the embodiment described above with reference to FIG. 2, the memory can be operated at the second performance level, so that the data memory will be accessed only when: Just operate in low power mode). The sixth block is a block diagram of a cache memory according to an embodiment of the present invention. Referring to FIG. 6, a tag memory 610 is used for frame construction and is stored in a data memory 62. The address of the stored data. The standard memory 61G is accessed with the address of the data j = to be processed by the synchronous multi-processor. A tag comparison circuit 63 will compare the entries in the tag memory " with the address to determine the synchronization

200421180 V. Description of the invention (16) Whether the data required by the device is stored in the data memory 62. If the tag comparison circuit 630 decides that the required data is indeed stored in the body 62 ', it means that the iron is hit. No_, it means hidden. If a tag hit occurs, an output enable circuit 650 will enable the data output from the data memory 620. ,

▲ ▲ According to the embodiment of the present invention, the effect = level provided by the performance level control circuit is used to control how the tag memory 6 and the data memory 6 2 0 work. More specifically, if the cache memory circuit is provided with a first performance level, a data memory activation circuit 64 will start to be accessed at the same time as the tag memory 61 regardless of whether a tag hit occurs. Data memory 62. In contrast, if a second level of performance is provided to the cache memory, the data memory activation circuit 640 will not allow access to the data memory 62 unless there is a tag hit. 〃 Therefore, in the embodiment according to the present invention, in the high-power mode, the tag memory 610 and the data memory 620 can be accessed at the same time, thereby providing better performance. However, when in the low-power mode, only the The data memory 62 will be accessed only when the label 61 indicates a tag hit, because the power consumption of the cache memory can be reduced. FIG. 7 is a block diagram showing an instruction cache according to an embodiment of the present invention. Please refer to FIG. 7, the cache management circuit 700 allocates an instruction cache 722 to a new cache. The performance level control circuit included in the flop management circuit 300 provides an efficiency level to the instruction cache 722 to control how the instruction cache 722 operates. work

200421180 V. Description of the invention (17) More specifically, the instruction cache 722 can respond to the first performance level and operate in the high power mode, and also the frame constitutes the response to the second performance level and operate in the low power mode. As described above with reference to FIG. 5, the first performance level or the second performance level may be provided to the instruction cache 722 according to the number of blobs currently being processed by the synchronous multiprocessor. In addition, the instruction cache 722 can be operated at different performance levels in a similar manner to the above description with reference to FIG. 6. Among them, in the low power mode, the data memory 620 can be accessed only in response to a hit. For example, when it has been determined that the next 5 fe, body access is to access the same cache line (c a c h e 1 i n e), different performance levels may be provided to the instruction cache to allow it to perform direct access. This type 4 limitation can be avoided by a direct-addressed cache that allows reading random access memory (RAM) of the tag. This method can also avoid performing tag comparison. In addition, in the direct-address caching, the operation of converting the virtual address to the actual address can be avoided. Fig. 8 is a block diagram showing independent processing circuits having different performance levels according to an embodiment of the present invention. Please refer to FIG. 8. A first floating-point circuit 805 is configured to operate at a first efficiency level, and a second floating-point circuit 8 1 5 is configured to be a second lower than the first efficiency level. Operate at performance levels. In other words, the first floating-point circuit 805 is applicable to the high power mode 'and the second floating-point circuit 815 is applicable to the low power mode. A first integer / load-storage circuit 810 constitutes the processing performed at the first performance level, and a second integer / load-storage circuit 820 constitutes the processing performed at the second performance level. Floc management circuit

13145pif.ptd Page 22 200421180 V. Description of the invention (18) — 8 "〇 The frame, which provides two different levels of performance. More specifically, the b-th plane is supplied to the first floating-point circuit 805 and the first integer storage circuit 810. The second efficiency level provided by the management circuit 0 / load ^ ^ 5 ^. ^ ^ Circuit 8000 is a two-point circuit 815 and a second integer / load-store circuit 820. The two set point circuits 805 and the first integer / load-storage circuits 810, 815 operate at the first performance level, and the second floating-point circuit level is downloaded to the storage circuit 820, which can be configured for the second performance The second performance is from 1 ”: the relevant artist should know the first-efficiency level and the first when the other circuit 800 is required to be provided separately or at the same time. It should also be μm, the floating-point circuit and the integer / load-storage circuit provided The number can be greater than two. The grid-number / queue is implemented according to the present invention. When the number of synchronizations is less than or equal to the _ ', & The circuit's current multi-flop processor is currently operating on a monthly basis: water thousand. When the second floating-point circuit should be used, the second performance level is the second efficiency level. Therefore, When the number of times of the same + ^ number input-storage circuit 820 exceeds the critical value, all the ^ / evening processor (currently operated by the processor) can use the second floating point circuit 8/5: the first 2 With the newly established 820 multi-flop processor, the power consumption circuit is stored-stored Λ: technology; = floating-point circuit with integer / load and / or different circuit types (For example, different clock rates at this level, for example, in the mouth = hall device according to the present invention) operation. In the detailed example of the knife, and the simultaneous multi-float processing 13145pif.ptd page 23 200421180 5. Description of the invention ( 19) The point related to the action of the controller is the low-power mode of the clock rate of the multi-processor processor synchronized at t clock; In the lower figure 9 is shown a block diagram of the / κι # g # embodiment of the device: ;;; = The circuit of the synchronous multi-float processing circuit 900 is provided in the middle of the circuit and will respond to the management of the electric power. The provided electrical circuit 900 provides three different levels of efficiency.

Information: cache 965, first and second floating-point circuits 90. == :, one, and second integers / loading-store Leizheng qin Q9n, 915, and the first knowledge provided to the Hth electrician to familiarize with relevant skills For the first and first hand point circuits 905, 915 and the ρ, + u η, 920 efficiency levels provided to the first 筮 8 figure, you can refer to the _ day * operation. In addition, the data cache 965 and the instruction cache 930 'can be operated in the manner described above with reference to FIG. ^ R7lg! AAL 丄, fetching / lossing FIG. 2 and FIG. 7, respectively. Therefore, different processing circuits can be provided with different performances and different performance levels. #This can have a trade-off between the power consumption of the second processing (tradeQf f. For example, 1 j takes 3 to operate at the first performance level. The data cache 265, the -V flute, the second foreign point circuit 905, 915, and the first and second integer / load: 9H '920, can operate at the second performance level. This = a combination of other performance levels. Figure 10 is used to show a block diagram illustrating the operation of an embodiment of the performance level control circuit included in the circuit 90G shown in Figure 9. Lu specifically stated that the performance level control circuit includes the following components. A β 乂1 0 0 0, the counter 1 000 responds to the new establishment and synchronization in the multi-fiber processor.

200421180 V. Description of the invention (20) The change of the treated floc & ′ increases or decreases its count. Nos. 1015, 1 020, 1 225, each of which is "two registers", and said that the current correction of the south m U — Special comment 15 can store the individual thresholds corresponding to the number of flocs treated in the same process. : Individual Πί: the first-register m5 of the critical value, = sex ί: ίΓ: ratio * circuit 1 030. The second threshold of the second threshold is stored in the second comparator circuit 1 035. Save! 〇 Series: The register is called 5, which is the third temporary mother that is electrically connected to the third comparator. The comparator circuits are 1030, 1035, 1 () 4 (). The number of processors currently operated by the processor will be the first comparator if the first comparator circuit ΐ = the number of processors is greater than the first critical value stored in the first register 1015, then the first comparator The circuit 1030 will generate two Λ, ♦ output to the data cache 965 at a performance level of 1045. Therefore, when the number of flocs currently operated by the multi-flop processor exceeds the threshold value stored in the first temporary; °, the performance level in the data cache 965 will flatten to the second performance level (that is, from = Low power mode). 1. Eight and two. If the second comparator circuit 1035 decides the synchronous multi-processing, the number of t Γ is greater than the critical value stored in the second register 1 0 °, and the n comparator circuit 1 〇35 will produce an output value level mo. Therefore, when the number of simultaneous multi-flop processors currently operating 30 exceeds the critical value stored in the second register 1 020, the 'instruction cache 200421180 V. Description of the invention (21) The performance level of 30 From the first performance level is to change from high power mode to low power mode). If the third comparator circuit 1040 decides that the number of co-workers is larger than the threshold value stored in the 15-mesh place at the M; the threshold value in the register 1025 of the first brother, Then the second comparator circuit 1 040 will produce must-have circuits 905, 915, and the first and second net points 920 at an efficiency level of 1055. Therefore, the first and second storage circuits 气, 气 ', and' 'storage circuits are The number exceeds the performance level of the processing circuits currently operated in the third temporary >v; 0 ^ 2 ^ processing ^, when the threshold value in the combiner 1 025, the level (that is, changed from high power mode For ^ the first effect, the artist should know the output to the float mode). # Xi Related Techniques level 1 055, the performance of the integer / load-storage circuit is based on the method described above with reference to Figure 8. Control ^ Road map paste: display " V is used to explain the efficiency of the horizontal control circuit as shown in Figure 10, the method of initialization of the synchronous multi-floating processor. 丄; :: 二 :: 刚 _ 里 ~ 1, : (Fang Gui 1100). § When a new multi-fiber processor is established or new, the synchronous multi-fiber processor currently operates 1 plus == provides a representative Step multi-flop processor currently. The number of 2% of the number N (box 1105). First, such as the elimination of the same step multi-flop processor is currently operating less than or equal to the number of blocks = an ancient block 1110) , All processing circuits will continue to operate at the same efficiency level (block 1115). On the other hand, if the number of clocks currently operated by the synchronization processor exceeds the first threshold (block, the efficiency level is 1) 〇4 5 The input processing circuit will start to operate at the second 13145pif.ptd page 26 200421180 V. Description of the invention (22) Political month b level (that is, low power mode) operation (block 1 1 2 0). When as # 果 黄 Synchronous multi-fiber processor is currently operating less than or equal to the number of blocks (block 1125), then when the performance level is Cong (as described above) == the management circuit continues to operate at the second performance level, the performance

^ 50 (”Efficiency level 1 055) The input processing circuit will turn on X and keep it on) Operate at the first performance level (block " Second-way start) (Boundary ^ 5 3 If the number exceeds the second clinical efficiency level of 102, the processing circuit inputted at the efficiency level of 1 050 together with it will start with the first processing circuit (and hold the bribe & energy level). Operation (block 1135), and if the performance level is: Λ processing circuit ', it will operate at the-performance level.-First = the number of batts currently operated by the pro processor is less than or equal to the block 1140)' then the performance level 1 055 input processing efficiency level operation (square processing circuit, will continue to maintain the second 7 ,, Zha (block Η 4 5). If the number of simultaneous multi-fault virtual cry a made more than the second series of processing goals Do not operate the input processing circuit: ^, value (box "4〇) 'then the efficiency level _ (j, θ) starts (and continues to) operate at the second efficiency level (also = 疋 in low power mode) ( Box ii5G). "VJ on the Water Processor: According to an embodiment of the present invention, Synchronous multi-fiber circuits are used to construct a plurality of processing circuits. Among these processing numbers, the multiple multi-fiber processors are currently operated by a non-synchronous multi-fiber processor. Two: Fuck !: For example, As far as the processing circuit in the mini / hand unit or negative material cache according to the present invention is concerned with the multi-float at 13145pif.ptd page 27, the description of the invention (23) the processing circuit in the processor is currently The operation and operation of high-power can be based on synchronous multi-fiber processing. 'Mo mode or low-power mode operation In addition, when the multi-fiber processor is synchronized, the efficiency of the processing circuit can be reduced. This increases the power consumption of the logic circuit, and thereby reduces the shoulder-related advantages. For example, t, the processing circuit invented according to the framework of the multi-processor processor of this development step can be used to provide different = $ points In the embodiment, the operation is performed at different clock speeds based on the probability and / or the level of different circuit types. For example, in a CMOS device according to this type) the point unit or data cache is synchronized with that in the embodiment. , Such as the floating processing circuit, According to the synchronous multi-flood processing = floating action correlation number in the processor, the operation is performed in a high-power mode with a high clock rate. A low-power mode with a low clock rate X Although the present invention has been better implemented The example is disclosed as above, but the present invention is limited. Anyone skilled in this art can make various changes within the scope of the law, the scope of the patent application attached to the spiritual sacrifice of Shi Moyue. The definitions shall prevail. Follow the diagrams of 200421180. The diagrams are briefly explained. The diagrams are briefly shown in Figure 1. + "Figures.", A block diagram of a conventional synchronous multi-fiber processor architecture. Figure 2 shows a block diagram. Figure 3 of the synchronous multi-fiber processor according to the embodiment of the present invention is a block diagram of county g + j. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ... The performance water of the embodiment of the invention. Fig. 7 shows a block diagram of a cache memory according to an embodiment of the present invention-> flil 4e 1 device. Figure 8 shows a block diagram of a multi-fiber synchronous processing according to an embodiment of the present invention. A synchronous multi-flop processor according to an embodiment of the present invention is shown in FIG. 9; a block diagram of tp i is shown in FIG. FIG. 10 is a block diagram of a pepper eaves a circuit according to an embodiment of the present invention. Figure 11 of the performance level control according to the embodiment of the present invention is a flowchart of a useful > capable level control circuit to illustrate the effect diagram marking according to the embodiment of the present invention: 13145pif.ptd page 29 200421180 Schematic description 200 Synchronous multi-flop processor 205 Fuzz management circuit 210 Fetch circuit 215 Program counter 220 Instruction cache 225 Decoder 230 Register rename circuit 235 Floating point instruction queue 240 Integer instruction queue 245 Floating point Register 250 Integer register 255 Floating point circuit 260 Integer / load-store circuit 265 Data cache 300 Float management circuit 305 Float management circuit 330 Float configuration circuit 340 Efficiency level control circuit 405 Counter circuit 410 Comparator circuit 50 0 ~ 5 2 0: flow step 610 tag memory 620 data memory 630 tag comparison circuit

13145pif.ptd Page 30 200421180 Schematic description 640: Data memory start circuit 650: Output start circuit 700: Float management circuit 722: Instruction cache 8 0 0: Float management circuit 8 0 5: First floating point circuit 810 : First integer / load-store circuit 8 1 5: Second floating-point circuit 820: Second integer / load-store circuit 9 0 0: Float management circuit 9 0 5: First floating-point circuit 910: First Integer / load-storage circuit 9 1 5 ·· Second floating-point circuit 92 0: Second integer / load-storage circuit 930: Instruction cache 9 6 5: Data cache 1 0 0 0: Counter 1 0 1 5: first register 1 0 20: second register 1 0 2 5: third register 1 0 3 0: first comparator circuit 1 0 3 5: second comparator circuit I 040: first Three comparator circuit II 0 0 ~ 11 5 0 · • Process steps

13145pif.ptd Page 31

Claims (1)

200421180 VI. Application scope of patents 1 of which is the Synchronous Multiple Float (SMT) processor, which is related, and the number of -1 in the device is the same as the number of…. It is effective for the synchronous multiple flop processing target u :: of a synchronous multi-fiber processor, which is equal to-critical value, it should be; one or two :: the number of these flocks is less than or can be operated horizontally, and the four-circuit circuit frame structure is composed of -th-effect ^ A ^ ^ a ^ ^ two efficiency level operations. The structure of the road frame includes the synchronous multi-flood processing H as described in item 1 of the scope of the patent application. It also writes 1 · Effective / 1 flat control circuit. The structure of the frame is based on the synchronous multi-float. The number of processing the flocs, for the at least-processing circuit, JrT Semi-Shen Λ11 Λ11 Synchronous multi-flop processor described in item 3, the processing circuit in the bean; two:; =; Provided to the at least-where, when the synchronous multi-floc processing Λ-Λ-Λ energy level; and the energy of the less-processing circuit Γ: Π:; Γ road will be provided to the -second efficiency level + reduced to low At the first performance level of 13145pif.ptd, page 32, 200421180 6. Patent application scope ΐ '2 · The synchronous multi-fiber processor described in item 4 of the patent scope of the application, where the two values include a first critical value, Moreover, when the number of the synchronized multi-floating processor item 2 is equal to or greater than a second critical value higher than the first critical value, the performance level control circuit will further provide the at least one J The performance level of the processing circuit is reduced to the second performance level; a second performance level $$ 6 · The synchronous multi-flop processor as described in item 1 of the patent application scope, wherein: Lei: The logic circuit includes a cache memory circuit, and the cache memory caches a memory and a data The memory is structured to cache the data at the same time as the tag memory; and〗, the access is lower, the memory is lower than the memory, and the memory is structured to be the cache memory circuit. -When operating at the second efficiency level, the cached data is provided in response to a hit of the target " self & body.哕: The enemy is as claimed: The synchronous multi-flop processor described in item 6 of the patent scope, in which the μ fetch A fe body includes at least one data cache memory, which is run by multiple instructions. ^ The wooden structure is used to store the rack furnace. The instruction cache memory is used to store the instructions that are operated on the relevant data. Please synchronize as described in item 6 of the patent scope; although the processor is operating at the second performance level, the data memory embers ringing a non-hit in the tag memory to provide cached data ? A μ ', the synchronous multi-fiber processor described in the first item of the patent scope, wherein at least one processing circuit includes a floating point unit. Eight in 10. 10. The synchronous multi-fiber processor as described in item 9 of the scope of patent application, which 200421180 In the case of the floc processor, the following is included: = includes a first floating point unit, which is structured to operate when the number of flocs operated before the synchronization is less than or equal to a critical first performance level. The multi-fiber processor further includes a second floating-point unit, which is structured to operate at a second performance level that is lower than the performance level when the threshold is greater than the critical value. 11 · The synchronous multi-fiber processor according to item 丨 of the patent application, wherein the at least one processing circuit includes an integer register. w ^ 2 · As described in the second patent application scope of the synchronous multi-fiber processor, 苴 Κ = system architecture to respond to the multiple processes in the synchronous multi-fiber processor; Increasing or decreasing the number of the blobs operated by the synchronization processor respectively. ^ 3. According to the synchronous multi-fiber processor described in item 丨 of the scope of the patent application, "at least one processing circuit includes a first processing circuit, which is the structure of the floc Count “the first one operated: floc:” coefficient rack = when the number of a series increases above the critical value, Ml operates at a second efficiency level of the first efficiency level. Call below ^ 4. Synchronous multi-fiber processor as described in item i of the scope of patent application. Straight! Two horizontal control circuit architecture to respond-new production 1, ° by which 5 specialization-critical value of the synchronous multi-fiber processor. The number of operations currently performed by the processor is increased to greater than the threshold value. This reduction is provided to the = 200421180 VI. The scope of the patent application is one less than the treatment power. 15 · When the critical value of the water before the application is applied, it is as low as a plurality of 16. If the water used in the application is currently operated above the performance level, A second 17 · — a number of treatments that were performed before an efficiency level 1 8 · If you apply the performance water plus the synchronization for these operations to deal with the current performance of a current level, please patent the level control circuit The synchronous multi-floating processor described in item 2 of the multi-floating processor that will provide the decreasing performance water level patent control circuit is structured so that when the number of synchronous multi-floating processors exceeds a plural number An efficiency level of each of the at least one processing circuit that increases the critical value decreases one of them. The synchronous multi-fiber processor described in item 2 is structured to respond to the first processing circuit when the number of the synchronous multi-fiber processor is lower than or specialized in a critical value, and is provided to a first processing circuit. A first and second processing circuit provides a water efficiency level lower than the first efficiency. Synchronous multiple loop control circuit, a circuit of these loops, provides a patentable scope of flat control circuits, a new processor, and a new level of operation to provide a level of performance. Patent Scope Multi-Factor Processor 19 • As stated in the application, the synchronous processor includes: a system architecture to determine a performance level in the synchronous multi-processor based on the number of synchronous multi-processor processors. The synchronous multi-fiber processor described in item 17 is more structured in response to the generation of a new floc, increasing the number of the previously operated flocs to increase the number, and the frame structure is based on the synchronized multi-floc The new number of flocs, the synchronous multi-flop processor described in item 17 of the processing circuits, the number of the current flocs that are currently operating is less than 200421180 VI. When the scope of patent application is equal to a critical value, the performance level control circuit will provide s_ Electricity :: This / energy level will be increased to-the number of = = when the number exceeds the number of multi-flop processors The two of the processing circuits that are currently operating are equal to each other: provide to the second efficiency levels. + $ Lower than the 苐 -efficiency level-The synchronous multi-fiber processor described in item 19 of the China-Israel Shenli scope; the mr system architecture responds when the synchronous multi-fiber processor stays, The number of blobs is lower than or equal to a critical value, and when the critical value is raised, the first level of the processing circuit is provided: 7%, and the second processing circuit is provided below the first performance. A second efficiency level for water ten. > j 1 * The synchronous multi-fiber processor according to item 7 of the declared patent scope, and the second processing circuit includes one of a floating point unit and a data cache memory. ^ 2. The synchronous multi-fiber processor as described in item 17 of the scope of the patent application, wherein when the number of the flocs currently operated by the synchronous multi-fiber processor is small and equal to a critical value, the processing The circuit frame is configured to operate at a first-energy level; and%, wherein when the number of the flops currently operated by the synchronous multi-fiber processor is greater than the critical value, the processing circuits are at a second energy level operating. Double 23 · — a kind of synchronous multi-fiber processor, including: a flock management circuit, a frame structure, when a plurality of flocks are established, the 13145pif.ptd Page 36 200421180 VI. Scope of patent application Synchronous multi-fiber processor Phase multi-fiber processor operating a performance level control spinner currently operating results, for these processing 24. As in the patent application, the at least one A critical number of critical values. 2 5 · As in the patent application, when the synchronized multiples are equal to one or more of the at least one of the processing circuits, when the same number exceeds a flat second efficiency of the at least one to the processing circuits 2 6 · If the performance level control in the application for a patent is less than or equal to the low of the at least the floppies provided to the processes 2 7. If the performance level control in the application for a plurality of processing circuits is assigned to And the circuit at the synchronization; and the circuit frame is configured to provide one of a plurality of performance levels according to a circuit which compares a number of the locations at the synchronized multiple locations with at least one threshold value. The synchronous multi-fiber processor according to the scope item 23 includes the multiple multi-fiber processors operated by the synchronous multi-floc processor. When the number is less than the _ threshold value, the performance level control circuit will provide the performance level to a first performance level; when the threshold value of the blobs currently operated by the b multi-fiber processor, the performance The level control circuit will provide the performance level to be lower than the first performance level. The synchronous multi-fiber processor described in item 23 of the scope has a circuit architecture that responds to the generation of a new flop, thereby increasing a critical value of the current multi-fiber processor to be greater than the at least-critical value. This ^ a level of performance of the circuit. The synchronous multi-fiber processor described in item 2 in item 22 has a circuit architecture that when the synchronous multi-fiber processor is 200421180 6. The number of the flocs operated before the scope of the patent application exceeds a plurality of increasing thresholds At each critical value of the value, the efficiency level provided to the processing circuits is reduced to one of a plurality of decreasing performance levels. 28. The synchronous multi-fiber processor according to item 23 of the patent application scope, wherein the performance level control circuit is configured to respond to the number of the multiple flocks currently operated by the synchronous multi-fiber processor from less than or Equal to the at least one critical value 'is raised to be greater than the at least one critical value, maintaining a first efficiency level for a first processing circuit & and providing a second processing circuit below the first efficiency level A second level of effectiveness. 29 · —A kind of cache memory related to a synchronous multi-fiber processor, wherein the cache memory includes a tag memory and a data memory ^, and ^ according to the current operations of the synchronous multi-fiber processor It can access the tag memory and the data memory at the same time, or first access the tag memory and then the data memory. 30. According to the cache memory described in item 29 of the scope of the patent application, Lizhong Plastic should be less than or equal to the -critical value of the synchronous multi-fiber processor currently operating the number of the two flocks, which can be accessed simultaneously The tag memory and the data memory 31. If a patent is filed, the synchronous multi-flop processor will respond in the memory when the threshold is reached. A cache memory in the tag memory currently being operated as described in the scope item 29, wherein when the number of flashes is greater than one hit, the data can be accessed. 32. A kind of synchronous multi-flash processor The operation method includes: according to a number of the flocs currently operated by the synchronous multifiber processor, 200421180 At least one processing circuit provides a performance level. Supplying cattle: Application: The operation method described in item 32 of the patent scope, wherein after the providing step, the method further includes: Counting the number of the battens currently being operated by the Synchronization Synchro Processor, /, α boundary The values are compared to provide the performance level to the at least one processing circuit. ~ Package 34. The method of operation described in item 32 of the scope of patent application, which after the comparison method further includes: 一 响 # 应. A new batch just started in the synchronous multi-fiber processor increases the number of the multiple flocks currently operated by the same processor; and Responding to a batch that ends in the synchronous multi-fiber processor, reducing the number of the multiple flocks currently operated by the synchronous multi-fiber processor. 35. The operation method as described in item 34 of the scope of patent application, wherein the providing step further includes: ^ If the number of the flocs currently operated by the synchronous multi-fiber processor is less than or equal to the critical value, then Providing a first performance level to the at least one processing circuit; and, if the number of the flops currently operated by the synchronous multi-fiber processor exceeds the critical value, providing a level lower than the first performance level Give the at least one processing circuit. $ 一 效 此 3 6 · The operation method described in item 35 of the scope of patent application, further includes: providing a reduced level of performance to the same as used to increase the number of current operations of the synchronous multi-processor The number of related new treatments Page 39 200421180 Circuit to exceed these additional additional critical values 37 · —a type of synchronous multi-fiber processor, including: providing a performance level of at least 3 8 according to the number of synchronous multi-fiber processors Including: a device for a one-to-one processing circuit of the flocs. The synchronous multi-floc processor described in the above item, further, the synchronous multi-floc processing + M > ^ ^ 15 The number of the flocks just made by the mesh is compared with the '^ cutoff value, and the face q, A device for a circuit.乂 Provide this level of efficiency to the at least one processing 39. The synchronous multi-fiber processor described in item 37 of the scope of patent application, further comprising: in response to a new flop just started in the synchronous multi-fiber processor, increasing A device of the number of the flocs currently operated by the synchronous multi-fiber processor; and in response to a flop that ends in the synchronous multi-floc processor, reducing the number of flocs currently operated by the synchronous multi-floc processor The number of a device. 40. The synchronous multi-fiber processor as described in item gg of the declared patent scope, the providing device in the basin includes: 〃 § The number of the multiple flocks currently operated by the synchronous multi-fiber processor is less than or equal to the threshold When a value is provided, a first performance level is provided to a device of the at least one processing circuit; and, > when the number of the flocs currently operated by the synchronous multi-fiber processor exceeds the critical value, provide A second-effect Huping that is lower than the first efficiency level is provided to a device of the at least one processing circuit. 200421180 6. Scope of patent application 41. The synchronous multi-fiber processor described in item 40 of the scope of the patent application, plus: w The ruler will reduce the level of performance provided to the purpose of increasing the synchronous multi-fiber processor. A device that operates the number of the new floes associated with the number of new flocculation processing circuits to exceed the added extra critical values. 42 · A computer program product port for operating a synchronous multi-fiber processor includes: σσ Computer-readable media with electronically readable code, and the computer-readable program products include: μ ^ The computer can read the code, and it is structured to provide a performance level to at least one processing circuit in the synchronous multi-fiber processor according to a number of the multiple-fiber processor operated by the synchronous multi-fiber processor. 43. The computer program product as described in item 42 of the scope of patent application, further comprising: ^ computer-readable code, a framework for setting the number of the synchronized multi-processors as the number of operations, Compare with a threshold value to provide the efficiency level to the at least one processing circuit. 44. The computer program product described in item 42 of the scope of patent application, further comprising: ^ Computer readable code, the system is structured to respond to a new program just started in the synchronous multi-processor, and increase the synchronous multi-processor The number of the flocs currently operated by the flocking processor; and the computer can read the code, and the system is structured to respond to a flocking that ends in the synchronous multi-fiber processor, reducing the current operating of the multi-fiber processor. The 13145pif.ptd Page 41 200421180 Sixth, the scope of the patent application The number of support.粑 :: The computer program product described in Item 42 of the scope of profit, wherein according to item ": The computer-readable code provided by the computer includes:" Computer-readable code "system structure when the synchronization is more When the number of the batches is less than or equal to the critical value, the level is provided to the at least one processing circuit; and the computer can read the code, which is necessary The first and second efficiency levels operated by the operator are the first and second efficiency levels of g and §. When the threshold value is exceeded, the efficiency level is lower than the 46 ^ ^-brother level-the at least one processing circuit. Including: · The computer program product described in Item 43 of Zhongli's patent scope has more electric shame, and the system can be used to reduce the supply to increase the number of Tong Niu Xi ^ Zhengyue • Shui Qian, mention this The number of the cuts is 1 additional point t] The additional threshold of the cuts: the new cut-related processing circuit, "exceeds the added