KR20040075287A - Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating - Google Patents

Abstract

PURPOSE: An SMT(Simultaneous Multi-Threading) processor, a computer program product operating other performance levels based on number of operating threads, and an operating method for the same are provided to increase performance while reducing power consumption. CONSTITUTION: When a new thread is generated in the SMT processor(200), a thread managing circuit(205) allots a set of processing circuits used by the new thread. The processing circuits include a program counter(215), a set of floating point registers(245), and a set of integer registers(250). A fetch circuit(210) fetches a command from a command cache(220) based on a position provided from the allotted program counter, and the command is provided to a decoder(225). The decoder outputs the decoded command to a register renaming circuit(230). According to a form of the command provided from the register renaming circuit, the renamed command is provided to a floating point command queue(235) or an integer command queue(240) by the register renaming circuit.

Description

Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on concurrent multithreading processor circuits, and how to operate them at different performance levels based on the number of threads running on a number of operating threads and methods of operating}

TECHNICAL FIELD The present invention relates to a computer processor architecture, and more particularly, to simultaneous multi-threading (SMT) computer processors, related computer program products, and methods of operating them.

Simultaneous Multi-Threading (SMT) is a processor architecture that uses hardware multithreading to allow issues to be issued to multiple independent threads during each cycle. Unlike other hardware multithreaded structures in which only one hardware context (i.e. one thread) is active in any given cycle, the SMT structure shares processor resources to all thread contexts simultaneously. Can be allowed to do.

The SMT processor may utilize wasted cycles to perform instructions that may reduce the effects of long latency operations within the SMT processor. In addition, performance can increase as the number of threads increases, while the power consumed by an SMT processor can increase.

A block diagram of a conventional SMT processor is shown in FIG. Operation of the conventional SMT processor of FIG. 1 is described by Dean M. Tullsen, Susan J. Egger, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, "Exploiting Choice: Instruction Fetch and issue on an Implementable Simultaneous Multithreading Processor ", 23rd Annual International Symposium on Computer Architecture, pp. 191-202, 1996). Since the structure and operation of the conventional SMT processor is well known in the art, a detailed description thereof will be omitted.

It is an object of the present invention to provide a simultaneous multithreading (SMT) processor that can increase performance while reducing power consumption.

Another object of the present invention is to provide a method of operating the simultaneous multithreading processor.

Another object of the present invention is to provide a computer program product for operating the simultaneous multithreading processor.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a conventional simultaneous multithreading (SMT) processor structure.

2 is a block diagram illustrating an embodiment of an SMT processor according to the present invention.

3 is a block diagram illustrating an embodiment of a thread management circuit according to the present invention.

4 is a block diagram showing an embodiment of a performance level control circuit according to the present invention.

5 is a flowchart showing an embodiment of a performance level control circuit according to the present invention.

6 is a block diagram illustrating an embodiment of a cache memory according to the present invention.

7 is a block diagram illustrating another embodiment of an SMT processor according to the present invention.

8 is a block diagram illustrating another embodiment of an SMT processor according to the present invention.

9 is a block diagram illustrating another embodiment of an SMT processor according to the present invention.

10 is a block diagram showing another embodiment of a performance level control circuit according to the present invention.

11 is a flowchart showing another embodiment of a performance level control circuit according to the present invention.

Embodiments according to the present invention described below may provide processing circuits, computer program products, and methods that operate at different performance levels based on the number of threads operated by an SMT processor.

In some embodiments in accordance with the present invention, processing circuits associated with thread operation in an SMT processor, i.e., processing circuits such as a floating point unit or data cache, are currently operated by the SMT processor. It may operate in one of a high power mode and a low power mode based on the number of threads that become. In addition, as the number of threads operated by the SMT processor increases, performance levels of the processing circuits may decrease. As such, the architectural benefits of the SMT processor may be provided to reduce the amount of power consumed by the processing circuits associated with the threads. In addition, the SMT processor may operate at the same power but at higher performance or consume more power than conventional SMT processors but at higher performance levels.

In some embodiments according to the present invention, the processing circuit is configured to operate at a first performance level when the number of threads currently operated by the SMT processor is less than or equal to a threshold and is currently operated by the SMT processor. Can be configured to operate at a second performance level when the number of fields is greater than the threshold.

In some embodiments according to the present invention, a performance level control circuit may be configured to provide a performance level for the processing circuit based on the number of threads currently operating by the SMT processor. In some embodiments according to the present invention, the performance level control circuit increases the performance level provided to the processing circuit to a first performance level when the number of threads currently operated by the SMT processor is less than or equal to a threshold. You can. The performance level control circuit may reduce the performance level provided to the processing circuit to a second performance level lower than the first performance level when the number of threads currently operated by the SMT processor exceeds the threshold. .

In some embodiments according to the present invention, the performance level control circuit provides the performance provided to the processing circuit when the number of threads currently operated by the SMT processor exceeds a second threshold value greater than the first threshold value. The level is further reduced to a third performance level lower than the second performance level.

Various embodiments of varying performance levels may be provided in accordance with the present invention. For example, in some embodiments according to the present invention, the processing circuit can be a cache memory including a tag memory and a data memory. Wherein the data memory is configured to provide cached data simultaneously with access to the tag memory when the cache memory circuitry operates at a first performance level.

The data memory may be configured to provide cached data in response to a hit in the tag memory when the cache memory circuit operates at a second performance level lower than the first performance level.

In some embodiments according to the present invention, the cache memory may be at least one of a data cache memory configured to store data and an instruction cache memory configured to store instructions. In some embodiments according to the present invention, the data memory is configured to not provide cached data in response to a miss in the tag memory when the cache memory circuit operates at the second performance level. Can be.

In some embodiments according to the present invention, the processing circuit may be a floating point unit. In some embodiments according to the present invention, the floating point unit may be a first floating point unit configured to operate at a first performance level when the number of threads operated by the SMT processor is less than or equal to a threshold. have. The SMT processor may further include a second floating point unit configured to operate at a second performance level lower than the first performance level when the number of threads operated by the SMT processor is greater than the threshold.

In some embodiments according to the present invention, the performance level control circuitry may be configured to increase or decrease the number of threads currently operating by the SMT processor in response to threads that are each created and completed in the SMT processor. Can be.

In some embodiments according to the present invention, the second processing circuit is configured to operate at a second performance level that is greater than the threshold and is lower than the first performance level in response to the number of threads currently operating in the SMT processor. It is composed.

In some embodiments according to the present invention, the performance level control circuitry is configured to increase the number of threads currently running by the SMT processor from a value less than or equal to a threshold to a value greater than the threshold. And may be configured to reduce the performance level provided to the at least one processing circuit in response to the generation. In some embodiments according to the present invention, the performance level control circuit is configured to reduce the performance level of the processing circuit by a plurality of levels when the number of threads currently operated by the SMT processor exceeds each of a plurality of rising thresholds. It can be configured to reduce one of the performance levels.

In some embodiments according to the present invention, the performance level control circuit maintains a first performance level for a first processing circuit and increases the SMT from a value less than or equal to a threshold to a value greater than the threshold. The second processing circuit may be configured to provide a second performance level lower than the first performance level in response to the number of threads currently operated by the processor.

In other embodiments according to the present invention, the performance level control circuit may be configured to provide a performance level to processing circuits within the SMT processor based on the number of threads currently operating by the SMT processor.

In still other embodiments according to the invention, the thread management circuitry may be configured to assign processing circuits associated with the SMT processor to threads that are operated on the SMT processor when threads are created. The performance level control circuit may be configured to provide the processing circuits with one of a plurality of performance levels based on the number of threads currently operating by the SMT processor compared to at least one threshold.

In still other embodiments according to the present invention, a cache memory associated with an SMT processor may be a tag memory and data simultaneously accessed or sequentially accessed with the tag memory based on the number of threads currently operated by the SMT processor. Memory may be provided.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

The invention may be practiced as circuits, computer program products, and methods. Thus, the present invention may have a hardware embodiment, a software embodiment, or an embodiment combining software and hardware. The invention may also take the form of a computer program preparation on a computer-usable storage medium having computer program code. Hard disks, CD-ROMs, optical storage devices, and magnetic storage devices may be used as the computer storage medium.

Computer program code or "code" for performing the operations according to the invention may be written in JAVA Smalltalk or object oriented programming languages such as C ++, JavaScript, Visual Basic, TQSL, Perl or various other programming languages. have. Software embodiments of the present invention need not be implemented with a particular programming language. Portions of code can be fully executed on one or more systems used by an intermediary server.

The code may be executed entirely on one or more computer systems or partly on the server and partly on the client device or on a proxy server midway in the communication network. have. The client device may be connected to a server on a LAN or WAN (eg, the Internet) or the connection may be made via the Internet (eg, via an Internet Service Provider). The invention may be practiced using various protocols on various types of computer networks.

The invention is described below with reference to block diagrams and flow charts illustrating methods, systems, and computer program products according to embodiments of the invention. Obviously, each block of the block diagrams and flow charts may be performed by computer program instructions. These computer program instructions may be directed to a simultaneous multithreading (SMT) processor circuit, a special purpose computer, or other programmable data processing device such that these instructions generate means for performing the functions described in the block diagram and / or flow chart. Can be provided.

These computer program instructions may be stored in computer-readable memory. The computer readable memory instructs the computer or other programmable data processing apparatus such that the instructions stored in the computer readable memory produce an article of manufacture comprising instruction means for performing the functions described in the block diagram and / or flowchart. You can direct.

Computer program instructions may be loaded into an SMT processor circuit or other programmable data processing device such that a series of operating steps are performed on a computer and / or other programmable device. These instructions, loaded into the SMT processor circuit or other programmable data processor, may provide steps to perform the functions described in the block diagram and / or flowchart.

Embodiments in accordance with the present invention may provide processing circuits related to the operation of threads in an SMT processor. These processing circuits are configured to operate at different performance levels based on the number of threads currently operating by the SMT processor. Different performance levels may include different operating speeds and / or different levels of accuracy of the circuits. In some embodiments in accordance with the present invention, processing circuits may operate at different clock speeds and / or use other circuit types to provide different performance levels. For example, in some embodiments in accordance with the present invention, processing circuits such as a floating point unit or data cache associated with the operation of a thread in an SMT processor are based on the number of threads currently operating by the SMT processor. Can operate in either a high power mode at a high clock rate or a low power mode at a low clock rate. In addition, when the number of threads operated by an SMT processor increases, the performance levels of the processing circuits can be reduced and thus the architectural advantages of the SMT processor can be provided to reduce the amount of power consumed by the processing circuits associated with the threads. have.

In embodiments according to the present invention, it is obvious that a plurality of threads are executed in parallel with each other. As used herein, a "thread" may be a separate process with associated instructions and data. A thread can mean a process that is part of a parallel computer program with multiple processes. A thread can also mean a separate computer program that runs independently of other programs. Each thread may have an associated state defined, for example, by respective states for related instructions, data, program counters, and / or registers. The relevant state for a thread may include sufficient information about the thread being executed by the processor.

In some embodiments in accordance with the present invention, the performance level control circuitry is configured to provide respective performance levels to processing circuits allocated to threads created in the SMT processor. For example, the performance level control circuit may provide a first performance level for the processing circuit to operate in the high power mode and provide a second performance level to operate in the low power mode. In still other embodiments according to the invention, an intermediate performance level (ie, performance levels between high and low power) is provided by the performance level control circuit.

In some embodiments of the present invention, the processing circuits operating at different performance levels may be cache memory including a tag memory and a data memory. When the cache memory is operating in the first performance level (ie, high power mode), the tag memory and the data memory can be accessed simultaneously regardless of whether the access to the tag memory is a hit or not. Simultaneous access of the data memory can provide greater performance because the hit rate in the tag memory can be higher. Alternatively, the cache memory may operate at a second performance level (ie, low power mode) in which the data memory is accessed only in response to a hit in the tag memory. Thus, in the event of a tag miss, some of the power consumption associated with accessing the data memory can be reduced.

In still other embodiments according to the present invention, the processing circuits associated with the operation of the threads may be instruction caches and other forms of processing such as floating point circuits or integer / load-store circuits. Circuits. In addition, each of these processing circuits may operate at different performance levels. For example, in some embodiments in accordance with the present invention, cache memory, instruction cache, and floating point circuits, and integer / load-store circuits may operate simultaneously at different performance levels.

In still other embodiments according to the present invention, the same type of processing circuits (such as floating point circuits and integer / load-store circuits) may be used where some of these circuits operate at a first performance level and others are It may be divided into different performance categories to operate at the second performance level. For example, in some embodiments in accordance with the present invention, some of the floating point circuits are configured to operate in a high power mode while other floating point circuits are configured to operate in a low power mode.

2 is a block diagram illustrating an embodiment of an SMT processor according to the present invention.

According to FIG. 2, when a new thread is created in the SMT processor 200, the thread management circuitry 205 allocates a set of processing circuits for use by the newly created thread. The allocated processing circuits may include a program counter 215, a set of floating point registers 245, and a set of integer registers 250. Other processing circuits can also be allocated to newly created threads. Once the thread is complete, the allocated processing circuits can be released so that they can be reassigned to the sequentially created threads.

The fetch circuit 210 fetches an instruction from the instruction cache 220 based on the position provided by the assigned program counter 215 and the instruction is provided to the decoder 225. The decoder 225 outputs the decoded command to the register renaming circuit 230. Depending on the type of instructions provided by the register renaming circuit 230, the renamed instructions may be generated by the register renaming circuit 230 by a floating point command queue 235 or an integer command queue ( For example, if the form of the instruction provided by the register laming circuit 230 is a floating point instruction, the instruction is stored in the floating point instruction queue 235, while the register renaming circuit ( If the command provided by 230 is an integer command, the command is stored in the integer command queue 240.

Instructions from floating point command queue 235 or integer command queue 240 are stored in associated registers for execution by respective fluting point circuit 255 or integer / load-store circuit 260. In particular, floating point instructions are passed from floating point command queue 235 to a set of floating point registers 245. Instructions in floating point registers 245 may be accessed by floating point circuits 255. The floating point circuits 255 may also have a floating point stored in the data cache 265, such as when instructions performed by the floating point circuits 255 refer to data stored in the data cache 265. Data can be accessed.

Integer instructions are passed from the integer command queue 240 to the integer registers 250. Integer / load-store circuits 260 may access integer instructions stored in integer registers 250 such that the instructions may be performed. Integer / load-store circuits 260 may also access data cache 265 when integer instructions stored in integer registers 250 refer to integer data stored in data cache 265.

According to embodiments of the present invention, thread management circuitry 205 provides a performance level to data cache 265. In particular, the performance level may control whether the data cache 265 will operate in the first performance level or the second performance level (ie, high power mode or low power mode). For example, the thread management circuitry 205 may provide a first performance level at which the data cache 265 operates in a high power mode or may provide a second performance level at which the data cache 265 operates in a low power mode. . In some embodiments in accordance with the present invention the operation of the data cache 265 is described as occurring at either the first performance level or the second performance level, but it is apparent that more performance levels may be used.

3 is a block diagram illustrating an embodiment of thread management circuits in accordance with the present invention.

According to FIG. 3, thread management circuitry 305 receives information from an operating system or from a thread generation circuit associated with the creation of a thread in an SMT processor. The thread management circuit 305 includes a thread allocation circuit 330, which may allocate processing circuits for use by threads created by the SMT processor.

The thread management circuit 305 also includes a performance level control circuit 340 that provides a performance level to processing circuits associated with the threads created by the SMT processor. The performance level control circuit 340 may provide a performance level to the processing circuits based on the number of threads currently operated by the SMT processor. In particular, as the number of threads operated by the SMT processor increases, the performance level control circuit may provide decreasing performance levels to the processing circuits associated with the threads operated by the SMT processor. The performance level control circuit 340 may determine the number of threads currently operated by the SMT processor by increasing and decreasing an internal count in response to the creation and completion of the threads operated by the SMT processor.

It is apparent that the performance level provided to the processing circuits according to the invention may have a default value such as the first performance level (or high power mode). Thus, as threads are added, the performance level provided to the processing circuits can be reduced to reduce the performance and thus reduce the power consumption of the processing circuits. The performance level may be provided to the processing circuits via a signal line capable of transmitting a signal having at least two states, namely, a first performance level and a second performance level. For example, after the SMT processor is initialized, the number of threads operated by the SMT processor may be "0". The default value of the performance level provided to the processing circuits here is the first performance level (high power mode). When the threads are added and eventually exceed the threshold, the performance level can be changed to the second performance level, for example by changing the state of the signal indicating which performance level is used.

4 is a block diagram illustrating an embodiment of performance level control circuits according to the present invention.

According to FIG. 4, the counter circuit 405 may receive information from an oerating system or the thread generation circuit described with reference to FIG. 3 to determine the number of threads currently operating by the SMT processor. For example, if the counter circuit 405 indicates that four threads have already been started by the SMT processor when information regarding the creation of a new thread is received, then the counter circuit 405 may currently have five threads by the SMT processor. Can be increased to reflect that they are operated.

The counter circuit 405 may provide the comparison circuit 410 with the number of threads currently operating by the SMT processor. A threshold is provided to the comparison circuit 410 with the number of threads currently operating by the SMT processor. The threshold may be a programmable value representing the number of threads for which the performance level will change beyond that. Therefore, when the number of threads currently operated by the SMT processor is less than or equal to the threshold value, the performance mode provided to the processing circuits may be maintained at the first performance level such as the high power mode. However, when the number of threads currently operated by the SMT processor exceeds the threshold, the performance level may be reduced to reduce the power consumed by the SMT processor.

5 is a flowchart illustrating the operation of an embodiment of a performance level adjusting circuit according to the present invention.

According to FIG. 5, the number of threads currently operating by the SMT processor when the SMT processor is initialized is “0” (block 500). Once threads are created and completed in the SMT processor, the number N of threads currently operating in the SMT processor is increased or decreased (block 505). For example, if four threads are operated by an SMT processor, the value of N is four. When a new thread is created, the value of N is increased to 5, while if one of the threads is then completed, the value of N is reduced back to 4.

The number of threads currently operating in the SMT processor is compared with a threshold (block 510). If the number of threads currently operated by the SMT processor is less than or equal to the threshold, the performance level control circuitry provides a first performance level to the processing circuits assigned to the threads (block 515). For example, if the processing circuit allocated to a thread is the cache memory described with reference to FIG. 2, the cache memory may operate (in high power mode) such that the tag memory and the data memory are accessed simultaneously. On the other hand, if the number of threads currently operated by the SMT processor is greater than the threshold (block 510), then the performance level control circuitry provides a second performance level to the processing circuits associated with the threads (block 520). For example, in the embodiments described above with reference to FIG. 2, at the second performance level, the cache memory may operate so that the data memory is accessed only in response to a hit in the tag memory (in the low power mode).

6 is a block diagram illustrating an embodiment of a cache memory according to the present invention shown in FIG. 2.

According to FIG. 6, the tag memory 610 is configured to store addresses of data stored in the data memory 620. Tag memory 610 is accessed using an address associated with the data acted upon by the SMT processor. The contents of the tag memory 610 are compared with the address by the tag comparison circuit 630 to determine whether data required by the SMT processor is stored in the data memory 620. When the tag comparison circuit 630 determines that necessary data is stored in the data memory 620, a tag hit occurs. Otherwise, a tag miss occurs. When a tag hit occurs, the output enable circuit 650 enables the data to be output from the data memory 620.

According to embodiments of the present invention, the performance level provided by the performance level control circuit is used to control how the tag memory 610 and the data memory 620 operate. In particular, when the first performance level is provided to the cache memory, the data memory enable circuit 640 enables the data memory 620 to be accessed simultaneously with the tag memory 610 regardless of whether a tag hit occurs. On the other hand, if the second performance level is provided to the cache memory, the data memory enable circuit 640 does not allow the data memory 620 to be accessed unless a tag hit occurs.

Therefore, in embodiments according to the present invention, the tag memory 610 and the data memory 620 can be accessed simultaneously to provide improved performance in the high power mode. In the low power mode, on the other hand, the data memory 620 is accessed only when the tag memory 610 indicates that a tag hit has occurred, and as a result, the power consumed by the cache memory can be reduced.

7 is a block diagram illustrating an embodiment of the present invention used for instruction cache.

According to FIG. 7, the thread management circuit 700 allocates an instruction cache 722 to a new thread. The performance level control circuit included in the thread management circuit 300 may provide the performance level to the instruction cache 722 to control how the instruction cache 722 operates.

In particular, the instruction cache 722 can operate in a high power mode in response to the first performance level and can be configured to operate in a low power mode in response to the second performance level. For example, as described above with reference to FIG. 5, first and second performance levels may be provided to the instruction cache 722 based on the number of threads currently operating by the SMT processor. In addition, the instruction cache 722 may operate at different performance levels in a manner similar to that described above with reference to FIG. 6. In FIG. 6, the data memory 620 is accessed only in response to tag hits in the low power mode. For example, different levels of performance may be provided to the instruction cache to allow direct addressing when it is determined that successive memory accesses are in the same cache line. This type of limitation can be applied using a direct-addressed cache that does not require reading of tag RAM and tag comparison. Moreover, direct addressed caching may also not require translation from a virtual address to a physical address.

8 is a block diagram illustrating an embodiment of separate processing circuits having different performance levels in accordance with the present invention.

According to FIG. 8, the first floating point circuit 805 may be configured to operate at a first performance level and the second floating point circuit 815 may be configured to operate at a second performance level lower than the first performance level. In other words, the first floating point circuit 805 can be used in the high power mode and the second floating point circuit 815 can be used in the low power mode.

The first integer / load-store circuit 810 is configured to operate at a first performance level and the second integer / load-store circuit 820 is configured to operate at a second performance level. Thread management circuitry 800 is configured to provide two separate levels of performance. In particular, the first performance level is provided to the first floating point circuit 805 and the first integer / load-store circuit 810. The second performance level provided by the thread management circuit 800 is provided to the second floating point circuit 815 and the second integer / load-store circuit 820. Thus, the first floating point circuit 805 and the first integer / load-store circuit 810 can be allocated to threads operating at the first performance level, while the second floating point circuit 815 And the second integer / load-store circuit 820 may be allocated to threads operating at the second performance level. It is apparent that the first and second performance levels may be provided independently or simultaneously by the thread management circuitry 800. It is also apparent that two or more separate floating point circuits and integer / load-store circuits may be provided as two or more performance levels may be provided.

According to embodiments of the present invention, the first performance level provided to the first floating point circuit 805 and the first integer / load-store circuit 810 is determined by the number of threads operating in the SMT processor. May be provided when less than or equal to. The second performance level may be provided to the second floating point circuit 815 and the second integer / load-store circuit 820 when the number of threads simultaneously operated by the SMT processor exceeds the first threshold. Therefore, when the number of threads operated by the SMT processor exceeds the threshold, all the threads, including previously existing threads and newly created threads, have a second coating to reduce the power consumed by the SMT processor. Point circuit 815 and second integer / load-store circuit 820 may be used.

Floating point circuits and integer / load-store circuits in accordance with the present invention may operate at different clock speeds and / or use other circuit types to provide different performance levels. For example, in some embodiments according to the present invention, the floating point circuit associated with the operation of a thread in an SMT processor may be a high power mode or a low clock rate at a high clock speed based on the number of threads currently operating by the SMT processor. It can operate in one of the low power modes.

9 is a block diagram illustrating an embodiment of an SMT processor including a plurality of processing circuits responsive to separate performance levels provided by thread management circuitry 900. In particular, the thread management circuitry 900 sets three separate performance levels into the instruction cache 930, the data cache 965, the first and second floating point circuits 905 and 915, and the first and second integers /. To the load-store circuits 910 and 920. It is apparent that the performance level provided to the first and second floating point circuits 905, 915 and the first and second integer / load-store circuits 910, 920 may operate as described above with reference to FIG. 8. Do. In addition, the instruction cache 930 and data cache 965 may operate as described above with reference to FIGS. 2 and 7, respectively.

Thus, separate performance levels can be provided to other processing circuits so that the processing circuits can operate at different performance levels. This allows very good control over the tradeoff between performance and power consumption. For example, the instruction cache operates at the first performance level while the data cache 265 and the first and second floating point circuits 905 and 915, and the first and second integer / load-store circuits 910 and 920. May operate at a second performance level. Also other combinations of performance levels may be used.

FIG. 10 is a block diagram illustrating an operation of an embodiment of a performance level control circuit included in the thread management circuit 900 of FIG. 9. In particular, the performance level control circuit includes a counter 1000 that is incremented and decremented in response to threads created and completed in the SMT processor. Each of the first to third registers 1015, 1020, and 1025 may store a threshold value of the number of threads currently operating in the SMT processor. Three comparison circuits 1030, 1035, 1040 are connected to each of the registers 1015, 1020, 1025. In particular, the first register 1015, which stores the first threshold value, is connected to the first non-conduit 1030. The second register 1020, which stores the second threshold value, is connected to the second non-converted path 1035. The third register 1025, which stores the third threshold value, is connected to the third non-conduit 1040.

Each of the comparison circuits 1030, 1035, 1040 compares the number of threads currently operated by the SMT processor with a threshold stored in each register. If the first non-intersection 1030 determines that the current number of threads operated by the SMT processor is greater than the first threshold value stored in the first register 1015, the first non-intersection 1130 is shown in FIG. 9. A performance level 1405 is generated that is coupled to the data cache 965. Therefore, when the number of threads operated by the SMT processor exceeds the threshold stored in the first register 1015, the performance level of the data cache 965 is changed from the first performance level to the second performance level (i.e., from the high power mode). Into low power mode).

If the second non-intersection 1035 determines that the number of threads currently operated by the SMT processor is greater than the threshold stored in the second register 1020, the second non-intersection 1035 is connected to the instruction cache 930. Generate level 1050. Thus, the performance level of the instruction cache 930 is changed from the first performance level to the second performance level (ie, from the high power mode to the low power mode).

If the third non-intersection 1040 determines that the number of threads currently operated by the SMT processor exceeds the threshold stored in the third register 1025, the third non-intersection 1040 determines the first and second floating points. Generates a performance level 1055 that is coupled to the circuits 905, 915 and the first and second integer / load-store circuits 910, 920. Thus, the performance level of these processing circuits is changed from the first performance level to the second performance level (ie from the high power mode to the low power mode). The performance level 1055 connected to the first and second floating point circuits 905, 915 and the first and second integer / load-store circuits 910, 920 operates as described above with reference to FIG. 8. It is self-evident.

FIG. 11 is a flowchart illustrating a method embodiment of a performance level control circuit shown in FIG. 10.

According to FIG. 11, the number of threads currently operating in the SMT processor is "0" when the SMT processor is initialized (block 1100). When threads are created and completed by the SMT processor, the number N of threads currently operating by the SMT processor is increased and decreased (block 1105).

If the number of threads currently being executed by the SMT processor is less than or equal to the first threshold (block 1110), all processing circuits continue to operate at the first (or high) performance level (block 1115). On the other hand, if the number of threads currently being executed by the SMT processor exceeds the first threshold (block 1110), the processing circuits connected to the performance level 1045 begin to operate at the second performance level (i.e., low power mode) ( Block 1120).

If the number of threads currently being executed by the SMT processor is less than or equal to the second threshold (block 1125), processing circuits connected to performance level 1050 (and performance level 1055) begin operating at the first performance level. (Or keep running). On the other hand, processing circuits connected to performance level 1045 (as described above) continue to operate at the second performance level.

If the number of threads currently being executed by the SMT processor exceeds the second threshold (block 1125), the processing circuits connected to performance level 1050, along with the processing circuits connected to performance level 1045, perform a second performance level ( And start operating (or continue operating) at block 1135. On the other hand, processing circuits connected to performance level 1055 continue to operate at the first performance level.

If the number of threads currently being executed by the SMT processor is less than or equal to the third threshold (block 1140), the processing circuits connected to performance level 1055 continue to operate at the first performance level, while performance level 1045 and performance Processing circuits coupled to level 1050 continue to operate at the second performance level (block 1145). If the number of threads currently being executed by the SMT processor exceeds a third threshold (block 1140), processing circuits coupled to performance level 1055 begin to operate at a second performance level (i.e., low power mode) (or continue operation). (Block 1150).

As described above, embodiments in accordance with the present invention may provide processing circuits related to the operation of a thread in an SMT processor. These processing circuits are configured to operate at different performance levels based on the number of threads currently operating by the SMT processor. For example, in some embodiments of the invention, processing circuits associated with the operation of a thread in an SMT processor, such as a floating point circuit or a data cache, may be in high power mode or low power mode based on the number of threads currently operating by the SMT processor. It can work on one.

In addition, increasing the number of threads operated by an SMT processor may reduce performance levels of the processing circuits, thereby providing structural benefits of the SMT processor, thereby reducing the amount of power consumed by the processing circuits associated with the thread. For example, in some embodiments in accordance with the present invention, processing circuits may operate at different clock speeds and / or use other circuit types to provide different performance levels. For example, in some embodiments according to the present invention, the processing circuits associated with the operation of a thread in an SMT processor, such as a floating point circuit or a data cache, may be high power at a high clock speed based on the number of threads currently operating by the SMT processor. Mode or low power mode at low clock speeds.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the simultaneous multi-threading (SMT) processor and the method for operating the same, the processing circuits related to the thread operation in the SMT processor are different performance levels, that is, high clock based on the number of threads currently operating. It can optionally operate in either a high power mode at speed or a low power mode at low clock speed. As a result, power consumption can be reduced and performance can be increased.

Claims (41)

In Simultaneous Multi-Threading (SMT) Processor, And at least one processing circuit associated with the operation of the thread in the SMT processor and configured to operate at different performance levels based on the number of threads currently operating by the SMT processor. The system of claim 1, wherein the at least one processing circuitry is configured to operate at a first performance level when the number of threads currently operated by the SMT processor is less than or equal to a threshold value. The at least one processing circuit is configured to operate at a second performance level when the number of threads currently operated by the SMT processor is greater than the threshold. The method of claim 1, And a performance level control circuit configured to provide a performance level for the at least one processing circuit based on the number of threads currently operated by the SMT processor. The performance level control circuit of claim 3, wherein the performance level control circuit increases the performance level provided to the at least one processing circuit to a first performance level when the number of threads currently operated by the SMT processor is less than or equal to a threshold value. The performance level control circuit reduces the performance level provided to the at least one processing circuit to a second performance level lower than the first performance level when the number of threads currently operated by the SMT processor exceeds the threshold. Simultaneous multithreading processor, characterized in that. The method of claim 4, wherein the threshold value comprises a first threshold value, When the number of threads currently operated by the SMT processor exceeds the second threshold value greater than the first threshold value, the performance level control circuit may increase the performance level provided to the at least one processing circuit than the second performance level. And further reduce to a lower third performance level. 2. The system of claim 1, wherein the at least one processing circuit comprises a cache memory circuit comprising a tag memory and a data memory, The data memory is configured to provide cached data simultaneously with access to the tag memory when the cache memory circuit operates at a first performance level, The data memory is configured to provide cached data in response to a hit in the tag memory when the cache memory circuit operates at a second performance level lower than the first performance level. Processor. The method of claim 6, wherein the cache memory, At least one data cache memory configured to store data operated by instructions; And And an instruction cache memory configured to store instructions that operate on associated data. 7. The simultaneous multithreading processor of Claim 6, wherein the data memory is configured to not provide cached data in response to a miss in the tag memory when operating at the second performance level. 2. The simultaneous multithreading processor of claim 1, wherein the at least one processing circuit comprises a floating point unit. 10. The method of claim 9, wherein the floating point unit comprises a first floating point unit configured to operate at a first performance level when the number of threads operated by the SMT processor is less than or equal to a threshold, The SMT processor further includes a second floating point unit configured to operate at a second performance level lower than the first performance level when the number of threads operated by the SMT processor is greater than the threshold value. Simultaneous multithreading processor. 2. The simultaneous multithreading processor of Claim 1, wherein the at least one processing circuit comprises an integer register. 3. The performance level control circuit of claim 2, wherein the performance level control circuitry is configured to increase or decrease the number of threads currently operating by the SMT processor in response to threads that are each created and completed in the SMT processor. Simultaneous multithreading processor. 2. The system of claim 1, wherein the at least one processing circuit comprises a first processing circuit configured to operate at a first performance level in response to the number of threads currently operating in the SMT processor that is reduced below a threshold; The SMT processor further comprises a second processing circuit configured to operate at a second performance level lower than the first performance level in response to the number of threads currently operating in the SMT processor that is increased greater than the threshold. Features simultaneous multithreading processor. The method of claim 1, wherein the performance level control circuit is responsive to creation of a new thread to increase the number of threads currently operated by the SMT processor from a value less than or equal to a threshold to a value greater than the threshold. And reduce the level of performance provided to the at least one processing circuit. The performance level control circuit of claim 2, wherein the performance level control circuit is configured to lower the performance level of the at least one processing circuit when the number of threads currently operated by the SMT processor exceeds each of a plurality of rising thresholds. A simultaneous multithreading processor, configured to reduce one of the performance levels. 3. The system of claim 2, wherein the performance level control circuit is configured by the SMT processor to maintain a first performance level for a first processing circuit and to increase from a value less than or equal to a threshold to a value greater than the threshold. And provide a second processing circuit with a second performance level lower than the first performance level in response to the number of currently operating threads. In the SMT processor, And a performance level control circuit configured to provide a performance level to processing circuits in the SMT processor based on the number of threads currently operated by the SMT processor. 18. The system of claim 17, wherein the performance level control circuitry is configured to increase the number of threads currently operated by the SMT processor in response to the creation of a new thread to provide a new number of running threads. And provide a level of performance to the processing circuit based on the new number of threads operated by a processor. 18. The system of claim 17, wherein the performance level control circuitry is configured to increase the performance level provided to the processing circuits to a first performance level when the number of threads currently operated by the SMT processor is less than or equal to a threshold. Become, The performance level control circuit is configured to reduce the performance level provided to the processing circuits to a second performance level lower than the first performance level when the number of threads currently operated by the SMT processor exceeds the threshold. Simultaneous multithreading processor, characterized in that the configuration. 20. The SMT processor of claim 19, wherein the performance level control circuit is configured to maintain the first performance level for a first processing circuit and to increase from a value less than or equal to a threshold to a value greater than the threshold. And provide the second processing circuit with a second performance level lower than the first performance level in response to the number of threads currently operating. 18. The multithreaded processor of claim 17, wherein the processing circuit comprises at least one of a floating point unit and a data cache memory. 18. The system of claim 17, wherein the processing circuits are configured to operate at a first performance level when the number of threads currently operated by the SMT processor is less than or equal to a threshold, And said processing circuits are configured to operate at a second performance level when the number of threads currently operated by said SMT processor is greater than said threshold. In the SMT processor, Thread management circuitry for allocating processing circuits associated with the SMT processor to threads that are operated in the SMT processor when threads are created; And And a performance level control circuit for providing one of a plurality of performance levels to the processing circuits based on the number of threads currently operating by the SMT processor compared to at least one threshold. 24. The SMT processor of claim 23, wherein the at least one threshold is a threshold number of threads operated by the SMT processor. 24. The system of claim 23, wherein the performance level control circuit increases the performance level provided to the processing circuits to a first performance level when the number of threads currently operated by the SMT processor is less than or equal to the at least one threshold. Let's The performance level control circuit sets the performance level provided to the processing circuits to a second performance level lower than the first performance level when the number of threads currently operated by the SMT processor exceeds the at least one threshold. Simultaneous multithreading processor, characterized in that for reducing. 24. The system of claim 23, wherein the performance level control circuit is to increase the number of threads currently operated by the SMT processor from a value less than or equal to the at least one threshold to a value greater than the at least one threshold. And reduce the performance level provided to the processing circuits in response to the creation of a new thread. 23. The system of claim 22, wherein the performance level control circuit lowers the performance level provided to the processing circuits when the number of threads currently operated by the SMT processor exceeds each of a plurality of rising thresholds. And reduce to one of the performance levels. 24. The system of claim 23, wherein the performance level control circuit maintains a first performance level for the first processing circuit and from a value less than or equal to the at least one threshold to a value greater than the at least one threshold. And provide a second processing circuit with a second performance level lower than the first performance level in response to the number of threads currently operated by the SMT processor. In the cache memory associated with the SMT processor, Tag memory; And And a data memory simultaneously accessed or sequentially accessed with the tag memory based on the number of threads currently operated by the SMT processor. 30. The cache memory of claim 29 wherein the tag memory and the data memory are simultaneously accessed in response to the number of threads currently operated by the SMT processor that is less than or equal to a threshold. 30. The cache memory of claim 29 wherein the data memory is accessed in response to a hit in the tag memory in response to the number of threads currently operated by the SMT processor that is greater than a threshold. In the method for operating the SMT processor, Providing a performance level to at least one processing circuit based on the number of threads currently operated by the SMT processor. The method of claim 32, wherein the providing step, And comparing the threshold number and the number of threads currently being operated by the SMT processor to provide the performance level to the at least one processing circuit. The method of claim 32, wherein the comparing step, Increasing the number of threads currently operated by the SMT processor in response to a new thread started at the SMT processor; And Reducing the number of threads currently operating by the SMT processor in response to the threads terminating in the SMT processor. The method of claim 34, wherein the providing step, Providing a first performance level to the at least one processing circuit if the number of threads currently operated by the SMT processor is less than or equal to the threshold; And Providing the at least one processing circuit with a second performance level lower than the first performance level if the number of threads currently operated by the SMT processor exceeds the threshold. 36. The method of claim 35 wherein Further reducing performance levels for processing circuits associated with new threads that increase the number of threads currently operated by the SMT processor to exceed increasing additional thresholds. A computer program product for operating an SMT processor, comprising: A computer readable medium having computer readable program code implemented therein, And the computer program product includes computer readable program code configured to provide a level of performance to at least one processing circuit in the SMT processor based on the number of threads currently operated by the SMT processor. product. The method of claim 37, And computer readable program code configured to compare a threshold and the number of threads currently operated by the SMT processor to provide the performance level to the at least one processing circuit. The method of claim 37, Computer readable program code for increasing the number of threads currently operated by the SMT processor in response to a new thread started at the SMT processor; And And computer readable program code for reducing the number of threads currently operated by the SMT processor in response to the threads terminating in the SMT processor. 38. The computer program product of claim 37, wherein the computer readable program code includes: Computer readable program code configured to provide a first performance level to the at least one processing circuit if the number of threads currently operated by the SMT processor is less than or equal to the threshold; And Computer readable program code configured to provide the at least one processing circuit with a second performance level lower than the first performance level if the number of threads currently operated by the SMT processor exceeds the threshold. Computer program products made. The method of claim 38, Further comprising computer readable program code configured to further reduce performance levels for processing circuits associated with new threads that increase the number of threads currently operated by the SMT processor to exceed increasing additional thresholds. Computer program product, characterized in that.