TW200303588A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
TW200303588A
TW200303588A TW091135033A TW91135033A TW200303588A TW 200303588 A TW200303588 A TW 200303588A TW 091135033 A TW091135033 A TW 091135033A TW 91135033 A TW91135033 A TW 91135033A TW 200303588 A TW200303588 A TW 200303588A
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Taiwan
Prior art keywords
gold
substrate
wafer
bonding
wiring
Prior art date
Application number
TW091135033A
Other languages
Chinese (zh)
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TWI254398B (en
Inventor
Masayoshi Shinoda
Kazutoshi Itou
Toshiaki Morita
Asao Nishimura
Ryoichi Kajiwara
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Hitachi Ltd
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Publication of TW200303588A publication Critical patent/TW200303588A/en
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Publication of TWI254398B publication Critical patent/TWI254398B/en

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L21/607—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of mechanical vibrations, e.g. ultrasonic vibrations
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Abstract

The present invention provides a semiconductor device, in which an LSI chip having a separation smaller than 100μ m and the number of pin electrode larger than 50 is directly mounted on an organic substrate, the mounting structure, which has excellent quality in anti-soldering and flattening thermal treatment of semiconductor device, temperature cycling reliability, and reliability at high temperature and high humidity, and the manufacturing method. In the invention, the metal of gold/gold directly bonded to the electrode gold bump of the flip chip and the gold film structure of the surface for the substrate connection terminal is formed, and the bonding structure with an extension larger than 2 μ m for the bonding part of the gold bump is also formed. In the method of forming the bonding structure, ultrasonic bonding treatment is conducted in ten minutes after both faces for bonding are cleaned by sputtering process. The structure stated above can be realized by selecting the bonding conditions as shown below: substrate side: room temperature; chip side: room temperature ~150 DEG C; bonding load: 1/2Sx 100Mpa~Sx 180Mpa (S: bump/contact area between chips); load mode: increase during the bonding; and ultrasonic time: 50~500 ms.

Description

200303588 ⑴ 玖、發明說明 (發明說明應敘明：發明所屬之翻_、先前她、内容、實施方式及圖式簡單說明） 【發明之技術領域】 本發明係有關經由貴重金屬凸塊面朝下地將矽晶片安裝 於配線基板上之半導體裝置及安装方法，尤其是有關可減 少安裝時之晶片損傷，可大幅改善連接部之耐熱性、溫度 周期壽命、高溫高濕及高溫保持可靠性之晶片/基板間之 接合構造、接合端子之金屬喷鍍構造及金屬接合方法。 【先前技藝】 先前之使用金凸塊之半導體晶片之倒裝片安裝法包含： 1) 金/金之直接接合， 2) 以絕緣樹脂之晶片接著進行金/金接觸連接， 3) 以異方導電性樹脂之晶片接著進行金/銀粒子/金接觸 連接， 4)金/錫之熔融接合 2。2)，3)項之樹脂接著的接觸連接方式，存在經暴露於 间濕度環境下後之各種可靠性測試，惡化顯著缺乏可靠性 之問題，4)項之使用低熔點金屬之熔融接合方式，則存在 接合界面形成脆弱金屬間化合物，接合後之冷卻過程及溫 度周期賴B夺容易產生裂痕之強度可靠性低的問題。目前 可罪性隶佳之安裝法係金/金直接接合方式。 金/金接合方式之先前技術，於特開平1〇_1〇7〇78號及電 子通信學會技術報告書（1995年7月）中作為領先技術而揭 不有：於配線基板之金凸塊上，面朝下地施加超音波進行 金屬接合而搭載形成金凸塊之表面波裝置的方法。此等領 (2) 200303588 發明說明績頁 先技術，為使金凸塊/金凸塊間確實地金屬接合，金凸塊 之膜厚在0.5 μπι以上，適切接合條件為··接合負載為乃gf/ bump〜3 00 gf/bump，接合溫度為15〇〜25(rc，超音波施 加時間為500〜800 ms。在該條件下之金凸塊接合部之剪切 強度可獲得40 gf / bump〜1 〇〇 gf / bump。表面波裝置之電介 質基板因係複合氧化物系之電介質材料，因此強度極強， 於接合負載300 gf/bump内無接合損傷。若下降至接合條 件下限值之接合負載75gf/bump，接合溫度15〇。〇，=音 波，加時間300 ms以下時’料致接合強度降低且接合不 L疋產生未接合品及未接合凸塊而良率降低及連接可靠 性降低’屬於製品組裝困難的條件。此外，配線基板僅述 及陶究基板。 另外，在包含有機材料之配線基板上，面朝下地藉由金 :接合搭載形成金凸塊之半導體晶片的安裝方法，作為領 先^而揭示於特開平10_275826號中。該領先技術係將 配線基板上之覆蓋硬質金屬：鎳(3〜5μιη)/金(〇〇3〜〇.〇5㈣ 3合焊墊部’於接合前在真空中照射離子或原子予以潔 :::曰;片於形成凸塊之後保管於非氧化性環境中，使用 與晶片予以^ 氣巾將此等配線基板 及靶昼，保持特定時間，於硬質金屬與金 A 3 >成合金層來進行全屬 ...^ Tv 件為：其接合溫度在晶片^屬接5。此時適切之接合條 Ί 曰片側為1 5ο〜300 c，在基板側為60 〜120C，接合負載為 ^ , π …g / bumP 〜30 gf / bump，接合時間 為1〇〜150秒。以昭 ^ 、、、射離子或原子予以潔淨化後之焊墊表 (3) (3)200303588 發明說明續頁 面僅殘留少許金的程产 屬鎳與金凸塊間形成：全ΐ上述條件下藉由接合於硬質金 強固地接合，直至❹對接合部進行破壞測試時可 ^ ^ ^ - nr ^ 、、曰的一部分缺損，附著於凸塊電極頂 Ρ t a… 卞超日波時雖可促使接合溫度低溫化 緣接合時間’但是並未詳細揭示。 【發明所欲解決之問題】 本舍明人於開發微雷腦 >曰& τ ^ ^圖像處理裝置及搭載記憶體等 之农新L SI晶片之快诸•令 ,_ 、連回性此之多晶模組時，檢討評估 引之金/孟接合方式。模組基板為求配合LSI晶片之電極 間距，須使最小配線間距達到90〜40μιη間距。一般之印 刷配線基板係以貼附銅羯經姓刻予以圖案化的方法製造， 不過微細間距化方面仍有限制，僅達約1〇〇陶間距。可對 應於其以上之微細間距之配線基板之於核心基板上形成薄 絕緣層後，以焊接法形成圖案之逐次堆疊方式的組合基板 在，產，、可靠性及成本上最佳。但是該組合基板存在以 逐-人堆豐形成之有機絕緣膜的玻璃轉移溫度較低^ H机） ，彈性率⑯’因鍍處理限定於無電解鍍，以致在成本上形 成：鍍膜困難，且因形狀.尺寸受限而微細配線的剛性低 $致以先$之金/金金屬接合之倒裝片安裝困難的問題 。具體檢討例顯示於下。 藉由上述之超音波接合技術，以金/金接合在上述組合 基板上倒裝片安裝最新的LSI晶片。結果判明在接合負^ Mgf/bUmp，接合溫度150〜250t，接合時間3〇〇ms的條 件下’於形成金凸塊之晶片的紹電極下絕緣層上產生微小 -10 - (4) (4)200303588 發明說明績頁 裂痕，晶片損傷係本安裝法的重大問題。此外判明於組合 基板被加熱時，因施加於微細配線部之接合負載與超音^ 振動致使微細配線嚴重變形，表面鍍成之鎳層上產生^痕 及產生斷線。並判明為求避免此等問題，而降低接合負載 時則無法確貫接合’ 50接腳以上之LSI晶片不易避免因接 合不良導致初期接通不良而達到1〇〇%接合率。此外判明 ，於接合溫度15(TC中，因有機基板之熱膨脹率與 LSI晶片之熱膨脹率3ppm之差異，在1〇mm尺寸的晶片上 最大產生約20 μΐη的初期位置偏差，在超音波接合時之金 凸塊變形過程中，更助長其位置偏差，容易產生與鄰接端 子的短路不良。並判明在接合間距大的圖㈣，雖不致產 生位置偏差及短路不良，但是在接合後的冷卻過程中，於 晶片^基板間產生大的熱畸變，晶片上之鋁膜厚度變薄而 底層薄弱之LSI上產生晶片損傷（底層絕緣層的裂痕）。 另外，將基板I面予以潔淨化並予以熱壓著之先前的上 述金/金接合法，在鎳（5μΓη)/金（〇〇5μιη)規格之組合基板 上倒裝片安裝最新的LSI晶片時，在晶片溫度⑽口基板 溫度6(TC ’接合時間1〇〜15〇3，接合負載2〇〜3〇gf/ — 的條件下’於空氣中熱壓著接合時，無法達成確實的金屬 接合。接合狀態之評估係以於氫氧化鈉水溶液中腐钮銘電 "除去曰曰片仏查金凸塊對基板側之轉印率的方法進行 接σ拙樣’判斷有無金屬接合。檢討可獲得金凸塊轉印率 100%之接合條件的結果’在接合溫度為晶片溫度·。c/基 板/皿度120 c ’接合負載20〜30 gf/bump，接合時間15〇3以 (5)200303588 發明說明績頁200303588 发明 发明, description of the invention (the description of the invention should state: the invention belongs to the _, the previous description, the content, the embodiment and the schematic description of the invention) [Technical Field of the Invention] The present invention is related to the precious metal surface facing down A semiconductor device and a mounting method for mounting a silicon wafer on a wiring substrate, particularly a wafer / chip that can reduce chip damage during mounting, and can greatly improve the heat resistance, temperature cycle life, high temperature, high humidity, and high temperature retention reliability of a connecting part. A bonding structure between substrates, a metallized structure for bonding terminals, and a metal bonding method. [Previous technology] The previous flip chip mounting method of semiconductor wafers using gold bumps includes: 1) direct bonding of gold / gold, 2) wafers made of insulating resin followed by gold / gold contact connection, 3) alien The conductive resin wafer is then subjected to gold / silver particles / gold contact connection, 4) gold / tin fusion bonding 2. 2), 3) The resin contact connection method of item exists after being exposed to the humidity environment Various reliability tests worsen the problem of significant lack of reliability. In the fusion bonding method using low melting point metal in item 4), there are fragile intermetallic compounds at the bonding interface. The cooling process and temperature cycle after bonding are subject to cracks. The problem of low strength and reliability. The current installation method of guilt is good gold / gold direct bonding. The previous technology of the gold / gold bonding method was disclosed as a leading technology in JP-A No. 10_1007007 and the Technical Report of the Institute of Electronics and Communications (July 1995): gold bumps on wiring substrates A method of mounting a surface wave device that forms a gold bump by applying an ultrasonic wave face down to perform metal bonding. These collars (2) 200303588 The invention describes the first technology, in order to ensure the metal bonding between gold bumps / gold bumps, the thickness of the gold bumps is 0.5 μm or more, and the appropriate bonding conditions are: gf / bump ~ 3 00 gf / bump, joint temperature is 15 ～ 25 (rc, ultrasonic application time is 500 ~ 800 ms. Under this condition, the shear strength of the gold bump joint can obtain 40 gf / bump ~ 100 gf / bump. The dielectric substrate of the surface wave device is a composite oxide-based dielectric material, so it is extremely strong, and there is no joint damage within the joint load of 300 gf / bump. If it falls below the lower limit of the joint conditions Bonding load 75gf / bump, bonding temperature 15.0, = sound wave, when the time is less than 300 ms, the bonding strength will decrease and the bonding will not occur. Unbonded products and unbonded bumps will be generated, yield will be reduced, and connection reliability will be reduced. “Reduction” is a difficult condition for assembling products. In addition, the wiring board only refers to ceramic substrates. In addition, on a wiring board containing organic materials, a semiconductor wafer mounting method of gold: bonding is mounted face-down with gold: bonding. , It is disclosed in Japanese Patent Application Laid-Open No. 10_275826 for leading ^. This leading technology is to cover the hard metal on the wiring substrate: nickel (3 ~ 5μιη) / gold (〇〇3〜〇.〇5㈣) 3 bonding pads' in the joint Before cleaning, irradiate ions or atoms in a vacuum ::: said; after the bumps are formed, they should be stored in a non-oxidizing environment, and the wafers should be used. The hard metal and gold A 3 > alloy layer to carry out all belong ... ^ Tv parts are: its joining temperature is on the wafer ^ belongs to 5. At this time, a suitable joining bar Ί said side is 1 5ο ~ 300 c, at The substrate side is 60 to 120C, the bonding load is ^, π… g / bumP ～ 30 gf / bump, and the bonding time is 10 to 150 seconds. The pad table is cleaned with ^, ,, or ion or atom. (3) (3) 200303588 Description of the invention Continuing on the page, only a small amount of gold is left between the nickel and the gold bumps: under the above conditions, it is firmly bonded by bonding to hard gold until the joint is subjected to a damage test.时 ^ ^ ^-nr ^, part of the defect is attached to the top of the bump electrode P t a ... 卞 Ultra-day wave time can promote the junction temperature to lower the temperature and reduce the junction time ', but it has not been disclosed in detail. [Problems to be Solved by the Invention] Ben Sheming was developing the micro-thunder brain > Said & τ ^ ^ image The processing equipment and the Nongshin L SI chip with memory and other fast-moving • order, _, repeatability of the polycrystalline module, review the evaluation of the gold / Meng joint method. The module substrate is to match the LSI chip The electrode pitch must be a minimum wiring pitch of 90 ~ 40μm. A general printed wiring board is manufactured by attaching copper cymbals and patterning them by the last name. However, there is still a limitation in fine pitch, only about 100 ceramic pitch. It is possible to form a thin-layer insulating layer on the core substrate corresponding to the fine-pitch wiring substrates above, and then use a soldering method to form a patterned stacking substrate in a sequential stacking method in terms of production, reliability, and cost. However, the combined substrate has a low glass transition temperature of the organic insulating film formed on a one-by-one basis. The elastic modulus ⑯ is limited to electroless plating due to the plating process, so that it is formed in cost: the coating is difficult, and Due to the limited shape and size, the rigidity of the fine wiring is low, which makes it difficult to install the flip chip with gold / gold metal bonding. Specific review examples are shown below. Through the above-mentioned ultrasonic bonding technology, the latest LSI chip is flip-chip mounted on the above-mentioned combined substrate by gold / gold bonding. As a result, it was found that under the conditions of bonding negative ^ Mgf / bUmp, bonding temperature 150 ~ 250t, and bonding time 3000ms, 'a small amount of -10-(4) (4 200303588 The invention explains that the page cracks and wafer damage are major problems of this mounting method. In addition, it was found that when the combined substrate was heated, the micro-wiring was severely deformed due to the bonding load and ultrasonic vibration applied to the micro-wiring portion, and ^ marks and wire breakage occurred on the nickel plating surface. It was also found that in order to avoid these problems, it is not possible to consistently bond LSI chips with 50 pins or more when the bonding load is reduced, and it is difficult to avoid 100% bonding rate due to poor initial connection due to poor bonding. In addition, it was found that at a bonding temperature of 15 ° C, a maximum initial position deviation of about 20 μΐη occurred on a 10 mm wafer due to a difference between the thermal expansion coefficient of the organic substrate and the thermal expansion coefficient of the LSI wafer of 3 ppm. During the deformation process of the gold bumps, the position deviation is further promoted, and short circuit defects with adjacent terminals are easy to occur. It is found that in the map with a large bonding distance, although position deviation and short circuit defects do not occur, during the cooling process after bonding, There is a large thermal distortion between the wafer and the substrate. The thickness of the aluminum film on the wafer becomes thinner and the wafer damage (fracture of the underlying insulating layer) occurs on the LSI with a weak bottom layer. In addition, the I side of the substrate is cleaned and hot-pressed. Based on the previous gold / gold bonding method, when the latest LSI wafer is flip-chip mounted on a combination substrate of nickel (5μΓη) / gold (005μιη) specification, the substrate temperature is 6 (TC 'bonding) at the wafer temperature. When the time is between 10 ~ 15〇3 and the joining load is 20 ~ 30gf / — when the heat-bonding in air is performed, no reliable metal joining can be achieved. The evaluation of the joining state is based on In the sodium hydroxide aqueous solution, the button is rotten, and the method of removing the gold bumps to check the transfer rate on the substrate side is used to determine whether there is metal bonding. Review and obtain the gold bump transfer rate. Result of 100% bonding conditions 'when bonding temperature is wafer temperature. C / substrate / plate degree 120 c' bonding load 20 ~ 30 gf / bump, bonding time 1503 with (5) 200303588 Invention Description Sheet

此外，藉自先前之金/金帛纟；去，於各種配線基板上倒 裝片安裝模擬LSI之TEG晶片，製作於基板/晶片間填充含 熱膨脹率約30Ppm之無機絕緣填料之樹脂的安裝抽樣，進 打-55 / 150°C之溫度周期測試作評估時，判明金凸塊對其 板側之轉印率為麵之條件的抽樣，其金凸塊的變形： 而晶片/基板間之間隙小，纟晶片之銘電極與金凸塊間產 生裂痕，於1000周期等級產生斷線。抑制金凸塊變形之條 件的抽樣，若金凸塊之轉印率未達100%，^吏為初期可 確認接通者’經數百周期的測試，判明金凸塊與金連接端 子之接合界面形成開口，於短時間即斷線。 上的條件f，確認轉印率ΠΚ)%。但是即使在上述任何條 件下，由於接合時間長達10〜150s’而判明組合基板之溫 度上昇，逐次堆疊之絕緣層的彈性率降低。藉由該現象瞭 解於底層上核心、基板具有銅圖案配線之區域的微細配線部 與無銅圖案配線區域之微細配線部的變形程度產生差異。 因此判明產生金凸塊的變形率不均―，變形率大之凸塊可 獲得確實的金屬接合，但是變科小的金凸塊㈣合不足 。此係以玻璃轉移溫度及彈性率高之材料所構成之先前印 刷配線板上未產生的問題。若提高接合溫度則提高整體接 合等級，即使變形率小的金凸塊亦可達成金屬接合，伸是 基於隨基板之熱膨脹導致凸塊/微細配線間之位置偏差增 加，及微細配線部嚴重變形隨之位置偏差增加等兩個因^ ，未達100 μηι之微細間距LSI的安裝困難。此外，生產性 方面亦存在因接合時間長而導致製造成本提高的問題。In addition, borrow from the previous gold / gold tin; go, flip-chip mounting TEG wafers of analog LSIs on various wiring substrates, and make sample installation of resins filled with inorganic insulation fillers with a thermal expansion coefficient of about 30Ppm between the substrates / wafers During the evaluation of the temperature cycle test at -55 / 150 ° C, it is determined that the gold bumps are sampled under the condition that the transfer rate of the plate side is the surface, and the deformation of the gold bumps: and the gap between the wafer / substrate Small, cracks occur between the electrode of the wafer and the gold bumps, and disconnection occurs at the 1000 cycle level. Sampling conditions for suppressing the deformation of the gold bumps. If the transfer rate of the gold bumps does not reach 100%, ^ is the person who can be confirmed at the initial stage. 'After hundreds of cycles of testing, it is determined that the gold bumps are connected to the gold connection terminals. The interface forms an opening, which is broken in a short time. On the condition f, the transfer rate (ΠK)% was confirmed. However, even under any of the above conditions, since the bonding time was as long as 10 to 150 s', it was found that the temperature of the combined substrate increased, and the elasticity of the insulating layers that were sequentially stacked decreased. By this phenomenon, it is understood that the degree of deformation of the fine wiring portion in the core on the bottom layer and the area where the substrate has copper pattern wiring is different from that of the fine wiring portion in the area without copper pattern wiring. Therefore, it is determined that the deformation rate of the gold bumps is not uniform. The bumps with large deformation rates can obtain a reliable metal joint, but the small gold bumps are not sufficiently combined. This is a problem that has not occurred on a previously printed wiring board made of a material with high glass transition temperature and high elasticity. If the bonding temperature is increased, the overall bonding level is improved. Even gold bumps with a small deformation rate can achieve metal bonding. The extension is based on the increase in positional deviation between the bumps / fine wirings caused by the thermal expansion of the substrate, and the severe deformation of the fine wiring parts. It is difficult to install a fine-pitch LSI with two factors, such as an increase in positional deviation, of less than 100 μm. In addition, there is a problem in that the manufacturing cost is increased due to the long bonding time.

12- 200303588 發明說明繽頁 ⑹ 本發明之目的在提供一種於具有最小配線間距1〇〇 以 下之微細配線層，具有低玻璃轉移溫度之表面絕緣層的有 機配線板上，將具有最小電極間距在100 μιη以下，5〇接腳 · 以上之電極焊墊之LSI晶片，不產生基板/晶片間之位置偏 · 差，且不產生晶片損傷，藉由金/金之金屬接合確實地倒 裝片連接全部接腳之半導體的製造方法。 本發明之其他目的在提供一種可以高可靠且低阻抗之特 性將多接腳•微細間距之LSI晶片搭載於具有微細配線層 之有機配線基板上，組裝良率高且生產性優異之安裝構造 _ 及安裝處理。 本發明之其他目的在提供一種於表面層上具有包含微 配線層與低玻璃_多溫度之有機、絕緣層之组合層之有機 線基板上，藉由倒裝片連接搭載具有5()接腳以上之電極: 墊之多接腳LSI晶片，且倒裝片連接部之耐熱性、電性 高溫高濕及溫度周期可靠性優異之半導體裝置。 【解決問題之手段】12- 200303588 Description of the invention ⑹ The purpose of the present invention is to provide an organic wiring board having a fine wiring layer with a minimum wiring pitch of 1000 or less and a surface insulating layer with a low glass transition temperature. LSI chips with electrode pads of 50 μm or less and 50-pin or more electrode pads do not cause positional deviations or differences between the substrates and wafers, and do not cause wafer damage. The gold / gold metal bonding is used to reliably flip chip connections. Manufacturing method of all pin semiconductors. Another object of the present invention is to provide a mounting structure capable of mounting a multi-pin / fine-pitch LSI chip on an organic wiring substrate having a fine wiring layer with high reliability and low impedance. And installation processing. Another object of the present invention is to provide an organic wire substrate having a combination layer including a micro-wiring layer and a low-temperature multi-temperature organic and insulating layer on a surface layer, and a 5 () pin is mounted on the surface layer by flip chip connection. The above electrodes: semiconductor devices with pads of multiple pin LSI chips and excellent heat resistance, electrical high temperature, high humidity, and temperature cycle reliability of the flip-chip connection. [Means of Solving Problems]

為求達成上述第一目的，本發明於LSI晶片之電極上f 成具有基座部之直徑或矩形之—邊大小係電極尺寸之60 麵或是最小電極間距之5G〜9G%A小，高度為Η〜 。 於^上°卩，頂端部進一步縮小至基座部之直徑< 、，下的大小，自底面至頂端之整個高度在3 0 μχη以上戈 配S'查f外’於具有微細配線層之有機配線基板側之# !的連接端子最表面上形成金鍍膜。將兩者倒裝片接名 之引於大乳屋或0」〜數Pa之減壓的氨氣環境下，藉由德 -13· 200303588 ⑺ 發明說明續頁 厗為5 _以上之氬離子濺射法物理性姓刻金凸塊表面，藉 由5賊以上或金膜厚之約1/1〇〜1/2之氬離子減射法物理性 ㈣連接端子側之錢表面。兩者均在㈣下物理性姓刻 日守以亂軋或除去水分之乾燥空氣昇廢，分別放入空氣中 。將有機配線基板搭載於接合裝置的載台i，使⑶晶片 ^超曰波接合頭之接合卫具面上反轉吸附，進行兩者的對 ’使接合頭下降重4 °此時载台或接合卫具保持在特定 溫度’並使有機配線基板及LSI晶片之溫度在對準步驟中 到達特定溫度。於重疊後，自晶片底面施加I力盘超音波 振動’進行金凸塊與金鑛膜之金屬接合。此時之接合條件 係自施加於每1 bump之負載p為 士 ··· （ 1 ) (此時S1 ··金凸塊/電極間之接觸面積） :耗圍内選擇。此因南於該條件的負荷時，將於金凸塊/ 極之接觸部上產生隨伴金凸塊變形之晶片損傷，低 、、日接合面積明顯小於凸塊尺寸，在晶片/基板間產 生熱畸、遣時，凸塊本身不變形’畸變集中於接合界面而斷 線的概率增加。 ”接合條件係接合環境濕度在60%以下，接合溫度設 ;格載基板之載台側為室溫〜6(rc ’在接合頭側溫 〜Hot之範圍，接合時間在5〇〜5〇〇ms的範圍，於晶片: 振幅為50 kHz時，振動振幅為〇·3〜2〇_，因此工：振幅 於接合工具/晶片間之振動傳送效率為1/2時在〇.6〜4.〇 μιη -14- 200303588 ⑻ 發明說明績頁 的範圍，並配合工作選擇適切條件。此外負載的施加方法 採用施加超音波中，自負載上昇至高負載的方式，自表 面潔淨=至接合之接合卫作暴m氣中的時間在ι〇分鐘 以下。藉由設定該接合條件範圍，確認可將金凸塊之變形 僅殘留於頂端部分近旁，避免基板/晶片間產生位置偏差 ，且晶片上不造成損傷地達成全部接腳之金/金金屬接合 。其檢討結果之一例顯示於圖12及圖13。圖12顯示以金厚 度約20 nm之氬濺射洗淨有機基板側與晶片側之兩面，以 工具振幅3卜111超音波接合時之接合部剖面與伸張剖面之掃 描型電子顯微鏡影像。可知減少接合負載，將基板側之接 合面積與晶片側之接合面積比較，即使約小1/5，仍於伸 張剖面上確認凸塊的一部分附著於基板側，而達成金屬接 合。、此時所謂金屬接合之定義，於藉由伸張力在接合界面 ^成斷妓％，係彳g在金/金接合部達成呈現隨局部伸展之 I伸I·生斷裂的接合，可確認於凸塊側與鍍膜側之斷裂面上 可觀察出金的突起。圖"顯示將凸塊尺寸為5〇 —，電 極間距為80 μπΐ2晶片接合於組合基板上的剖面照片。因 將基板側之接合溫度設定在室溫而無熱變形，自低倍之剖 人^像可知於連接端子之大致巾央，金凸塊精度良好地接 合的狀態。.此外’自中高倍率之影像可知金凸塊之組織僅 於基板側壓碎扁平形成金屬性接合的狀況。對該條件之接 合抽樣調查晶片損傷時’並無損傷產生。從此等檢討結果 可確認，即使具有最小電極間距在⑽_以下，5〇接腳以 上之電極焊墊的LSI晶片，仍可提供基板/晶片間不產生位 15- 200303588 置偏差，且；s u 地倒裝片遠垃入B曰損傷，藉由金/金之金屬接合確實 ^ 接全部接腳之半導體的製造方法。 凸塊次於ί求達成第二目的，於LSI晶片上形成前述之金 面、、絮、爭化土板側I成則述之金鑛膜。接合前之藏射促使表 氣“方法’係採用部分同時進行真空排氣步驟與氬In order to achieve the above-mentioned first object, the present invention is to form an electrode on an LSI wafer with a diameter of a base portion or a rectangular shape—the side size is 60 faces of the electrode size or the minimum electrode pitch is 5G to 9G% A, the height is small. For Η ~. Above 卩 ° 卩, the top portion is further reduced to the diameter of the base portion <,, and the size of the bottom portion, the entire height from the bottom surface to the top is above 30 μχη A gold plating film is formed on the outermost surface of the connection terminals on the organic wiring substrate side. The two flip-chips are named in a large breast room or a depressurized ammonia environment with a pressure of several inches to several Pa. With the German -13 200303588 发明 Description of the Invention Continued 厗 is an argon ion splash with 5 _ or more The surface of the gold bump is engraved physically, and it is physically connected to the surface of the terminal side by an argon ion subtraction method with a thickness of 5 or more or about 1 / 1-10 to 1/2 of the gold film thickness. Both are engraved on the physical surname of His Majesty, and the dry air that is rolled up or removed from the water is used to lift waste and put them into the air. The organic wiring board is mounted on the stage i of the bonding device, and the CD wafer ^ super wave bonding head is reversely adsorbed on the bonding fixture surface, and the two are aligned. 'The bonding head is lowered by 4 ° at this time. The bonding jig is maintained at a specific temperature, and the temperature of the organic wiring substrate and the LSI wafer reaches a specific temperature in the alignment step. After the overlap, the I-disk ultrasonic vibration is applied from the bottom surface of the wafer to perform metal bonding between the gold bump and the gold ore film. The joining conditions at this time are based on the load p applied to each bump being ± (1) (at this time S1 ·· contact area between gold bumps / electrodes): selected within the consumption range. This is because when the load is under this condition, the damage of the wafer with the deformation of the gold bump will occur on the contact portion of the gold bump / pole. The low, and daily joint area is significantly smaller than the size of the bump, which occurs between the wafer / substrate. During thermal distortion and distortion, the bump itself is not deformed. The distortion is concentrated on the joint interface and the probability of disconnection increases. "The joining conditions are that the joint environment humidity is below 60%, and the joining temperature is set; the stage side of the grid substrate is from room temperature to 6 (rc 'at the junction head side temperature to Hot range, and the joining time is 50 to 500. In the range of ms, for the wafer: when the amplitude is 50 kHz, the vibration amplitude is 0.3 ~ 2〇_, so the work: the amplitude of the vibration transmission efficiency between the bonding tool / wafer is 1/2 to 0.6 ~ 4. 〇μιη -14- 200303588 发明 The scope of the description page of the invention, and the appropriate conditions are selected in accordance with the work. In addition, the load is applied by applying ultrasonic waves, rising from the load to a high load, and cleaning from the surface = to the joining joint work. The time in the storm is less than ι0 minutes. By setting the range of the bonding conditions, it can be confirmed that the deformation of the gold bumps can be left only near the top portion to avoid positional deviation between the substrate / wafer and no damage to the wafer. The gold / gold metal bonding of all the pins is achieved. An example of the results of the review is shown in Figs. 12 and 13. Fig. 12 shows that both sides of the organic substrate side and the wafer side are cleaned by argon sputtering with a gold thickness of about 20 nm. Tool amplitude 3 bu 111 super Scanning electron microscope image of the joint section and extension section during sonic bonding. It can be seen that the joint load is reduced, and the joint area on the substrate side is compared with the joint area on the wafer side. Even if it is about 1/5 smaller, the convexity is still confirmed on the extension section. Part of the block is attached to the substrate side to achieve metal bonding. At this time, the so-called metal bonding is defined as the percentage of breakage at the bonding interface by extension tension, which is achieved when the gold / gold joint is partially stretched. Bonding of I and I fractures can be confirmed by gold protrusions on the fracture surface of the bump side and the coating side. The figure " shows that the bump size is 50- and the electrode spacing is 80 μπΐ2. Cross-section photograph on the combined substrate. Since the junction temperature on the substrate side is set at room temperature without thermal deformation, it can be seen from the cut-out image of the low magnification that the approximate center of the connection terminal and the gold bump are accurately joined. In addition, 'from the images of medium and high magnification, it can be seen that the structure of the gold bumps is only crushed and flattened on the substrate side to form a metal joint. When the joint is sampled for damage under this condition, no damage is found' Damage occurred. From the results of these reviews, it can be confirmed that even LSI chips with electrode pads with a minimum electrode pitch of less than ⑽_ and 50 pins or more can still provide a substrate / wafer position deviation of 15-200303588, and ; Su ground flip chip is far into B damage, and the manufacturing method of the semiconductor that is connected to all the pins by gold / gold metal bonding. The bump is inferior to the second one, and the aforementioned is formed on the LSI wafer. The surface of the gold surface, scum, and scrabble is described as a gold ore film on the side of the clay plate. The hidden shot before joining promotes the surface gas "method" is to use part of the simultaneous vacuum exhaust step and argon

Lsr片^Γ㈣’其係因應必要數量依序進行使數個 其板牛° 、於知盤上進行同時賤射步驟及同時滅射數個 步驟。此外選擇接合溫度係將搭載基板之載台 1 J 口又於至溫，僅使吸附曰 波與負载進行接合的方;並施加超音 ,/4. 、 百光於濺射洗淨步驟中，Μ 氣壓=排氣ΐ氬氣導入一部分時間性重疊，可縮短將‘ 上严：：t特疋壓力的時間’提早開始放電，藉由在拖盤 曰=曰曰片可同時搬運及洗淨多數個晶片，其係將基板盘 開洗淨方式’可促使各個洗淨條件最佳化及適時洗 所需數量，可大幅縮短工作之洗淨所需時間 驟=2加將基板與晶片兩者之接合表面與以潔淨 心的超音波接合，可大幅改善金/金接合性，可在 二：：短時間接合，由於縮短昇温時間與熱性穩定，、， 、、-紐對準步驟，可大幅縮短倒裳片接合步驟 =性。此外，藉由接合性之提高亦有助於大幅減少^ 不良，而提高生產良率。 為求達成第三目的，將形成於配線基板上之有機 、-、、彖層上之銅微細配線圖案以自絕緣層上突出的形 ’於該銅配線上的最表面形成金膜，形成LSI晶片電極上 -16- 200303588 (ίο) 發明說明續頁 之至凸塊與金鍍膜對於伸張 , 其金凸塊接合部係以2 μηι 以上之延伸接合電平進行全屬 始 7 ^ 屬接合，於晶片/基板間之間 隙’以低熱膨脹填充含微細 ^ ^ <無械填料的樹脂予以凝固的 構造。此時將金在2 μηι以卜证从a g 上^伸條件的定義與斷裂例同時 顯示於圖9、圖10、圖11。蕤 错由接合電平，斷裂位置分散 於凸塊/金膜之接合界面近套、 、方 凸塊内、及凸塊/鋁電極之The Lsr film ^ Γ㈣ 'is performed in order to make a number of slabs according to the necessary number, to perform simultaneous low-level firing steps and simultaneous multiple-level firing steps on the known disc. In addition, the bonding temperature is selected to be the temperature at which the 1J port of the substrate on which the substrate is mounted is brought to the highest temperature, and only the side where the suction wave is bonded to the load is applied; and a supersonic, / 4., Baiguang is used in the sputtering cleaning step, Μ air pressure = exhaust gas, argon gas introduction part overlaps in time, which can shorten the time of 'upper strict :: t special pressure' to start the discharge earlier. By dragging the tray at the same time, the majority can be transported and washed at the same time. The number of wafers is based on the method of opening and cleaning the substrate disk, which can promote the optimization of various cleaning conditions and the required number of timely cleaning, which can greatly reduce the time required for cleaning. 2 The bonding surface and the ultrasonic bonding with a clean heart can greatly improve the gold / gold bonding. It can be bonded in a short time: due to the shortening of the heating time and the stability of the thermal properties. Shorten the step of joining the pieces upside down = sex. In addition, the improvement in bonding also contributes to a significant reduction in ^ defects and improves production yield. In order to achieve the third object, a copper fine wiring pattern formed on the organic,-, and hafnium layers on the wiring substrate is formed in a shape protruding from the insulating layer to form a gold film on the outermost surface of the copper wiring to form an LSI. On the wafer electrode-16- 200303588 (ίο) Description of the invention continued from the continuation sheet to the bumps and gold plating. For the stretch, the gold bump joints are all extended at a level of 2 μηι or more. The gap between the wafer and the substrate is a structure in which a resin containing a fine filler and a solid filler is solidified with low thermal expansion. At this time, the definition of the extension condition of gold from ag at 2 μm is shown in Fig. 9, Fig. 10, and Fig. 11 at the same time.由 Depending on the bonding level, the fracture locations are scattered in the near interface of the bump / gold bonding interface, inside the square bump, and between the bump / aluminum electrode.

接合=面近旁，不過任何情況均將Hb—則作為金的延伸。 首先藉由以金/金之金屬接合予以連接的構造，促使連接 部之耐熱性與電性大幅提高。其次，#由金/金接合電平 具有可在接合界面吸收2_以上時變的性能，S晶片/基 板間填充含無機填料之樹脂，以不造成大畸變的方式凝固 接5邓使基板之配線層高於基板面而實質地擴大晶片/ 基板間隙，減少施加於接合部之熱畸變，可大幅改善溫度 周期可罪性，可以具有延展性之金接合部吸收因吸濕等造 成曰曰片/基板間隙擴大，因此可大幅提高高溫高濕可靠性。 【發明之實施形態】Junction = near the surface, but in any case Hb-as an extension of gold. First, the structure of connection by gold / gold metal bonding promotes greatly improved heat resistance and electrical properties of the connection portion. Secondly, # the gold / gold bonding level has a time-varying property that can absorb more than 2_ at the bonding interface. The S-wafer / substrate is filled with a resin containing an inorganic filler, and solidified in a manner that does not cause large distortion. The wiring layer is higher than the substrate surface, which substantially enlarges the wafer / substrate gap, reduces the thermal distortion applied to the joints, can greatly improve the temperature cycle guilty, and can have a ductile gold joint to absorb the film caused by moisture absorption, etc. / The substrate gap is enlarged, so the reliability of high temperature and high humidity can be greatly improved. [Embodiment of Invention]

以下’使用圖式详細說明本發明之實施例。 圖1顯示一種本發明之半導體裝置之剖面構造的實施例 。圖中之配線基板以：核心基板丨2 ;形成於其兩側之組合 層1 7 ’ 27，..及晶片用連接端子2 1構成。核心基板丨2由：藉 由I虫刻與玻璃環氧絕緣板8接著之銅落予以圖案化之粗配 線層1 0 ’ 11 ;及連接表與裡之配線間用之貫穿通孔9構成 ’組合層1 7由··藉由塗敷而形成之薄絕緣層丨3 ;以焊接法 形成於其上之微細配線層丨4 ;及連接粗配線層與微細配線 -17- 200303588 00 Γ-- 發明說明績頁 二。r連通孔15構纟。由於組合層中之薄絕緣層係以150〜 toc之溫度硬化烘烤㈣樹脂者，因此㈣度在峨以 下且彈性率亦為低值。晶片用诖姑v y 連接^子2 1係由以銅鍵所 形成之微細配線1 8與其上之婷# , n 又螺鍍胰19、以及其上之金鍍膜 成。錢係以摻人磷之無電解鍍形成者，膜厚為5〜 μι金鑛係以替換型無電解鑛所形成者，膜厚為 〇·〇—半導體晶片6具有形成於半導體基板艸央之電 路形成=2的區域與形成於周邊之疊層絕緣膜3的區域，並 具有覆蓋外部連接用之鋁電極烊墊4與其以外區域之保饉 膜5。於半導體晶片之紹電極焊塾上藉由超音波熱壓著: 球形接合法形成有金凸塊。晶片 曰曰乃（電極焊墊數為256接腳 ’谭墊間距為80μΐη，焊塾尺寸為邊長65_，焊塾材質為 鋁-銅或鋁-銅-矽，鋁膜厚為4〇〇nm〜1〇〇〇nm。金凸塊尺 寸為壓著後之凸塊徑為5〇μιηΦ，台座高度為1〇〜25陶， 頭部徑為30〜40μηιΦ’高度為35〜5〇_，包含至配線之 突起部的整個高度為50〜70 μηι。而倒裝片接合步驟之表 面潔淨化處理，係藉由氬氣以金膜厚相當於1〇〜2〇⑽部 分濺射蝕刻基板側之金凸塊面，以金膜厚相當於5〜i〇nl 部分濺射蝕刻基板側之金凸塊面。表面潔淨化處理後，自 放入空氣中至進行接合的時間在丨0 min以内，並在周圍相 對濕度為60%以下的環境下進行接合。接合條件其接合負 載模式採超音波施加中使負載增加的變動負載方式，初期 負載為1 g/bump〜5 g/bump，最後負載為1〇 g/bump〜3〇 bump之範圍，抵接晶片之工具頂端之振動振幅在i〜4 -18- 200303588 發明說明績頁 (12) 之範圍’赵音波施加時間在1⑼m s〜5 m s之範圍，從其 中選擇最佳條件。具體而言，係以初期負載5 g / bump (1.2 8 kg) ’最後負載2〇g/bump (512kg)，振動振幅3叫， 超音波施加時間300㈣進行接合。接合溫度於晶片側之工 具加熱溫度為b〇°c，搭載基板之載台溫度為室溫：20X： 。實際之接合部的剖面如圖B所示。儘管組合基板之金膜 厚非常薄，金/金接合界面上幾乎未發現缺陷地達成金屬 接合。有機基板之外部連接端子23上經由鎳鍍膜形成有無 鉛焊凸塊28。初期金膜熔解於焊料中而未殘留於界面上。 本實施例因可於具有以8〇 μηι之配線間距所形成之低玻 璃轉移溫度之表面絕緣層的有機配線基板上，將形成微細Hereinafter, embodiments of the present invention will be described in detail using drawings. FIG. 1 shows an embodiment of a cross-sectional structure of a semiconductor device of the present invention. The wiring substrate in the figure is composed of: a core substrate 2; a combination layer 17'27 formed on both sides thereof; and a connection terminal 21 for a wafer. The core substrate 2 is composed of: a rough wiring layer 1 0 '11 patterned by a copper foil followed by a glass epoxy insulation plate 8 and a through-hole 9 used to connect the wiring between the table and the wiring. The combination layer 17 is composed of a thin insulating layer formed by coating; 3; a fine wiring layer formed thereon by a soldering method; 4; and a connection between the coarse wiring layer and the fine wiring. 17-200303588 00 Γ-- Invention Description Page Two. The r communication hole 15 is formed. Because the thin insulating layer in the combined layer is a hardened baking resin at a temperature of 150 to toc, the degree of elasticity is below E and the elastic modulus is also low. The wafer is connected with the substrate y by the substrate y. The micro-wires 18 are formed by copper bonds with the tines #, n, and the gold plating 19 thereon. The money is formed by electroless plating with doped phosphorus, and the film thickness is 5 ~ μm. The gold is formed by replacement type electroless ore, and the film thickness is 〇—〇—The semiconductor wafer 6 has a semiconductor substrate formed on the center of the semiconductor substrate. The area where the circuit is formed = 2 and the area where the laminated insulating film 3 is formed in the periphery, and has a protective film 5 covering the aluminum electrode pad 4 for external connection and the area outside it. Gold bumps are formed on the solder pads of semiconductor wafers by ultrasonic thermal compression: a spherical bonding method. The chip is called (the number of electrode pads is 256 pins. The pitch of the pad is 80μΐη, the size of the pad is 65_, the material of the pad is aluminum-copper or aluminum-copper-silicon, and the thickness of the aluminum film is 400nm. ~ 100nm. The size of the gold bumps is 50μmηΦ after pressing, the height of the pedestal is 10 ~ 25 ceramics, the diameter of the head is 30 ~ 40μηΦ, the height is 35 ~ 50, including The entire height of the protrusions to the wiring is 50 ~ 70 μηι. The surface cleaning process of the flip-chip bonding step is performed by argon gas with a gold film thickness equivalent to 10 ~ 20⑽. The gold bump surface is a gold bump surface with a gold film thickness equivalent to 5 ~ 10nl. The gold bump surface on the substrate side is partially sputter-etched. After the surface is cleaned, the time from placing in the air to joining is within 0 minutes. And the bonding is performed under the surrounding relative humidity of 60% or less. The bonding conditions are based on a variable load method that increases the load during ultrasonic application. The initial load is 1 g / bump ~ 5 g / bump, and the final load is The range of 1〇g / bump ~ 3〇bump, the vibration amplitude of the tool tip abutting the wafer is i ~ 4 -1 8- 200303588 Description sheet of the invention (12) 'Zhao Yinbo's application time is in the range of 1⑼m s ~ 5 ms, and the best conditions are selected from this. Specifically, the initial load is 5 g / bump (1.2 8 kg) 'The final load is 20g / bump (512kg), the vibration amplitude is 3, and the ultrasonic application time is 300㈣ for bonding. The bonding temperature of the tool on the wafer side is b0 ° c, and the temperature of the stage on which the substrate is mounted is room temperature: 20X: The cross-section of the actual joint is shown in Figure B. Although the gold film thickness of the combined substrate is very thin, metal bonding is hardly found at the gold / gold bonding interface. The external connection terminal 23 of the organic substrate is passed through nickel. The plating film is formed with lead-free solder bumps 28. The initial gold film is melted in the solder without remaining on the interface. In this embodiment, an organic material having a surface insulating layer with a low glass transition temperature formed at a wiring pitch of 80 μm can be used. Fine wiring will be formed on the wiring board

之金柱形凸塊之LSI晶片，不產生連接部之位置偏差，』 不產生晶片損傷，亦即不產生鋁電極下之絕緣多層膜之系 痕地藉由金/金之金屬接合，倒裝片連接全部256^腳，泛 此可提供搭載於具有最尖端之超高速LSI晶片之有機基相 上的高可靠性多晶片模組。此時，因LSI晶片上無須二办 特殊的加工，可降低模組製品的成本，可以短期間（約2你 月）製成之有機基板構成模組，因此具有可於短期間開潑 組裝客戶所需規格之系統模組的效果。此外 :又 ,,. 邪具有在以 、’、、·1 mm離接晶片的狀態下可搭載於基板上，促進高资产 =裝化，可達到模組小型化的效果。另外，因接合:二才= 造係以具有延展性之金/金金屬接合連接，且其形狀係形 成晶片側較大，基板側較小的接合形狀，因此， ^ : 片/基板間產生畸變，於晶片側產生高應力之前，係以美 -19- 200303588 〇3) 發明說明繽頁 板側之金凸塊部及接合界面近旁之塑性變形來吸收崎變， 因此亦具有不產生模組組裝步驟中之晶片損傷及接合部斷 線等組裝不良，可以高良率組裝模組，而降低製品成本的 效果。LSI wafers with gold stud bumps do not produce positional deviations in the connection, and no chip damage occurs, that is, no traces of the insulating multilayer film under the aluminum electrode are bonded by gold / gold metal, flip-chip All chip connections are 256 ^ feet, which can provide high-reliability multi-chip modules mounted on the organic phase of the most advanced ultra-high-speed LSI chips. At this time, since no special processing is required on the LSI wafer, the cost of the module product can be reduced, and the module can be formed from an organic substrate made in a short period of time (about 2 months). Therefore, customers can be assembled in a short period of time. The effect of the required system module. In addition,: ,,. Evil can be mounted on a substrate in a state where wafers are separated by 1mm, 1mm, 1mm, 1mm, 1mm, and can be mounted on a substrate, which promotes high asset = mounting and can achieve the effect of miniaturization of the module. In addition, the bonding: Ercai = the system is connected with a malleable gold / gold metal joint, and its shape is formed on the wafer side and the substrate side is smaller, so ^: distortion between the wafers / substrates Before the high stress is generated on the wafer side, it is based on the US-19-200303588 〇3) Invention description The gold bumps on the side of the bin sheet and the plastic deformation near the joint interface to absorb the variability, so it also has no module assembly In the step, the wafer is damaged and the assembly is broken, and the assembly is poor. The module can be assembled with high yield and the cost of the product can be reduced.

此外，由於可倒裝片安裝於金膜厚為0·03〜〇 〇6 μηι之非 常薄的連接端子’因此亦可使基板外部連接端子側的金膜 厚同樣地薄，即使以富含錫的焊料形成焊接凸塊，仍具有 不形成金錫金屬間化合物層，促使焊料連接部高強度化， 可提高與母板之連接可靠性的效果。 圖2顯示本發明之半導體裝置構造的其他實施例。圖中 之組合基板係於具有通孔配線32與兩面配線33，34之核心 基板35之兩側形成有組合層42，49的構造，其係包含·以 塗敷形成之絕緣層36’ 37, 43’ 44;以鍍形成之微細配線 38，45 ;連通孔配線40 ’ 47，48 ;及以最表面之金膜厚為 〇.〇5 pm之鍍形成之連接端子39, 41 ’ 組合基板之一In addition, since the flip-chip can be mounted on very thin connection terminals with a gold film thickness of 0.03 to 0.06 μm, the thickness of the gold film on the external connection terminal side of the substrate can also be made thin, even with rich tin. The solder forms a solder bump, and still does not form a gold-tin intermetallic compound layer, which promotes the strength of the solder connection portion and can improve the effect of connection reliability with the motherboard. FIG. 2 shows another embodiment of the structure of the semiconductor device of the present invention. The combined substrate in the figure is a structure in which combined layers 42 and 49 are formed on both sides of a core substrate 35 having through-hole wiring 32 and two-sided wirings 33 and 34, and includes an insulating layer 36 '37 formed by coating. 43 '44; fine wiring 38, 45 formed by plating; interconnect hole wiring 40' 47, 48; and connection terminals 39, 41 'formed by plating with the outermost gold film thickness of 0.05 pm One

面，數個LSI晶片51經由藉由球形接合法而形成於紹電極 52上之金凸塊55，以金/金之金屬接合連續搭載於基板之 連接端子41上。並以Λ换古洛& 凸鬼π度為30 μιη，配線高度為2〇 μηι 組裝。該LSI晶片/基板間填充有含對晶片側之鈍化膜”盥 基板絕緣層3^方接著性良好之無機填料的底填樹脂56。 此外，被動零件57藉由無料與續搭載於連接端子39上 。另外，於組合基板之另一側上，以覆蓋連接端子Μ之一 部勿的方式形成有光阻膜59， 早 凸塊。圖3顯示圖2之半導妾：子上形成有無錯焊 干V體裝置之組裝流程的一種實施例 -20- 200303588 發明說明續頁 (14) 。LSI晶片形成金柱形凸塊並實施濺射洗淨，組合基板準 備經過錢射洗淨者後，於基板上依序超音波倒裝片接合特 定數量的LSI晶片。金凸塊之濺射厚度在1〇111][1以上，基板 側之藏射厚度在金膜厚之1/10以上或1〇nm以上。接合溫 度於晶片側為常溫〜1 5 0。〇，基板側為常溫〜6 〇 °c。L SI晶 片接合後，於晶片/基板間灌入底填樹脂，於12 〇 以下溫 度進行初期烘烤。其次，於基板之晶片搭載側的被動零件 連接端子上印刷焊接漿液，供給被動零件進行平坦化熱處 理。其次將局部塗敷焊劑之焊接球供給至連接端子，進行 平坦化熱處理。农後洗淨焊劑後，藉由1 5 〇之烘烤使乙$ I 晶片下的底填完全硬化而完成組裝。 本貝施例基於組裝成LSI晶片/組合基板之間隙擴大至5〇 ，且於其間隙填充樹脂，並藉由加熱烘烤加以硬化，因此 ，藉由樹脂硬化收縮與自烘烤溫度1 5〇°c冷卻，接合部上 始終施加壓縮力，於溫度周期測試及高溫高濕測試中，接 合部上不產生導致剝離的強大力，此外，因微小之剪切崎 麦可以柔軟之金凸塊的塑性變形吸收，因此接合部周邊不 產生咼應力等因素，可提供L SI晶片之連接可靠性非常高 的半導體裝置。此外，由於以0·05 μηι之非常薄的膜構成 基板之連接端子的金膜厚，因此亦具有可提高焊接連接部 之可靠性的效果。此外，由於LSI晶片之微小連接部係低 電阻之金，並以金屬性且以最短距離連接於基板，因此亦 具有連接部之電阻及阻抗成分非常小，電性優異，可縮短 仏號傳送延遲’避免高速系統之性能降低的效果。此外， -21 - 200303588On the other hand, a plurality of LSI chips 51 are continuously mounted on the connection terminals 41 of the substrate by gold / gold metal bonding via gold bumps 55 formed on the shao electrode 52 by a ball bonding method. Assemble Λ for Gulo & Convex pi with 30 μm and wiring height of 20 μm. This LSI wafer / substrate is filled with an underfill resin 56 containing an inorganic filler with a good passivation film on the wafer side, a substrate insulation layer 3, and a good adhesion. In addition, the passive component 57 is mounted on the connection terminal 39 without material and continued. In addition, a photoresist film 59 and an early bump are formed on the other side of the combined substrate so as to cover one part of the connection terminal M. FIG. 3 shows the semiconducting conductor shown in FIG. An example of the assembly process of the solder-dry V-body device-20- 200303588 Description of the Invention Continued (14). After the LSI wafer is formed into gold pillar bumps and subjected to sputtering cleaning, the combined substrate is prepared to be cleaned by money injection. A specific number of LSI wafers are sequentially bonded on the substrate by ultrasonic flip-chips. The sputtering thickness of the gold bump is 1010] [1 or more, and the thickness of the substrate side is 1/10 or more of the gold film thickness or 1 〇nm or more. Bonding temperature is from normal temperature to 150 ° on the wafer side, and normal temperature to 60 ° C on the substrate side. After the L SI wafer is bonded, an underfill resin is poured between the wafer and the substrate, and the temperature is below 120 ° C. Initial baking is performed. Second, passive components on the wafer mounting side of the substrate The soldering paste is printed on the connection terminals, and the passive parts are supplied for flattening heat treatment. Secondly, the solder balls partially coated with the flux are supplied to the connection terminals for the flattening heat treatment. After the solder is cleaned after the farming, the baking is performed by 150 The underfill under the wafer is completely hardened to complete the assembly. This example is based on the fact that the gap assembled into the LSI wafer / composite substrate is enlarged to 50, and the gap is filled with resin, and is hardened by heating and baking, so With resin hardening shrinkage and self-baking temperature of 150 ° C, compressive force is always applied to the joint. In the temperature cycle test and high temperature and high humidity test, no strong force that causes peeling is generated on the joint. In addition, The micro-sheared sintered wheat can absorb the plastic deformation of the soft gold bumps. Therefore, there are no factors such as pinch stress around the joints, and it is possible to provide a semiconductor device with very high connection reliability of the L SI chip. The very thin film of 05 μm constitutes the gold film thickness of the connection terminals of the substrate, so it also has the effect of improving the reliability of the soldered connection. In addition, since LSI The tiny connection part of the piece is low-resistance gold, and is connected to the substrate with a metallic property and the shortest distance. Therefore, the resistance and impedance components of the connection part are very small, and the electrical property is excellent, which can shorten the transmission delay of the 仏 number. Effect of reducing performance. In addition, -21-200303588

發明說明續頁 高，因此亦具有容易自 接搭載，可混合搭載超 系統構造的選擇範圍廣 由於金/金倒裝片接合部之耐熱性 後面進行被動零件及LSI零件的燁 尖端之LSI晶片與焊接接合零件， ’設計容易的效果。Description of the invention The continuation sheet is high, so it also has easy self-mounting. It can be mixed with a wide range of super-system structures. The choice is wide. Due to the heat resistance of the gold / gold flip-chip joints, passive parts and LSI parts are equipped with advanced LSI chips. Welding joint parts, 'Design easy effect.

圖4顯。示本發明之半導體裝置之剖面構造的其他實施例 。微細早面配線基板65之微細連接端子66係於銅圖案上奋 施鎳/純。在LSI晶片6G，61之銘電極上形成有金柱开^ 塊，亚藉由金/金之金屬接合與基板65之連接端子連接。 於基板與LSI晶片之間填充有含無機填料之低熱膨服樹脂 ，並藉由加熱予以硬化。基板65接著於母板68加以固定， 基板與母板之間以金線70之線接合連線。 本實施例因以無通孔之單面配線基板構成模組，因此具 有可以貼薄銅箔之基板的蝕刻處理來製造，可藉由降低基 板成本而降低模組成本的效果。此外，因於包含母板搭載 前並無焊接接合部，因此亦具有附加零件之焊接搭載^受 限制’組裝容易’可提高溫度周期可靠性及高溫高濕可=Figure 4 shows. Another embodiment of the cross-sectional structure of the semiconductor device of the present invention is shown. The fine connection terminals 66 of the fine early-side wiring substrate 65 are nickel / pure on a copper pattern. Gold pillar openings are formed on the LSI wafers 6G and 61, and are connected to the connection terminals of the substrate 65 by gold / gold metal bonding. A low thermal expansion resin containing an inorganic filler is filled between the substrate and the LSI wafer, and is hardened by heating. The base plate 65 is then fixed on the mother board 68, and the base plate and the mother board are connected by gold wires 70. In this embodiment, since the module is constituted by a single-sided wiring substrate without a through hole, it has an effect that the substrate can be etched with a thin copper foil, and the cost of the module can be reduced by reducing the cost of the substrate. In addition, since there is no solder joint before mounting on the motherboard, welding mounting with additional parts is also limited ^ Restricted ‘Easy assembly’ can improve temperature cycle reliability and high temperature and high humidity =

性的效果。 圖5顯示本發明之半導體裝置之剖面構造的其他實施例 。圖中於兩層配線印刷基板93之一面的一部分，藉由接著 劑86貼附具有通孔85的單面帶基板％，帶基板之^孔電極 Μ與印刷基板之連接端子9〇係以金/金之高負載條件的加 熱壓著接合。形成於帶基板之配線連接端子以與乙“晶片 8〇之鋁電極8 1的金鍍凸塊82係藉由超音波熱壓著進行金/ 金接合。於晶片/帶基板間填充有樹脂87並加以硬化。於 -22- (16) (16)200303588 發明說明續頁 印刷基板之底面的外部連接端子9丨上形成有焊接凸塊。 本實施例因採僅於LSI晶片搭載部上形成微細配線區域 的構造，可以壓著以其他步驟製出之微細配線帶基板的方 法製造模組基板，因此可提高基板製造之通量，可降低成 本。此外，亦具有於LSI晶片因收縮等因素而規格變更時 ，僅將帶基板作最小限度的變更即可再製造基板，可縮短 規格變更之開發期間的效果。 圖6顯示本發明之LSI晶片與有機配線基板之接合構造的 種貫鉍例。圖中於LSI晶片1 〇〇之鋁電極丨〇丨上，藉由球 接合法形成有金柱形凸塊103。柱形凸塊由：金球被毛細 管工具之頂端面壓碎之厚度為2〇 μιη之基座部、壓入毛細 孔所形成之殼部、與金線經過伸張斷裂而形成之尖塔狀的 頂端部構成，形成僅壓碎頂端部，而於基板之連接端子上 金/金接合的形狀。晶片側之接合部直徑為45 ，基板側 之接合部直徑為30 μιη。有機配線基板係於核心基板115之 兩面形成薄絕緣層107’ 108後’在其上形成微細配線層的 構造。晶片連接端子之構造係於銅圖案上鎳/金或鎳/鈀/金 鍍之構造，金厚度或鈀+金厚度為〇〇5〜〇1pm。 本貫施例因基板侧的接合面積比晶片側之接合面積小達 1/2以下，凸塊高度係維持初期之柱形凸塊殼部的高度， 因此即使產生接合後之負載釋放時產生之基板的反挽曲， 晶片之鋁電極周邊未施加金屈服強度之1/2以上之力，因 此不致應力性破壞晶片之鋁電極下的絕緣多層膜。因此， 即使基板之平坦精密度低，仍具有組裝良率高的效果。該 -23- 200303588 _ (17) 發明說明績頁 應力的問題，於接合中同樣地，係控制成實施例之凸塊形 狀，因此亦具有減少接合時之晶片損傷的效果。 圖7顯示本發明之LSI晶片與有機配線基板之接合構造的 其他實施例。圖中於LSI晶片120之鋁電極121上，以一部 釦復盍於鈍化膜122之方式形成有金屬喷鍍膜123，其上藉 由鍍法形成有金凸塊。金凸塊於鍍步驟後施加熱處理，以 維氏硬度Hv在80以下之方式實施軟質化處理。有機配線基 板之晶片連接端子1 3 7之連接端子頂端部的尺寸設計成小 於凸塊底面的尺寸，接合後之端子側的接合面積形成凸塊 底面之面積W2以下的尺寸。具體而纟，凸塊係長4"mx ，15μχη，連接端子之基座部寬3〇μιη，頂端部寬2〇gm， 高20 μηι。連接端子之構造係於銅圖案上鎳_磷/金或鎳_磷〆 鈀/金鍍的構造，金厚度或鈀+金厚度為〇〇5〜〇.hm。 本貫施例因採藉由金/金金屬接合將形成金鍍凸塊之lsi 晶片搭載於有機配線基板上的構造，鋁電極並未暴露於外 邛，即使暴露於高溫高濕環境之腐蝕環境下亦不受其影響 ’因此可提，可靠性非常高的半導體裝置。此外，因凸塊 底面大達覆蓋於鈍化膜，形成連接端子接觸於凸塊中央的 配置’因此亦具有銘電極周邊不產生應力集中，不對曰片 造成接合摄傷，可提高組裝良率的效果。最令人擔心：， 係=凸塊變形不易，無法吸收基板高度不均一及鑛凸塊 之鬲度不均一，而產生去技入 ^ 低全凸塊之硬错由以熱處理降 塊之硬度及％小連接端子尺寸’容易擠入金鑛凸塊 ’精由金凸塊之局部性變形來吸收高度不均—即可避免該 -24- (18) (18)200303588 發明說明績頁 問題。 圖8顯示本發明之半導體裝置之剖面構造的其他實施例 。圖中係於LSI晶片140之電路形成面上形成有由厚度為二〜 4μιη聚醯亞胺之絕緣膜142與附隔離膜之銅配線143構成之 再配線層，其上形成有最表面係金膜之電極端子Μ#。其 电極端子上藉由球接合法形成有金柱形凸塊丨45。有機配 線基板係配線間距200 μπι之印刷電路基板，並於連接端子 上實施鎳/金電鍍。於基板背面之外部連接端子上形成有 焊接凸塊。此外，⑥晶片/基板間填充有樹脂加以凝固。 /本實施例因係使用於微細間距之LSI晶片上藉由再配線 形成擴大層之晶片，以金/金金屬接合連接於有機基板上 ，因此有機配線基板上可使用一般之印刷電路基板，可予 以低成本化。此外，因係經由聚醯亞胺之緩衝將接合時之 應力傳導至晶片的構造，因此完全不產生組裝步驟時之晶 片相傷，可配合對準容易度大幅提高良率。此外，因晶片 /基板間之連接部的耐熱性與可靠性高，因此亦具有對模組 搭載於母板處理幾乎無限制，處理容易使用性佳的效果。 【發明之功效】 如以上詳述，本發明可提供一種於具有最小配線間距 100 μΐη以下之微細配線層，具有低玻璃轉移溫度之表面絕 緣層的有機配線板上’將具有最小電極間距在·帅以下 ，接腳以上之電極焊塾之LSI晶片’不產生基板/晶片間 之：置偏| ’且不產生晶片損傷’藉由金/金之金屬接合 確實地倒裝片連接全部接腳之半導體的製造方法。 -25- (19) (19)200303588 發明說明繽頁 μ此外可提供-種可以高可靠且低阻抗之特性將多接腳· U細間距之LSI晶片搭載於具有微細配線層之有機配線基 板上’組裝良率高且生產性優異之安裝構造及安裝處理。 卜可提供一種於表面層上具有包含微細配線層與低 ，璃轉移溫度之有機絕緣層之組合層之有機配線基板上，_ 猎由倒裝片連接搭載具有5〇接腳以上之電極焊墊之多接腳 ，曰曰片，且倒裝片連接部之耐熱性，、高溫高濕及 溫度周期可靠性優異之半導體裝置。 【圖式之簡單說明】 圖1係本發明之半導體裝置之剖面構造的一種實施例。 圖2係本务明之半導體裝置之剖面構造的其他實施例。 圖3係本奄明之半導體裝置之剖面構造的其他實施例。 圖4係本务明之半導體裝置之剖面構造的其他實施例。 圖5係本發明之半導體裝置之剖面構造的其他實施例。 圖6係本發明之LSI晶片與有機配線基板之接合構造的一 種實施例。 圖7係本發明之LSI晶片與有機配線基板之接合構造的其 他實施例。 一 圖8係本發明之半導體裝置之剖面構造的其他實施例。 圖9係接合部伸張斷裂時之金伸展的定義與斷裂例。 圖10係接合部伸張斷裂時之金伸展的定義與斷裂例。 圖11係接合部伸張斷裂時之金伸展的定義與斷裂例。 圖1 2係金凸塊接合部之剖面形狀與斷裂狀況。 圖13係80 _間距LSI晶片與組合基板之接合剖面例。 (20) (20)200303588 發明說明續頁 圖式代表符號說明 1…矽基板、2…電路形成區域、3…疊層絕緣膜、4…鋁 電極焊墊、5…保護膜、6，5‘··半導體晶片、7，55，82 …金凸塊、8…玻璃環氧絕緣板、9，85…通孔、，1卜·· 配線層、12，35，1 15 ···核心基板、13，22，36，37，43 ’ 44 ’ 107 ’ 108 ’ 126 ’ 128…絕緣層、14···微細配線層、 15，24…連通孔、16，25，59，92，113，135，15〇 …光 阻膜、17 ’ 27 ’ 42，49···組合層、18，38，45···微細配線 、19，26，110 ’ 131···鎳鍍膜、2〇，lu，132···金鍍膜、 21 ’ 39 ’ 41 ’ 46 ’ 66 ’ 90 ’ 91，133 ’ 148···連接端子、23 ，67，112，134 ’ 149···外部連接端子、28，5〇，94，114 ，136 ’ 152…焊接凸塊、31，146···有機絕緣基板、32， 89，147···通孔配線、33，34，1〇5，1〇6，127，129 ••配 線、40，47，48…連通孔配線、51，6〇，61，8〇，1〇〇， 120 ’ 140··· LSI晶片、52，62，81，1〇1，121，141···鋁電 極、53，63 ’ 102，122…鈍化膜、56…底填樹脂、57···被 動零件、58…焊接、64，103，145·.·金柱形凸塊、65…配 線基板、68…母板、69…WB連接端子、7〇…金線、83··· 絕緣帶、84…配線連接端子、86···接著劑、87，ι51·••樹 脂、88…玻璃環氧基板、93…印刷基板、95…帶基板、 104，125···有機絕緣板、1〇9，130…銅圖案、123…金屬 喷鍛膜、124···金鍍凸塊、142…絕緣膜、143…銅配線、 144···電極端子。 -27-Sexual effect. FIG. 5 shows another embodiment of the cross-sectional structure of the semiconductor device of the present invention. In the figure, on a part of one surface of the two-layer wiring printed circuit board 93, a single-sided substrate with a through-hole 85 is attached by an adhesive 86. The hole electrode M with the substrate and the connection terminal 90 of the printed circuit board are made of gold. / Heavy pressure bonding under high load conditions. The gold-plated bumps 82 formed on the wiring connection terminals of the substrate with the aluminum electrode 81 of the wafer 80 are bonded by gold / gold by ultrasonic thermal compression. The resin 87 is filled between the wafer / band substrate Solder bumps are formed on the external connection terminals 9 丨 on the bottom surface of the printed circuit board at -22- (16) (16) 200303588. Description of the Invention In this embodiment, the micro-fabrication is formed only on the LSI chip mounting portion. The structure of the wiring area can be used to manufacture the module substrate by pressing the fine wiring tape substrate produced by other steps. Therefore, the throughput of the substrate manufacturing can be improved and the cost can be reduced. In addition, it also has the LSI chip due to shrinkage and other factors. When the specification is changed, the substrate can be remanufactured with only minimal changes to the tape substrate, which can shorten the development period of the specification change. Fig. 6 shows an example of bismuth in the joint structure of the LSI wafer and the organic wiring substrate of the present invention. In the figure, a gold cylindrical bump 103 is formed on the aluminum electrode 丨 〇 丨 of the LSI wafer 100 by a ball bonding method. The cylindrical bump is formed by a thickness of 2 where the gold ball is crushed by the top surface of the capillary tool. 〇 The base part, the shell part formed by pressing into the pores, and the spire-shaped top part formed by the gold wire being stretched and broken, are formed by crushing only the top part, and gold / gold bonding on the connection terminal of the substrate The diameter of the joint on the wafer side is 45 and the diameter of the joint on the substrate side is 30 μm. The organic wiring substrate is a structure in which a thin insulating layer 107 '108 is formed on both sides of the core substrate 115, and a fine wiring layer is formed thereon. The structure of the chip connection terminal is a structure of nickel / gold or nickel / palladium / gold plating on a copper pattern, and the thickness of gold or palladium + gold is 005 ~ 〇1pm. This embodiment is based on the ratio of the bonding area on the substrate side. The bonding area on the wafer side is as small as 1/2 or less, and the bump height is maintained at the initial height of the cylindrical bump shell portion. Therefore, even if the reverse buckling of the substrate occurs when the load is released after bonding, the aluminum electrode periphery of the wafer The force of 1/2 or more of the yield strength of gold is not applied, so that the insulating multilayer film under the aluminum electrode of the wafer is not stress-damaged. Therefore, even if the flatness precision of the substrate is low, the effect of high assembly yield is still obtained. -200 303588 _ (17) The invention explains the problem of stress on the sheet. Similarly, during bonding, it is controlled to the shape of the bumps of the embodiment, so it has the effect of reducing wafer damage during bonding. Figure 7 shows the LSI chip and Another embodiment of the bonding structure of an organic wiring substrate. In the figure, a metal thermal spray film 123 is formed on the aluminum electrode 121 of the LSI wafer 120 in a portion of the aluminum electrode 121, which is formed by a plating method. Gold bumps. The gold bumps are heat-treated after the plating step, and softened so that the Vickers hardness Hv is 80 or less. The dimensions of the top ends of the connection terminals of the wafer connection terminals 1 3 7 of the organic wiring substrate are designed to be smaller than the bumps. The size of the bottom surface of the block, and the bonding area on the terminal side after bonding, are formed to have a size of an area W2 or less of the bottom surface of the bump. Specifically, the length of the bump is 4 " mx, 15 μχη, the base portion of the connection terminal is 30 μm wide, the tip portion is 20 gm wide, and the height is 20 μm. The structure of the connection terminal is a nickel-phosphorus / gold or nickel-phosphorus palladium / gold-plated structure on a copper pattern, and the thickness of gold or palladium + gold is 005 ~ 〇.hm. In the present embodiment, because the lsi chip that forms gold-plated bumps is mounted on an organic wiring substrate by gold / gold metal bonding, the aluminum electrode is not exposed to the outer periphery, even if exposed to the corrosive environment of high temperature and high humidity. It is not affected by it ', so it can be mentioned that a highly reliable semiconductor device. In addition, because the bottom surface of the bump is as large as covering the passivation film, the configuration of the connection terminal contacting the center of the bump is formed. Therefore, it also has no stress concentration around the electrode and does not cause joint damage to the wafer, which can improve the assembly yield. . Most worrisome:, = deformation of bumps is not easy, can not absorb the uneven height of the substrate and the unevenness of the ore bumps, which leads to the loss of hard technology ^ Low full bumps are caused by heat treatment to reduce the hardness and % Small connection terminal size 'easy to squeeze into gold ore bumps' Finely absorb the unevenness in height by the local deformation of the gold bumps—you can avoid the problem of the -24- (18) (18) 200303588 invention description page. FIG. 8 shows another embodiment of the cross-sectional structure of the semiconductor device of the present invention. In the figure, a rewiring layer composed of an insulating film 142 having a thickness of 2 to 4 μm polyimide and a copper wiring 143 with an isolation film is formed on the circuit formation surface of the LSI wafer 140, and the top surface is formed of gold. Electrode terminal M # of the membrane. Gold electrode bumps 45 are formed on the electrode terminals by a ball bonding method. The organic wiring board is a printed circuit board with a wiring pitch of 200 μm, and nickel / gold plating is applied to the connection terminals. Solder bumps are formed on the external connection terminals on the back of the substrate. In addition, ⑥ the wafer / substrate is filled with a resin and solidified. / This embodiment is used for a fine-pitch LSI wafer to form an enlarged layer by rewiring, and is connected to an organic substrate with gold / gold metal bonding. Therefore, a general printed circuit board can be used for the organic wiring substrate. Reduce costs. In addition, since the stress at the time of bonding is transmitted to the wafer through the buffer of polyimide, wafer damage during the assembly step is not generated at all, and the yield can be greatly improved in accordance with the ease of alignment. In addition, due to the high heat resistance and reliability of the connection portion between the wafer and the substrate, there are almost no restrictions on the handling of the module mounted on the motherboard, and the ease of handling is excellent. [Effects of the invention] As detailed above, the present invention can provide an organic wiring board having a minimum wiring pitch of 100 μΐη or less, and an organic wiring board with a surface insulation layer having a low glass transition temperature. Below, the LSI chip with electrode pads above the pins "does not generate a substrate / wafer gap: offset |" and does not cause wafer damage "by gold / gold metal bonding to reliably flip-chip connect all pins Semiconductor manufacturing method. -25- (19) (19) 200303588 Description of the invention Bin page μ In addition, we can provide a high-reliability and low-resistance feature. Multi-pin and U fine-pitch LSI chips can be mounted on organic wiring substrates with fine wiring layers. 'Installation structure and installation process with high assembly yield and excellent productivity. Bu can provide an organic wiring substrate with a combination layer including a fine wiring layer and a low-glass transition temperature organic insulating layer on the surface layer. _ Hunted by flip-chip connection and equipped with electrode pads with more than 50 pins A semiconductor device with many pins, said chip, and excellent heat resistance, high temperature, high humidity, and temperature cycle reliability of the flip chip connection portion. [Brief Description of the Drawings] FIG. 1 is an embodiment of a cross-sectional structure of a semiconductor device of the present invention. FIG. 2 shows another embodiment of the cross-sectional structure of the semiconductor device of the present invention. FIG. 3 shows another embodiment of the cross-sectional structure of the semiconductor device of the present invention. FIG. 4 shows another embodiment of the cross-sectional structure of the semiconductor device of the present invention. FIG. 5 shows another embodiment of the cross-sectional structure of the semiconductor device of the present invention. Fig. 6 shows an example of a bonding structure between an LSI wafer and an organic wiring substrate according to the present invention. FIG. 7 shows another embodiment of a joint structure between an LSI wafer and an organic wiring board of the present invention. FIG. 8 shows another embodiment of the cross-sectional structure of the semiconductor device of the present invention. Fig. 9 is a definition and an example of fracture of a gold stretch when the joint is stretched and fractured. Fig. 10 is an example of the definition and fracture of the gold stretch when the joint is stretched and fractured. Fig. 11 is an example of the definition and fracture of the gold stretch when the joint is stretched and fractured. Fig. 12 Cross-sectional shape and fracture condition of the 2 series gold bump joint. FIG. 13 is an example of a cross-section of a junction between an 80-pitch LSI wafer and a combination substrate. (20) (20) 200303588 Description of the invention Continuing drawings Representative symbols description 1 ... Silicon substrate, 2 ... Circuit formation area, 3 ... Laminated insulation film, 4 ... Aluminum electrode pads, 5 ... Protective film, 6, 5 ' ·· Semiconductor wafer, 7,55,82… Gold bumps, 8… Glass epoxy insulation board, 9,85… Through holes, 1 ·· Wiring layer, 12, 35, 1 15 ··· Core substrate, 13, 22, 36, 37, 43 '44' 107 '108' 126 '128 ... insulation layer, 14 ... fine wiring layer, 15,24 ... communication hole, 16,25,59,92,113,135, 15〇 ... Photoresist film, 17 '27' 42, 49 ... Combined layer, 18, 38, 45 ... Fine wiring, 19, 26, 110 '131 ... Ni plating, 20, lu, 132 ··· Gold plating, 21 '39' 41 '46' 66 '90' 91, 133 '148 ... Connection terminals, 23, 67, 112, 134' 149 ... External connection terminals, 28, 50, 94, 114, 136 '152 ... solder bumps, 31, 146 ... organic insulating substrates, 32, 89, 147 ... through-hole wiring, 33, 34, 105, 106, 127, 129 • • Wiring, 40, 47, 48 ... communication hole wiring, 51, 60, 61, 80, 100, 120 '140 ... LSI wafer, 52, 62, 81, 101, 121, 141 ... Aluminum electrodes, 53, 63' 102, 122 ... Passivation film , 56 ... underfill resin, 57 ... passive parts, 58 ... soldering, 64, 103, 145 ... gold pillar bumps, 65 ... wiring boards, 68 ... mother boards, 69 ... WB connection terminals, 7 … Gold wire, 83 ··· insulation tape, 84 ... wiring connection terminal, 86 ·· adhesive, 87 · 51 · •• resin, 88 ... glass epoxy substrate, 93 ... printed substrate, 95 ... with substrate, 104 ， 125 ··· Organic insulation board, 109,130 ... Copper pattern, 123 ... Metal forging film, 124 ... Gold-plated bump, 142 ... Insulation film, 143 ... Copper wiring, 144 ... . -27-

Claims (1)

200303588 拾、申請專利範圍 L一種半導體裝置，其且右· 邱八v古4 u 、 ·夕層配線基板，其係至少一 有機材料構成；形成有電子電路之半導體曰片. 及有機樹脂，A係掠Λ A + 丁电塔之牛V體曰曰片， 、’、月述半導體晶片與前述多層配線 基板之間；其特糌盔· A _ ^ a ^ ^ τ ^ ^ ' 、、'刖述多層配線基板上之晶片連接 祐：：：'! 部分構成構件係以具有15〇。。以下之 玻璃轉移溫度的有機好 嘴材枓構成，晶片連接用端子之最小 間距在100 μηι以下，曰y、由从… B曰片連接用端子之表面金屬係由鎳-%/金或錄-礙/!巴/金之鐘層構成，且金及把/金之貴重金 屬部之總厚度為㈣5⑷陶，半導體晶片之電極端子 上形成有金凸塊’基板上之前述金連接端子與晶片之前 述金凸塊以金屬接合連接。 2·如申請專利範圍第丨項之半導體裝置，#中前述多層配 線基板包含：核心基板，其係以具有單面或兩面配線圖 案之印刷配線基板構成；及丨層以上之組合層，其係具 有：於前述核心基板上塗敷液狀樹脂使其硬化或貼附膜 狀樹脂而形成之有機絕緣層；於前述有機絕緣層上形成 有比核心基板微細，最小配線間距在丨〇〇 以下之銅配 線之微細配線層；及連接上層微細配線與下層配線之連 通孔連接部。 3·如申請專利範圍第1或2項之半導體裝置，其中形成金凸 塊/金連接端子係藉由呈現金之延展斷裂之金屬接合倒裝 片連接’於晶片/基板間填充有含無機絕緣填料之樹脂， 基板之外部連接端子以焊接凸塊所構成之構造。 200303588 申請專利範圍續頁 4.如申請：利範圍第2項之半導體裝置，纟中前述核心基 板上之前述有機絕緣層係以玻璃轉移溫度Tg: 150。(：以 有機树知構成，微細配線銅圖案之至少一部分 由電鍍形成。 μ曰 5·如申料利範圍第2項之半導體m中前述核心基 ，上之料有機絕緣層與前述微細配線層係接著聚醯亞 月女帶基板而形成。 6·種半導體褒置，其具有：多層配線基板，其係至少一 部分以有機材料構成；形成有電子電路之半導體晶片； =有機树月日，其係埋人前述半導體晶片與前述多層配線 ^反之間’其特徵為：金屬接合前述多層配線基板上之 金連接端子與前述半導體晶片上之金凸塊，金凸塊之社 晶組織形成於晶片側較粗，於基板側向端子面方向一致 扁平形狀且微細的組織。 7·=半導體裝置’其特徵為包含：組合基板，其係於具 、孔與兩面配線圖案之有機配線基板的兩面，形成由 ^機絕緣層、銅鐘配線、與連通孔構成之卜4層的組合 於與半導體晶片連接之端子面上實施金厚度為0.005 二μιη之無電解鎳/金或無電解鎳/鈀/金鍍；及 :導體晶片，其係於具有接腳數5〇個以上之裸晶片之 電極或設於晶片表面之再配線層上之連 成金凸塊； t具有金凸塊與金鑛面以金/金之金屬接合進行倒裝片 ’基板與晶片間之間係以含無機絕緣填料之樹脂填 200303588 200303588 申請專利範圍續頁 充，於組合基板之底面之外部連接端子上藉由平坦化熱 處理形成有焊接凸塊之構造。 8·種半‘體裝置，其具有··多層配線基板，其係至少一 P刀乂有钱材料構成，·形成有電子電路之半導體晶片； 及有機树知，其係埋入晶片與基板之間，·其特徵為··前 述多層配線基板上之晶片連接端子之最表面金屬係以金 之鍍層構成’岫述半導體晶片之電極端子面上形成貴重 金屬柱形凸塊’前述晶片連接端子上之金鐘層與前述貴 重金屬凸塊以金屬接合連接，晶片電極/凸塊間之密著面 積Sc與凸塊/基板側連接端子間之密著面積⑶之比认仏 在1/2以下。 9.-種半導體褒置，其係半導體晶片以各貴重金屬之固態 金屬接合之倒裝片連接安裝於配線基板上，其特徵為^ .具有配線基板上之半導體晶片之連接端子之表面金屬由 鎳/金或綠/金之鑛層構成，且金及把/金之貴重金屬部 之總厚度為G.005〜〇·3陣，半導體晶片以⑦基板上之帝 子電路形成區域與電極料區域構成，其表面夾著厚: 在2 μιη以上之有機絕緣層而形成再配線層，與電極谭塾 電性連線之再配線層之連接焊塾以總厚度在2师以上之 銅/隔離金屬/金之多層金屬構造構成’該連接焊塾上形 成金凸塊’金凸塊與金鍍面以金/金之金屬接合倒裝片連 =’且基板與晶片間之_:以含無機絕緣填料之樹 充’配線基板之底面之外部連接端子上藉處 理形成有焊接凸塊之構造。 k、、、處 200303588 申請專利範圍績頁 10.-種半導體裝置，其係半導體晶片以各貴重金屬之固態 孟屬接合之倒裝片連接安裝於配線基板上，其特徵為： 具有配線基板上之晶片連接端子之表面金屬由鎳/金或鎖 A金之鍍層構成，且金及紅/金之貴重金屬部之總厚度 二帝05 〇·3 μιη，半導體晶片以矽基板上之銅配線之電 子包路形成(1域與銅電極料區域構成，銅電極焊塾最 表面經由隔離層而實施金或鋁金屬噴鍍處理，進一步於 -、^成有孟柱形凸塊或金鍍凸塊，金凸塊與金鍍面以 金/金之金屬接合倒裝片連接，且基板與晶片間之間隙以 含無機絕緣填料之_填充，配線基板之底面之外部連 接端子上形成有焊接凸塊之構造。 1 !·種半導體裝置之製造方法，其特徵為具有··物理性濺 =蝕刻步驟，其係於配線基板之金鍍連接端子與形成於 曰曰片上之金凸塊之倒裝片連接中，藉由平行平板電極間 產生之減壓下之氬放電氣體物理性濺射蝕刻配線基板之 金連接端子表面至金膜厚之1/1〇以上或1〇細以上，且僅 金膜厚之1/2以下厚度；與基板側同樣地濺射蝕刻晶片上 之金凸塊表面僅數〜數十nm厚度；對準步驟，其係使基 板與晶片相對；加熱步驟，其係將晶片側加熱成自室溫 至15(TC之範圍的溫度：Tc，將基板侧加熱成室溫〜基板 之玻璃轉移溫度Tg以下之溫度Tb;金/金之金屬接合步 驟其係以超音波接合方法進行，該超音波接合方法包 含於超音波加振中使施加於晶片之負載增加的步驟；填 充步驟，其係於基板與晶片之間填充樹脂；使填充之樹 200303588 申請專利範圍，镝g ^ 脂加熱硬化步驟；及於基板之外部連接端子上形成焊 凸塊步驟。 12·如申請專利範圍第u項之半導體裝置之製造方法，其中 於濺射蝕刻晶片與配線基板兩者後，，藉由超音波倒裝片 接合前之空氣釋放時間為1 〇分鐘以内。 1 3 ·如申請專利範圍第丨丨項之半導體裝置之製造方法，其中 將超音波接合時之基板溫度設定為室溫，將晶片溫度設 定為室溫〜15〇°C ° 14 ·如申請專利範園第11項之半導體裝置之製造方法，其中 將超音波接合時之基板溫度及晶片溫度設定為室溫。200303588 Patent application scope L A semiconductor device, and its right · Qiu Ba v Gu 4 u · · Xi layer wiring substrate, which is composed of at least one organic material; a semiconductor chip formed with electronic circuits; and organic resin, A It is a piece of Λ A + ding dynasty's bull V body, which is between the semiconductor wafer and the multilayer wiring substrate; its special helmet · A _ ^ a ^ ^ τ ^ ^ ',,' 、 The wafer connection on the multilayer wiring board is described as follows: :: '! Some of the constituent members are provided with 150. . The following glass transition temperature is composed of organic good mouth material, the minimum distance between the wafer connection terminals is less than 100 μηι, said y, from ... B said the surface of the terminal connection metal is nickel-% / gold or recorded- The structure of the bell layer of / bar / gold, and the total thickness of gold and precious metal parts of 金 / ⑷ is ㈣5⑷. The electrode terminals of the semiconductor wafer are formed with gold bumps. The gold bumps are connected by metal bonding. 2 · As for the semiconductor device in the scope of application for item 丨, the aforementioned multilayer wiring substrate in # includes: a core substrate, which is composed of a printed wiring substrate having a single-sided or double-sided wiring pattern; and a combined layer of more than one layer, which is It has: an organic insulating layer formed by coating a liquid resin on the core substrate to harden or attach a film-like resin; and forming a copper finer than the core substrate on the organic insulating layer and having a minimum wiring pitch of less than or equal to A fine wiring layer for wiring; and a connection hole connecting part for connecting the upper fine wiring and the lower wiring. 3. If the semiconductor device in the scope of patent application No. 1 or 2, the formation of gold bumps / gold connection terminals is connected by a metal bonding flip-chip that shows the extensional fracture of gold. The wafer / substrate is filled with inorganic insulation. The filler resin and the external connection terminals of the substrate are constructed by solder bumps. 200303588 Application for Patent Range Continued 4. If applying: For the semiconductor device of the second benefit range, the aforementioned organic insulation layer on the aforementioned core substrate is based on glass transition temperature Tg: 150. (: It is composed of an organic tree, and at least a part of the fine wiring copper pattern is formed by electroplating. Μ 曰 5 · As in the semiconductor core m in the second item of the material range, the above-mentioned organic insulating layer and the aforementioned fine wiring layer It is formed by gathering a polysilicon female substrate. 6. A semiconductor device having: a multilayer wiring substrate composed of at least a part of an organic material; a semiconductor wafer formed with an electronic circuit; It is buried between the aforementioned semiconductor wafer and the aforementioned multilayer wiring, and is characterized in that the gold connection terminals on the aforementioned multilayer wiring substrate and the gold bumps on the aforementioned semiconductor wafer are metal-bonded, and the crystal structure of the gold bumps is formed on the wafer side. It is relatively thick and has a flat and fine structure consistent with the substrate surface toward the terminal surface. 7 · = Semiconductor device 'is characterized in that it includes a combination substrate, which is formed on both sides of an organic wiring substrate with holes, holes, and two-sided wiring patterns. A combination of 4 layers consisting of a metal insulating layer, copper bell wiring, and communication holes is implemented with a gold thickness on the terminal surface connected to the semiconductor wafer. 0.005 electroless nickel / gold or electroless nickel / palladium / gold plating of two μιη; and: a conductive wafer, which is an electrode with a bare wafer having more than 50 pins or a redistribution layer provided on the surface of the wafer The gold bumps are connected; t the gold bumps and the gold ore surface are bonded with gold / gold metal for flip-chips. The substrate and the wafer are filled with a resin containing an inorganic insulating filler 200303588 200303588 A structure in which solder bumps are formed on the external connection terminals on the bottom surface of the combined substrate by a flattening heat treatment. 8. A half-body device having a multi-layer wiring substrate, which is at least one P-knife rich material Structure: · Semiconductor wafer on which electronic circuits are formed; and · Organic tree known that it is buried between the wafer and the substrate; · Characterized in that: · The topmost metal of the wafer connection terminals on the multilayer wiring board is a gold-plated layer A precious metal columnar bump is formed on the electrode terminal surface of the above-mentioned semiconductor wafer. The golden bell layer on the wafer connection terminal and the precious metal bump are connected by metal bonding. The ratio of the adhesion area Sc between the poles / bumps to the adhesion area ⑶ between the bumps / substrate-side connection terminals is considered to be less than 1/2. 9. A semiconductor device, which is a semiconductor wafer with various precious metals The solid-state metal-bonded flip-chip connection is mounted on a wiring substrate, which is characterized by ^. The surface metal of the connection terminal with the semiconductor wafer on the wiring substrate is composed of a nickel / gold or green / gold mineral layer, and the gold and the / The total thickness of the gold precious metal part is G.005 ~ 0.3 array. The semiconductor wafer is composed of the emperor circuit formation area and electrode material area on the substrate, and the surface is sandwiched by a thick: organic insulation above 2 μιη Layer to form a redistribution layer, and the connection pads of the redistribution layer that are electrically connected to the electrodes Tan, are composed of a multilayer metal structure of copper / isolated metal / gold with a total thickness of 2 divisions or more. Bump 'Gold bump and gold-plated surface are bonded with gold / gold metal flip-chip connection =' and between the substrate and the wafer _: filled with a tree containing an inorganic insulating filler 'external connection terminals on the bottom surface of the wiring substrate Processing of structures with solder bumpsk ,,,,,,,,,,, and 200303588 Patent Application Scope Page 10.- A semiconductor device, which is a semiconductor wafer mounted on a wiring substrate by a flip-chip connection of solid precious metal bonding of various precious metals, which is characterized by: The surface metal of the chip connection terminal is composed of nickel / gold or lock A gold plating, and the total thickness of the precious metal portion of gold and red / gold is 2.5. 3 μm. The semiconductor chip is wired with copper on a silicon substrate. Electronic envelope formation (1 domain and copper electrode material area formation, the copper electrode welding pads are subjected to gold or aluminum metal spray plating treatment through the isolation layer, and furthermore, there are Meng pillar bumps or gold plating bumps. The gold bump and the gold-plated surface are connected by a gold / gold metal bonding flip chip, and the gap between the substrate and the wafer is filled with _ containing an inorganic insulating filler. A solder bump is formed on the external connection terminal on the bottom surface of the wiring substrate. A structure for manufacturing a semiconductor device, which is characterized by having a physical sputtering = etching step, which is a flip-chip mounting of a gold-plated connection terminal on a wiring substrate and a gold bump formed on a chip. During the connection, the surface of the gold connection terminal of the wiring substrate was etched to a thickness of 1/1 or more or 10 or more thinner with a gold film by argon discharge gas under a reduced pressure generated between the parallel plate electrodes, and only the gold film was used. The thickness is less than 1/2 of the thickness; the thickness of the gold bump surface on the wafer is sputter-etched just like the substrate side, and the thickness is only a few to several tens of nm; the alignment step is to make the substrate face the wafer; the heating step is to make the wafer The side is heated to a temperature ranging from room temperature to 15 (TC: Tc, the substrate side is heated to a temperature Tb below the glass transition temperature Tg of the substrate; the gold / gold metal bonding step is performed by an ultrasonic bonding method The ultrasonic bonding method includes a step of increasing the load applied to the wafer during ultrasonic vibration; a filling step, which is filled with resin between the substrate and the wafer; the filling tree 200303588 applies for a patent, 专利 g ^ grease Step of heating and hardening; and step of forming solder bumps on the external connection terminals of the substrate. 12. A method for manufacturing a semiconductor device such as the item u of the patent application, wherein the wafer and the wiring substrate are etched by sputtering. After both, the air release time before bonding by the ultrasonic flip chip is less than 10 minutes. 1 3 · As in the method for manufacturing a semiconductor device according to item 丨 丨 of the patent application, in which the substrate when the ultrasonic bonding is performed The temperature is set to room temperature, and the wafer temperature is set to room temperature to 15 ° C ° 14 · As in the method for manufacturing a semiconductor device according to item 11 of the patent application, the substrate temperature and the wafer temperature during ultrasonic bonding are set to Room temperature.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI458052B (en) * 2007-05-30 2014-10-21 Shinko Electric Ind Co Wiring board and its fabricating method

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6889429B2 (en) * 2001-03-26 2005-05-10 Semiconductor Components Industries, L.L.C. Method of making a lead-free integrated circuit package
JP3891838B2 (en) * 2001-12-26 2007-03-14 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
US7505862B2 (en) * 2003-03-07 2009-03-17 Salmon Technologies, Llc Apparatus and method for testing electronic systems
JP4170137B2 (en) * 2003-04-24 2008-10-22 新光電気工業株式会社 Wiring board and electronic component mounting structure
TWI245381B (en) * 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof
US7408258B2 (en) * 2003-08-20 2008-08-05 Salmon Technologies, Llc Interconnection circuit and electronic module utilizing same
US7239023B2 (en) * 2003-09-24 2007-07-03 Tai-Saw Technology Co., Ltd. Package assembly for electronic device
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
KR101237172B1 (en) 2003-11-10 2013-02-25 스태츠 칩팩, 엘티디. Bump-on-lead flip chip interconnection
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
JP4507582B2 (en) * 2003-12-12 2010-07-21 パナソニック株式会社 Mounting method of electronic components with bumps
US20050184376A1 (en) * 2004-02-19 2005-08-25 Salmon Peter C. System in package
US20050186690A1 (en) * 2004-02-25 2005-08-25 Megic Corporation Method for improving semiconductor wafer test accuracy
US7064963B2 (en) * 2004-04-01 2006-06-20 Delphi Technologies, Inc. Multi-substrate circuit assembly
US7659148B2 (en) 2004-04-08 2010-02-09 Panasonic Corporation Bonding method and apparatus
US20050255722A1 (en) * 2004-05-07 2005-11-17 Salmon Peter C Micro blade assembly
US7393771B2 (en) * 2004-06-29 2008-07-01 Hitachi, Ltd. Method for mounting an electronic part on a substrate using a liquid containing metal particles
DE102004032706A1 (en) 2004-07-06 2006-02-02 Epcos Ag Method for producing an electrical component and the component
DE102004040414B4 (en) * 2004-08-19 2006-08-31 Infineon Technologies Ag A method of manufacturing a wiring substrate of a semiconductor device having external contact pads for external contacts
US7812441B2 (en) 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
TWI278090B (en) * 2004-10-21 2007-04-01 Int Rectifier Corp Solderable top metal for SiC device
US7427809B2 (en) * 2004-12-16 2008-09-23 Salmon Technologies, Llc Repairable three-dimensional semiconductor subsystem
US20070007983A1 (en) * 2005-01-06 2007-01-11 Salmon Peter C Semiconductor wafer tester
US7834376B2 (en) 2005-03-04 2010-11-16 Siliconix Technology C. V. Power semiconductor switch
US9419092B2 (en) 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
WO2006105015A2 (en) 2005-03-25 2006-10-05 Stats Chippac Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8841779B2 (en) * 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
JP2006278913A (en) * 2005-03-30 2006-10-12 Toyota Motor Corp Circuit device and manufacturing method therefor
US7538389B2 (en) * 2005-06-08 2009-05-26 Micron Technology, Inc. Capacitorless DRAM on bulk silicon
US20070023889A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Copper substrate with feedthroughs and interconnection circuits
US20070023923A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Flip chip interface including a mixed array of heat bumps and signal bumps
US7586747B2 (en) 2005-08-01 2009-09-08 Salmon Technologies, Llc. Scalable subsystem architecture having integrated cooling channels
US20070023904A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Electro-optic interconnection apparatus and method
US8368165B2 (en) 2005-10-20 2013-02-05 Siliconix Technology C. V. Silicon carbide Schottky diode
TWI311451B (en) * 2005-11-30 2009-06-21 Murata Manufacturing Co Ceramic substrate, electronic device, and manufacturing method of ceramic substrate
JP4638382B2 (en) * 2006-06-05 2011-02-23 田中貴金属工業株式会社 Joining method
EP2047514A4 (en) 2006-07-31 2010-12-01 Vishay Siliconix Molybdenum barrier metal for sic schottky diode and process of manufacture
KR20080042012A (en) * 2006-11-08 2008-05-14 산요덴키가부시키가이샤 Substrate for mounting device, manufacturing method thereof, semiconductor module and portable equipment
US7595553B2 (en) * 2006-11-08 2009-09-29 Sanyo Electric Co., Ltd. Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus
US7659192B2 (en) * 2006-12-29 2010-02-09 Intel Corporation Methods of forming stepped bumps and structures formed thereby
US9084377B2 (en) * 2007-03-30 2015-07-14 Stats Chippac Ltd. Integrated circuit package system with mounting features for clearance
SG148056A1 (en) 2007-05-17 2008-12-31 Micron Technology Inc Integrated circuit packages, methods of forming integrated circuit packages, and methods of assembling intgrated circuit packages
JP2009081366A (en) * 2007-09-27 2009-04-16 Elpida Memory Inc Batch processing apparatus
JP4431606B2 (en) * 2007-10-05 2010-03-17 シャープ株式会社 Semiconductor device, semiconductor device mounting method, and semiconductor device mounting structure
JP2009224492A (en) * 2008-03-14 2009-10-01 Oki Semiconductor Co Ltd Semiconductor device and method of manufacturing the same
JP5366674B2 (en) * 2008-06-27 2013-12-11 パナソニック株式会社 Mounting structure and mounting method
TW201011878A (en) * 2008-09-03 2010-03-16 Phoenix Prec Technology Corp Package structure having substrate and fabrication thereof
JP5101451B2 (en) 2008-10-03 2012-12-19 新光電気工業株式会社 Wiring board and manufacturing method thereof
CN101728289B (en) * 2008-10-10 2011-12-28 哈尔滨工业大学深圳研究生院 Room temperature ultrasonic soldering method for area array encapsulated electronic components
JP2010171386A (en) * 2008-12-26 2010-08-05 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP2010161136A (en) * 2009-01-07 2010-07-22 Panasonic Corp Semiconductor device and method of manufacturing the same
CN102282659B (en) * 2009-02-04 2013-11-20 松下电器产业株式会社 Semiconductor substrate structure and semiconductor device
US8410374B2 (en) 2009-02-27 2013-04-02 Ibiden Co., Ltd. Printed wiring board
US8461462B2 (en) * 2009-09-28 2013-06-11 Kyocera Corporation Circuit substrate, laminated board and laminated sheet
US8476757B2 (en) * 2009-10-02 2013-07-02 Northrop Grumman Systems Corporation Flip chip interconnect method and design for GaAs MMIC applications
US20110227216A1 (en) * 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
JP4823375B1 (en) * 2010-05-28 2011-11-24 株式会社東芝 Electronics
JP5229296B2 (en) * 2010-10-14 2013-07-03 日本テキサス・インスツルメンツ株式会社 Mounting electronic components on IC chips
KR20130007124A (en) 2011-06-29 2013-01-18 삼성전자주식회사 Joint structure having an organic preservative film
CN102244061A (en) * 2011-07-18 2011-11-16 江阴长电先进封装有限公司 Low-k chip package structure
US20130044448A1 (en) * 2011-08-18 2013-02-21 Biotronik Se & Co. Kg Method for Mounting a Component to an Electric Circuit Board, Electric Circuit Board and Electric Circuit Board Arrangement
JP2013235882A (en) * 2012-05-07 2013-11-21 Mitsubishi Electric Corp Semiconductor device
JP5832956B2 (en) 2012-05-25 2015-12-16 株式会社東芝 Semiconductor light emitting device
TWI451826B (en) * 2012-05-28 2014-09-01 Zhen Ding Technology Co Ltd Multilayer printed circuit board and method for manufacturing same
JP5869961B2 (en) 2012-05-28 2016-02-24 株式会社東芝 Semiconductor light emitting device
CN103458629B (en) * 2012-05-30 2016-12-21 碁鼎科技秦皇岛有限公司 Multilayer circuit board and preparation method thereof
US9269681B2 (en) * 2012-11-16 2016-02-23 Qualcomm Incorporated Surface finish on trace for a thermal compression flip chip (TCFC)
KR101284363B1 (en) * 2013-01-03 2013-07-08 덕산하이메탈(주) Metal core solder ball and heat dissipation structure of semiconductor device using the same
US8896118B2 (en) * 2013-03-13 2014-11-25 Texas Instruments Incorporated Electronic assembly with copper pillar attach substrate
JP5763116B2 (en) * 2013-03-25 2015-08-12 株式会社東芝 Manufacturing method of semiconductor device
KR20150002492A (en) * 2013-06-28 2015-01-07 쿄세라 서킷 솔루션즈 가부시키가이샤 Wiring substrate
KR101673649B1 (en) * 2013-07-16 2016-11-08 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US20150097268A1 (en) * 2013-10-07 2015-04-09 Xintec Inc. Inductor structure and manufacturing method thereof
US20150115442A1 (en) * 2013-10-31 2015-04-30 Infineon Technologies Ag Redistribution layer and method of forming a redistribution layer
TWI576869B (en) * 2014-01-24 2017-04-01 精材科技股份有限公司 Passive component structure and manufacturing method thereof
CN104409434A (en) * 2014-08-28 2015-03-11 南通富士通微电子股份有限公司 Package structure of semiconductor device
JP6623508B2 (en) 2014-09-30 2019-12-25 日亜化学工業株式会社 Light source, method of manufacturing and mounting method
KR102248876B1 (en) * 2014-12-24 2021-05-07 엘지디스플레이 주식회사 Array substrate for display device and displya device
KR101518760B1 (en) * 2014-12-31 2015-05-08 주식회사 자이스 Attaching method for chip using conductive adhesive
JP7002134B2 (en) * 2016-08-29 2022-01-25 国立大学法人東北大学 Magnetic tunnel junction element and its manufacturing method
US10923449B2 (en) 2016-10-06 2021-02-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US11069606B2 (en) 2016-10-06 2021-07-20 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US10103095B2 (en) * 2016-10-06 2018-10-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
CN106847936B (en) * 2016-12-07 2019-01-01 清华大学 Packaging of photoelectric device structure and its manufacturing method based on metal bonding
JP7012489B2 (en) * 2017-09-11 2022-01-28 ローム株式会社 Semiconductor device
JP7189672B2 (en) * 2018-04-18 2022-12-14 新光電気工業株式会社 Semiconductor device and its manufacturing method
KR20200116577A (en) 2019-04-01 2020-10-13 삼성디스플레이 주식회사 Display device and method for manufacturing the same
KR20220022302A (en) 2020-08-18 2022-02-25 삼성전자주식회사 A semiconductor package and a method for manufacturing of the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3252745B2 (en) * 1997-03-31 2002-02-04 関西日本電気株式会社 Semiconductor device and manufacturing method thereof
US20030001286A1 (en) * 2000-01-28 2003-01-02 Ryoichi Kajiwara Semiconductor package and flip chip bonding method therein
JP3891838B2 (en) * 2001-12-26 2007-03-14 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI458052B (en) * 2007-05-30 2014-10-21 Shinko Electric Ind Co Wiring board and its fabricating method

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