SU888202A1 - Buffer storage - Google Patents

Description

The invention relates to techniques for constructing buffer memory devices (BZU) and may find application in data transmission equipment used in an automatic telegraph communication system.

Known buffer storage device [1], containing drives, the number of which is equal to the number of message sources (subscriber lines), switching device polling drives, information buses, polling and recording buses.

Information from message sources is pre-accumulated in the drives, and then, by alternately polling the drives, it is output to the transmitter input. The disadvantage of this device is the inefficient use of the total capacity of the drives, each of which is designed to store information only one of any message source.

The closest in technical essence to the invention is a buffer memory device {2J, containing the main drive, intermediate drives, the first and second group of AND elements, the third group of AND elements, encoder, decoder, fill analyzers, OR-NOT element, input buses, recording buses , a polling bus, a bus for reading information from intermediate drives, an output bus.

In the known device, information from sources is recorded in a common for all the main drive, while the information belongs to that. or other source is encrypted and in the form of an additional code is recorded in the control bits of the main drive. Before information is output to the output bus of the device, it is read into intermediate storage devices, each of which is designed to store information only on one888202

quite a certain source. Intermediate drives have a small capacity corresponding to the number of characters that make up the standard group selected for this device to be transferred. The advantages of this device are the efficient use of storage capacity, simplification of the device and increasing its reliability.

A disadvantage of the known device is that when filling one of the intermediate drives, the interrogation of the main drive stops, which reduces the speed of output of information from the main drive and ultimately delays the delivery of information to the recipient.

The aim of the invention is to improve the performance of the device.

This goal is achieved by the fact that in the buffer storage device containing the drive, the information inputs of which are connected to the outputs of the elements of the first group, the first control input to the outputs of the encoder, the address inputs to the outputs of the address block, and the control input of the drive is connected to the output the first element And, the information outputs of the drive are connected to the first inputs of the elements And of the second group, and the first control output of the drive is connected to the input of the decoder, the outputs of which are connected to the second inputs respectively of the corresponding elements And the second group, a group of additional drives, the inputs of each of which are connected to the outputs of the corresponding elements And the second group, the control output to the input of the corresponding driver of the overflow signal, and the outputs of the group of additional drives are the information outputs of the device, the elements And of the third group are additionally introduced, the first the inputs of each of which are connected to the output of the corresponding shaper of the overflow signal, and the second inputs to the corresponding outputs of the decoder a torus, a group of elements NOT, the inputs of each of which are connected to the output of the corresponding driver of the overflow signal, and the output to the third inputs of the corresponding elements of the second group, the OR element, whose inputs are connected to the outputs of the elements of the third group, and the output to the second control input drive, an equivalence element, the first input of which is connected to the second control output of the drive, and their output - to the fourth 5 inputs of the elements AND of the second group, an additional drive, the information outputs of which I connect the inputs to the address block, AND elements of the fourth group, the first inputs of which are connected to the outputs of the address block, the second inputs to the output of the OR element, the NOT element, whose input is connected to the control output of the additional drive, and the output 15 to the third inputs of the AND elements of the fourth groups, the shaper of the end of the address, the inputs of which are connected to the outputs of the address block, and the output to the second input of the additional storage device · 20, and the trigger, the input of which is connected to the output of the shaper of the end of the address, and the output to the second input of the element p vnoznachnosti.

The drawing shows a diagram of the proposed device.

The device contains a drive 1, a group of additional drives 2, AND elements of the first group 3, AND elements of the second group 4, AND element 5, encoder 20 tor 6, decoder 7, overflow signal generator 8, AND-NOT element 9, input buses 10 onto which receives information from the message source, the bus 11, write enable bus 12 polling storage, spikes 13, koto ³⁵ rye receives signals permit reading of the intermediate storage, the output bus 14, which receives information from the group of additional drives address ⁴⁰ the block 15 which in accordance with receipt · at its counting input a clock signal generates the address code supplied to the address inputs of drive 1.

⁴⁵ The device consists of AND elements of the third 16 and fourth 17 groups, a group of elements NOT 18, an element NOT 19. An element NOT 20, a driver 21 of the end of the address, an additional drive ⁵⁰ , a trigger 22, a trigger 23, and an equivalence element 24.

The proposed device operates as follows.

Information from message sources 55, for example, telegraphy devices, is transmitted to the buses 10 and then, according to the recording permission signals arriving alternately to the buses 11, is written to the drive 1. At the same time, a binary code is written to the control bits of the drive 1 from the encoder output at the same address, at to which information from the source is recorded. Thus, the drive 1 contains information coming from the source with notes on whether this information belongs to one or another .. source.

When reading information from drive 1, the binary code contained in the 'control bits at the address being polled arrives at the inputs of the decoder 7 and is converted to a positional code that ensures the selection of the element And of the second group 4. This ensures that the information read from drive 1 is transmitted to drives 2 2. Drives 2 are sequentially interrogated by read permission signals arriving alternately on buses 13. If there is information in the intermediate drive, it is output to bus 14. Filling out the intermediate s drive controlled formers 8, whose outputs are connected to inputs of AND - NOT 9. When filling the storage tank 2 at the output of AND-NO element 9 is formed by a signal prohibiting polling signals flow via bus 12 to the input interrogation main storage 5 via the AND gate.

When filling one or more additional drives 2, but not all, the survey of the main drive continues. In this case, the signal about filling from the output of block 8 associated with the filled drive 2 pos-. · Dulls through the element NOT 18 to one of the inputs of the second group of the element AND of the second group 4 and prevents the information read from the drive 1 to the input of the filled intermediate drive.

Drive full alarm 2. the output of the shaper 8 is delayed by the polling cycle of the drive 1, as a result of which this signal is fed to the input of the And 16 element following the filling cycle of the access cycle to this drive 2, at which the information received from its drive 1 is not recorded. The signal about filling from the output of the element And 16 through the element. OR 20 goes to one of the inputs of the elements AND 17 of the fourth group to

888202 4 and to the additional control input of drive 1.

If the drive 22 is free, a signal is received at the input of the And 17 elements, allowing the address code to be written from block 15 to the drive 22. Thus, the drive 22 will contain the address code of the drive 1 cell, information from which was not read into the drive 2 due to its filling . When writing the address code to the drive 22 to the input of AND elements 17 through the element NOT 19, a signal is issued that prohibits writing to the drive 22.

The fill signal writes 1 to the additional control bit of drive 1 at the address of the cell that contains information not read into drive 2.

At the end of the cycle of polling the memory cells of the drive 1, the driver 21 generates a signal that polls the drive 22, records the code of the block 15 contained in it, and sets the trigger 23 to a • state, as a result of which the drive is not polled from the starting address of the cell whose information was not accepted by intermediate drive 2 in the previous cycle. Due to this, the time for outputting information from the drive 1 to the output of the device is reduced.

When the drive 1 is polled again, only the information contained in the memory cells is passed to the input of the drives 2. In the memory cells, the additional control bit of which is written 1. This is ensured by the fact that the fourth inputs of the AND 4 elements receive the permission signal from the output of the Element 24, since the output of the additional control discharge drive 1 and the output of the trigger 23 to both inputs of it comes 1.

After the interrogation, the drive 22 is freed up, as a result of which a signal is received at the input of the And 17 elements through the ele-

the unit of this after1 begins with the address

The operation of the proposed device is considered under the condition that the survey of memory cells of the drive 1 is carried out without destroying the information contained in it. Such drives are currently in use due to the development of integrated semiconductor.

technology is most prevalent.

When using a storage device in the proposed device, in which interrogation of memory cells available (not shown in the drawing).

The advantage of the proposed device compared to the known ones is to increase the speed of information output from the main drive and its delivery to the consumer. In known devices, the output of information stops as soon as one of the intermediate drives is full. In the proposed device, the survey of the main drive in such cases continues. In this case, information related to unoccupied intermediate drives is read from the main drive and then, after grouping, is output to the device. Information related to a busy intermediate drive is stored in the main drive, and an increase in the speed of its output is achieved by the fact that after the polling cycle of the main drive is completed, it is again polled from the address of the cell whose information was not received by the occupied intermediate drive.

Claims (2)

The invention relates to a technique for constructing buffer storage devices (RAMs) and may find application in data transmission equipment used in an automatic telegraph communication system. A buffer storage device tl is known, containing accumulators, the number of which is equal to the number of sources of messages (subscriber lines), switching devices for polling accumulators, information buses, polling and recording buses. Information from the sources of the messages is preliminarily accumulated in the accumulators, and then, by alternately polling the accumulators, is output to the transmitter input. The disadvantage of such a device is the inefficient use of the total capacity of the drives, each of which is intended to store information from just one of the message sources. The closest in technical essence to the invention is a buffer storage device 2 containing the main drive, intermediate drives, the first and second group of elements AND, the third group of elements AND, encoder, decoder, filling analyzers, element OR NOT, input buses, write buses , polling bus, bus reading information from intermediate drives, output bus. in a known device, information from sources is recorded in a common primary drive for all, while the information belonging to one or another source is encrypted and in the form of an additional code is recorded in check bits of the main accumulator. Before outputting information to the output bus of the device, it is read into intermediate drives, each of which is intended to store information from only one specific source. Intermediate drives have a small capacity corresponding to the number of characters that make up the standard group selected for this device to be transferred. The advantages of this device are efficient use of storage capacity, simplifying the device and increasing its reliability. A disadvantage of the known device is that when filling in one of the intermediate drives, polling of the main drive stops, which reduces the speed of information output from the main drive and ultimately delays the delivery of information to the recipient. The aim of the invention is to increase the speed of the device. The goal is achieved by the fact that the buffer memory device containing the drive, informational inputs of which are connected to the outputs of elements AND of the first group, the first control input to the outputs, the encoder, address inputs to the outputs of the address block, and the control input of the storage device connected to the output the first element And, the information outputs of the accumulator are connected to the first inputs of the elements And the second group, and the first control output of the accumulator is connected to the input of the decoder, the outputs of which are connected to the second inputs from corresponding elements AND of the second group, a group of additional drives, the inputs of each of which are connected to the outputs of the corresponding elements AND the second group, controlling the output to the input of the corresponding overflow signal generator, and the outputs of the group of additional drives are informational outputs of the device; And the third group, the first inputs of each of which are connected to the output of the corresponding overflow signal generator, and the second inputs - to the corresponding outputs g of the encoder, a group of elements NOT, the inputs of each of which are connected to the output of the corresponding overflow signal generator, and the output to the third inputs of the corresponding elements AND of the second group, the OR element whose inputs are connected to the outputs of the AND elements of the third group, and the output to to the second console of the accumulator 24, the element of equivalence, the first input of which is connected to the SECOND control output of the accumulator, and their output - to quarter 1m. the inputs of elements AND of the second group, an additional drive, whose information outputs are connected to the inputs of the address block, elements of the fourth group, the first inputs of which are connected to the outputs of the address block, the second inputs - to the output of the element OR, the element NOT whose input is connected to the control output additional storage device, and the output to the third inputs of the elements of the fourth group, the driver of the end of the address, the inputs of which are connected to the outputs of the address block, and the output to the second input of the additional storage device, and the trigger Whose input is connected to the output of the end address, and an output - to a second input of the equivalence element. The drawing shows a diagram of the proposed device. The device contains a drive 1, a group of additional drives 2, elements AND of the first group 3, elements AND of the second group C, element AND 5. encoder 6, decoder 7 shaper 8 overflow signal, element II 9 input buses 10, which receives information from message sources of bus 11 resolution write, bus 12 interrogation drive, spikes 13, which receive read enable signals from intermediate drives, output buses 14, which receive information from a group of additional drives, address block 15, which In accordance with the receipt of clock signals on its counting input, an address code is generated that arrives at the address inputs of accumulator 1. The device contains elements of the third 1b and fourth 17 groups, a group of elements HE 18, a element NOT 19 a element NOT 20, a shaper 21 of the end addresses, additional drive 22, trigger 23, the element 24 equivalence. The proposed device works as follows. Information from sources of communication. for example, telegraph devices, goes to bus 10 and then, by recording resolution signals that arrive alternately on bus 1 1, 5 8 drive 1 is recorded. In this case, a binary code is written to the check bits of drive 1 from the same address as the record information from the source. Thus, in drive 1 there is information coming from a source with marks indicating that this information belongs to one or another -, ;; point. When reading information from accumulator 1, a binary code containing control bits at the interrogated address is fed to the inputs of the decoder 7 and is converted into a positional code that allows the selection of the AND element of the second group k. This ensures that information read from accumulator 1 is passed to accumulators 2. Accumulators 2 are sequentially polled by readout signals received alternately on buses 13. If there is information in the intermediate accumulator, it is output to the bus 14. Filling of intermediate accumulators is controlled by shaping bodies 8 , the outputs of which are connected to the inputs of the element AND - NOT 9. When filling the drives 2 at the output of the element AND-NOT 9, a signal is generated that prohibits the receipt of polling signals from the bus 12 to the input about the main drive's millet is through element 5. When one or several additional drives 2 are filled, but not all, the survey of the main drive continues. In this case, the signal about filling from the output of block 8, associated with the filled drive 2 pos-. stupid through the element NOT 18 to one of the inputs of the second group of the element AND of the second group k and prohibits the input of the information read from accumulator 1 to the input of the filled intermedia accumulator. The signal about filling the accumulator 2 from the output of the imaging unit 8 arrives with a delay per polling cycle of accumulator 1, as a result of which the signal arrives at the input of the element I 1b following the tact of filling the access to this drive 2, at which the information arriving at its input 1 is not recorded. The signal about filling from the output of the element I 16 through the element. OR 20 arrives at one of the inputs of the AND 17 elements of the fourth group 2 and the additional control input of the accumulator 1. If the accumulator 22 is free, the input of the And 17 elements receives a signal allowing the writing of the address code from block 15 to the accumulator 22. Thus, drive 22 will contain the address code of drive cell 1, information from which was not read into drive 2 due to its filling. When writing the address code to the drive 22, the input signal of the elements And 17 through the element H 19 is given a signal that prohibits writing to the drive 22. The filling signal records 1 to the additional check bit of the drive 1 at the address of the cell containing information unreadable drive 2. At the end of the cycle of polling the memory cells of drive 1, the driver 21 generates a signal that polls drive 22, records the block code 15 contained in it, and sets trigger 23 to a single State, as a result of which The polling of accumulator 1 starts not from the starting address, but from the address of that cell whose information was not received by intermediate accumulator 2 in the previous cycle. Due to this, the time taken to output information from drive 1 to the output of the device is reduced. When the drive 1 is re-polled, only information contained in the memory cells, whose additional check bit is written 1, passes to the input of drives 2. This is ensured by the fact that the fourth inputs of the And 4 elements from the output of the Element 24 receive the enable signal, because from the output, the additional control is much larger than the accumulator 1 and the output of the trigger 23 at both its inputs 1. After the interrogation, the accumulator 22 is released, resulting in the input of the elements And 17 through the element: NOT 19 a signal is received that permits writing to n Job storage ring 22. Let us consider the proposed device provided that the memory cells poll accumulator 1 is to implement it without destroying the contained information. Such storage devices are currently the most widespread in connection with the development of integrated semiconductor technology. When used in the proposed device, a drive in which interrogating the memory cells destroys the information contained therein, for example, a drive on ferrite memory cells, when filling in intermediate storage device 2, the information read out from storage device 1 is rewritten again at the polled address on the regeneration circuit, which There are such accumulators (not shown). The advantage of the proposed device in comparison with the known ones is to increase the speed of information output from the main storage device and its delivery to the consumer. In known devices, the output is stopped as soon as one of the intermediate drives is full. In the proposed device, the survey of the main drive in such cases continues. In this case, information relating to unallocated intermediate accumulators is read from the main accumulator and then, after grouping, is output to the output of the device. Information relating to the busy drive is stored in the main drive, and its output speed is increased by the fact that after the end of the main drive's polling cycle, it is re-polled from the address of the cell whose information was not received occupied by intermediate storage. The invention contains a buffer storage device containing a drive, the information inputs of which are connected to the outputs of the elements of the first group, the first control input to the outputs of the gateway, the address inputs to the outputs of the addressable unit, and the control input of the storage device information outputs of the drive are connected to the first inputs of elements AND of the second group, and the first control output of the storage device is connected to the input of the decoder, the outputs of which are connected to the second inputs of the corresponding elements AND The second group, a group of additional accumulators, the inputs of which are connected to the outputs of the corresponding elements AND the second group, which controls the output to the input of the corresponding overflow signal generator, and the outputs of the additional accumulators of the group are information outputs of the device, in order to improve speed It contains the third group of elements AND, the first inputs of which are connected to the output of the corresponding overflow signal generator, and the second inputs to the corresponding outputs of the desh a group of elements NOT, the inputs of which are connected to the output of the corresponding overflow signal generator, and the output to the third inputs of the corresponding AND elements of the second group, the OR element whose inputs are connected to the outputs of the AND elements of the third group, and the output to the second control input of the accumulator, the element of ambiguity, the first input of which is connected to the second control output of the storage device, and the output - to the fourth inputs of the elements AND of the second group, an additional storage device, information outputs of which are connected to the inputs of the address block, the fourth group of elements AND, the first inputs of which are connected to the outputs of the address block, the second inputs to the output of the element OR, the element NOT whose input is connected to the control output of the additional drive, and the output to the third inputs of the elements AND the fourth group, the driver of the end of the address, the inputs of which are connected to the outputs of the address block, and the output to the second input of the additional accumulator, and the trigger whose input is connected to the output of the driver of the end of the address, and the output to the second input of the element equals achnosti. Sources of information taken into account during the examination 1. German patent number 1268652, cl. G 11 C 9/00, 1969. 2. USSR author's certificate for application number 2526171 / 18-24, cl. From 9/00, 03/31/73 (prototype). AND / f rJ n 24 t g jT  nineteen