SU743227A1 - Device for coding and decoding video information - Google Patents

Description

The invention relates to the field of television. A coding and decoding device, video information, is known: it contains: an input matching amplifier, a clock signal selector, a control unit, an image signal switch and an output matching amplifier; the second input of the clock signal is connected to the input of the clock pulse generator 1, However, the known device does not have sufficiently high noise immunity and video masking. The aim of the invention is to increase the degree of video information masking and noise immunity. For this B, a video encoding and decoding device containing a sequential input matching amplifier, a clock selector, a control unit, an image signal switch, and an output matching amplifier whose second input is connected to the second output of a clock selector whose output is connected to the input of a clock pulse generator, sequentially included code selection block, pseudo-random number sequence generator, the second input of which is connected to the output clock pulse generator, address switch, connected by the second and third inputs respectively to the output of the clock pulse generator and to the second output of the control unit, the first address register and the first memory block, whose second input and output are connected respectively to the second outputs and the second the input of the image signal switch, the second address register connected in series, connected by the input to the second switch output of the address signal, and the second memory block, the second input and output to torogo respectively connected to the third output switch and the third input image signal, an analog-digital converter, input and output of which are respectively connected to the selector input clock signal and the fourth switch input image signal, wherein

the second output of the code selection block is connected to the third input of the output matching amplifier.

The drawing shows a structural electrical circuit of the proposed device.

The video encoding and decoding device includes serially connected input matching amplifier 1, clock selector 2, control unit 3, image signal switch 4 and output matching amplifier 5, the second input of which is connected to the second output of sync selector 2. The output of the latter is connected to the input of a clock pulse generator frequency 6. In addition, the coding device contains a code selection block 7, a pseudo-random number generator 8, an address signal switch 9, the first an address register 10 and a first memory block 11, a second address register 12 and a second memory block 13, an analog-to-digital converter. 14.

The second input of the generator 8 of the sequence of pseudo-random numbers is connected to the output of the generator b of clock pulses. The second and third inputs of the KOMMi-TaTopa address signal 9 are connected respectively to the output of the generator 6 pulses — a frequency signal and to the second output of the control unit 3. The second input and output of the first memory block 11 are connected respectively to the second output and the second input of the image signal combator 4. The input of the second address register 12 is connected to the second output of the address signal switch 9. The second input and the output of the second memory block 3 are connected. respectively, with the third output and the third input of the com-5 lator 4 of the image signal. The input and output of the analog digital converter 14 is connected respectively to the inputs of the clock signal selector 2 and to the quarter 5m input of the signal switch from the circuit: None 4. The second output of the code selection unit 7 is connected to the third input of the output matching amplifier 5,

In the encoding mode, the device o works as follows.

The original full video signal through the input matching amplifier 1 is fed to the input of the clock signal selector 2. The dedicated synchronization signal is fed to the control unit 3. and the oscillator b of the clock, frequency pulses. In the latter, the synchronization signal carries out the phasing of the clock frequency pulse sequence. The output of the matching amplifier 1 is also connected via analog-to-digital converter 14 to the fourth input of the commander 4 image signal, which provides a serial (via ka, others) connection of the output signal of the analog-digital converter 14 to the inputs of either the first memory block 11, or the second memory block 13. The switching sequence is specified by the control unit 3 signal arriving at the switch 4 of the image signal. The inputs of the memory blocks 11 and 13 are connected respectively to the outputs of the address registers 10 and 12, and the inputs of which receive output signals from the switch 9 of the address signal, also controlled by the control unit 3. The second input of the switch receives a sequence of pulses of the clock frequency from the generator 6 of pulses of the clock frequency, and the first sequence of pseudo-random numbers from the generator 8 of the sequence of pseudo-random numbers. The sequence contains numbers from one to N, where N is the number of nominal decomposition elements in the INITIAL video signal. The order of the numbers in the sequence is determined by the control signal supplied to the generator control input from the code selection unit 7. The pseudo-random number sequence code is fed to the output matching amplifier 5 for mixing into the encrypted video signal in the backward intervals. A sync signal from the output of the sync signal selector 2 and an encrypted video signal from the output of the image signal switch 4 are also supplied to the output matching amplifier 5. Switches 4 and 9 operate in phase so that, in the frame in which the original video signal arrives at the first memory block 11, the first address register 10 is connected to a clock pulse generator. In the same time interval, the second memory block 13 is connected via its output via the switch 4 of the image signal to the input of the output matching amplifier 5, and to the second address register 12 (operating in the direct number setting mode and not in the counting mode) sequence of pseudo-random numbers. In the next frame, the output of the first memory block 11 will be connected by the switch to the input of the output matching amplifier 5, the first address register 10 - to the output of the pseudo-random number generator 8 and the memory field of the memory block 11, filled according to the scanning law of the original video signal, will be read by pseudo-random to the law. In the same time interval, the second memory block 13 will be connected by its input

with the output of the analog-to-digital converter 14, and the second address register 12 with the output of the clock frequency generator 6. After the memory of the memory unit 13 will be filled according to the scanning law of the source video signal.

The operation of the device in the decoding mode differs from that described by the fact that during the operation of the PS1m TI unit, the sequence of pseudo-random numbers is transferred to the write register on its address register through the switch 9 of the address signal. The order of the numbers in the sequence, as in encoding, is determined by the control signal from block 7 code selection. With this address. the memory cell into which the instantaneous value of the image signal is recorded will correspond to the address of the memory cell 7 of the encoder at the transmitting end, from which this instantaneous value of the image signal is extracted during transmission. As a result, upon expiration of the forward stroke interval, the frame after memory will be filled in the sequence of instantaneous values of the image signal that corresponds to the original image. To read the decoded signal from the memory block, its address register by the switch 9 of the address signal is connected to a clock frequency generator 6 and read out according to the law of the original video signal sweep.

From the description of the coding and decoding modes it is obvious that the difference between them consists only in the inter-phasing of switches 4 and 9. In the coding mode, the generator 6 of clock pulses must be connected to the address register of memory 11 or 13, and A generator of pseudo-random number sequences must be connected. In the decoding mode, the generator of 8 sequences of pseudo-random numbers must be connected to the address register of the filled memory block, and the generator of 6 clock pulses must be connected to the address register of the readable memory block. The transition from the coding mode to the decoding mode is carried out by internal switching in the control unit 3. The possibility of using the same device on both the transmitting and receiving sides with the mode of receiving and transmitting gives significant technical advantages in the operation of the equipment.

Claims (1)

1. Japan patent 51-12483, class, 97 (5) A15, 1976 (prototype). / J 12