SU758533A1 - Pulsed system for transmitting binary signals - Google Patents

Description

Rogr is connected to another output of a significant modulation moment recovery unit, and the output is connected to a receiver input, the output of the signal recovery unit is connected to another input of the receive register, the other outputs of which are connected to other decoder inputs, and the other outputs of the clock extracting unit are respectively connected to input frequency multiplier and another input shaper time intervals.

FIG. Figures 1 and 2 show the structural electrical circuit of the proposed system; FIG. 3 shows timing diagrams for the operation of devices.

The system contains on the transmitting side (Fig. 1) a source of 1 binary signals, an output matching unit 2, a transmission register 3, a converter of 4 signals, a source of 5 clock frequencies, a driver of the significant modulation moment (3 mm), a frequency multiplier 7, a driver of temporary spacing and encoder 9, and on the receiving side (Fig. 2) the input matching unit 10, threshold unit 11, clock extracting unit 12, receiver 13, significant modulation moment recovery unit 14 (3 mm), signal reconstructing unit 15, multiplier 16 form frequencies spruce slots 17, decoder 18, a register 19 and generator 20 receiving binary signals.

The device works as follows.

. On the transmitting side, the signal from the output of source 5 (FIG. Za) is fed to the input of multiplier 7 and at the same time this signal is fed to the synchronization input of the driver 8. In the multiplier 7, the frequency is multiplied by 2. The sequence from the output of the multiplier 7 is fed to the input of the generator 8 ( Fig. 36), at the outputs of which time sequences are formed (Fig. 3f, d, e, f) corresponding to the first, second, third and fourth time intervals. These sequences are fed to the inputs of the encoder 9. Binary signals from source 1 are fed simultaneously to register 3 and to driver 6. During the time when a constant signal is transmitted, for example, the corresponding logical zero, the input of register 3 is received by zeros, which are converted in converter 4 conveniently for transmission to the communication channel. Such a synchronous transformation can be, for example, bi-pulse transformation, a ternary code, etc. At the moment of time corresponding to the time interval between the first and second clock cycles.

Source 1 generates a signal unit, which causes the appearance of a signal at its output in the former, the temporary position of which corresponds to the signal front, i.e. the moment of transition from one state to another. The ZMM signal arrives at the encoder 9, which determines the number of the time interval in which the ZMM is located (Fig. 3f), and writes the number of this time interval to the installation inputs of registrar 3. As a result, the register 3 ne. The first bit is recorded (on the first clock), the value of this first bit corresponds to the value of the binary signal transmitted after forming the MMM. So, for example, when the output of the signal source 1 (Fig. 3) appears in register 3, the following information bits are written. On the first clock cycle, zero is stored from the previous state of the binary signal. On the second clock of the time diagram, a register corresponding to the actual state of the binary signal after the formation of the MMM is recorded into the register 3 by the information input. The third and fourth bits. Carry information about the number of the time interval in which the MMM was. The fifth and sixth bits correspond to the state of the signal that continues to arrive at the information input of register 3. At the time between the sixth and seventh cycles from source 1, a logical zero signal arrives, and the MMM enters in the third (in this particular case) time interval. Register 3 records zero on the seventh clock cycle, and on the eighth and ninth clock cycles, register 3 records the cipher corresponding to the third time interval in which the MMM is used. Thus, in register 3, each combination consisting of 01 or 10 is an indication of the formation of the PMM and the direction of the change in the state of the binary signal. The next two bits of information for the ZMM sign carry information about the number of the time interval containing the ZMM. during the remaining periods of time in register 3, the actual values of the binary signal are recorded. After synchronous conversion, information from register 3 is supplied with a clock frequency of source 5 (Fig. Pros, and) through output unit 2 to the communication channel. The switching of the current direction in accordance with the output signal of the converter 4 is additionally synchronized by the source 5.

At the receiving side, the received signal is supplied to an input unit 10, in which, for example, a frequency-amplitude correction line node and an amplifier may be contained. The signal from the output of the input unit 10 is fed to the input of the threshold unit 11, the output signal from which is fed simultaneously to the block 12 and block 15, which receives information about the averaged clock frequency. In block 15, the received synchronous binary signal is recovered in cycles (in time) and in amplitude sufficient to ensure the operability of the entire device. The block 12, the multiplier 16 and the driver 17 produce output signals similar to those on the transmitting side (Fig. 3k, l, m, n, o, n), which are sequences of the quadruple frequency of source 5 and four sequences of time intervals. All information transmitted is recorded in register 19 in succession. When a pulse combination is created at the parallel outputs of the register 19 that corresponds to the ZMM attribute and the cipher of the time interval ZMM, the decoder 18 generates a signal whose appearance corresponds to the decoded time interval. In block 14, the ZMM signal is restored. The reconstructed signal ZMM (Fig. Er) arrives at shaper 20, in which a binary signal is generated, the beginning of which is determined by restoration of ZMM, the sign is determined by the actual content recorded in the binary information register. After decoding the MMM and restoring its temporary position from the output of block 14, the MMM time interval is accelerated overwritten with acknowledgment information corresponding to the true state of the binary signal. At the output of the imaging unit 20, a recovered binary signal is generated (Fig. 3c), which differs from the initial one by an amount not exceeding the length of the time interval, which in turn corresponds to one fourth of the clock frequency period.

Thus, the proposed system allows improving the accuracy of transmission of anisochronic signals transmitted over a communication channel. Thus, the transmission accuracy is increased by as many times as the frequency of the clock pulses is multiplied. The speed of the transmitted pulses remains unchanged; therefore, the communication distance is also unchanged.

Claims (1)

1. USSR author's certificate 55 No. 462290, cl. H 04 B 3/00, 1971 (prototype). taffttun imil ctaic / but fi I i 1 I I I. I And {I I I t {I III I M I I II 9ig s