SU710040A1

SU710040A1 - Devider

Info

Publication number: SU710040A1
Application number: SU752134691A
Authority: SU
Inventors: Юрий Григорьевич Бондаренко
Original assignee: Предприятие П/Я А-1845
Priority date: 1975-03-26
Filing date: 1975-03-26
Publication date: 1980-01-15

Description

(54) УСТРОЙСТВО ДЛЯ ДЕЛЕНИЯ(54) DEVICE FOR FISSION

к 2 входам сумматора 1, и выходов которого подключены соответственно к п входам матрицы умпожени 3 (как множимое), к другим и входам матрицы умножени 3 подключены | выходов, регистра делител 4 (как множитель). В регистре делител хранитс дополнительный код делител . Делитель предварительно нормализуетс .to the 2 inputs of the adder 1, and the outputs of which are connected respectively to the n inputs of the matrix of multiplex 3 (multiplicative), to the other and the inputs of the matrix of multiplication 3 are connected | outputs, register divider 4 (as a multiplier). An additional divider code is stored in the divider register. The divider is pre-normalized.

Процесс делени начинаетс с момента поступлени делимого и дополнительного кода делител на предварительно обнуленные регистры 2 и-4. The division process starts with the arrival of the dividend and the additional divider code into the previously zeroed registers 2 and-4.

Процесс делени осуществл етс по итеративному уравнениюThe division process is performed by an iterative equation.

)где а - делимое,) where a is a dividend

в - делитель,c - divider

РК - к-е приближение результата. Через Л итераций на выходе сумматора 1 формируетс результат делени .RK is the k-approximation of the result. Through L iterations at the output of adder 1, the result of division is formed.

Итерационный процесс можно проследить на численном примере, The iterative process can be traced through a numerical example.

Р А/В 6,10101010/0,11000000Р А / В 6,10101010 / 0,11000000

0,101010100.10101010

0,11010101000.1101010100

0,110111110.11011111

0,11100001.0.11100001.

0,111000100.11100010

Claims

0.11100010 The number of iterations, as can be seen from the above example, may be less. . Introduction to the device of the comparison circuit can further increase the speed of the device, ending the process of division at P - P |. The speed of the proposed device is higher than that of the prototype, since the time in each iteration of the result is not recorded in the result of taking into account the maximum delay of the calculation transients. In addition, ma. the equipment used for multiplication, addition, and subtraction operations is used in the best way. DETAILED DESCRIPTION OF THE INVENTION A division device comprising a division register, a divider register and a multiplication matrix, and the outputs of the divider register are connected respectively to the first n inputs of the multiplication matrix, distinguished by the fact that

0,01000000 strodeystv, the adder is entered into the device, the first and its inputs are connected to the corresponding h outputs of the register of the dividend, the second and the inputs of the adder are connected to the corresponding and outputs of the multiplication matrix, and the P outputs of the adder are respectively connected to the second n inputs of the multiplier. Sources of information taken into account in the examination 1. The author's certificate of the USSR. No. 485447, cl. G 06 F 7/39, 1972.

2. USSR Author's Certificate No. 235397, cl. G About F 7/52, 1966.

3. U.S. Patent 3,733,477; 235-164, 1973.

4.. US patent number 3633018, cl. 235-164, 1972.

5.Kartsev M.A. A15 Digital Digital Machines, M., Science, 1969, p. 53-2-536.

6. Prangishvili I.V. and others. Microelectronics and homogeneous, structures for logic and computing devices, .M., Science., 1967, p. 183, rice, 4.42 (prototype).