SU584323A1 - System for checking information-transmitting units - Google Patents

Description

one

The invention relates to the field of automation and computer technology, in particular, to devices for detecting faults in devices, converting information transfer rate.

In the field of automation and computer technology, a device is often used that accomplishes the task of converting information transfer speeds when transmitting information between devices with different speeds, the main node of which is a drive. Moreover, in many cases, the conjugation conditions require the installation of two switching buffer drives in the device for converting the speed data, alternately operating in the write mode or reading mode.

In the process of functioning of a device for converting information transfer rate as part of complex systems, it is very important to ensure the operability of these devices. For this, it is necessary to have sufficiently effective means of control that can not only detect the presence of faults, but also indicate their location. One such tool is device control using test programs. To control an information transfer rate converter, a special device is required which would form a verification test, the code combinations of which would vary according to a certain law, for recording into one drive, simultaneously read information from another accumulator and analyze the results of passing the verification test each drive monitored device.

Devices are known for monitoring information transmission units, comprising triggers, a code comparison unit, AND elements and inequality unit 1, and a device for monitoring information transmission units, containing an address counter, logic elements, delay elements, control and monitoring registers, error fixation unit 2 .

The pedostat of the known device for controlling information transmission units is

the inability to diagnose its malfunction, since it is analyzed that not every word of the verification test passes through the control object, but the entire test according to the sum of the words of the test. The disadvantage of the second known device for monitoring information transfer units is the lack of monitoring of the software part of information transfer rate devices, which allows connecting drives to write, then to

reading, since it does not simultaneously with the issuance of a verification test to a monitored device, receiving from a monitored device and analyzing information sent to it during a previous period of time.

The closest solution to the present invention is a device for monitoring information transfer units containing its checked and reference blocks, a comparison block, two AND elements, a delay element, an AND gate element, an OR element, a counter, a decoder, a pulse generator, a trigger, buttons start and reset, the outputs of the tested and reference blocks are connected to the inputs of the comparison unit, the output of which is connected to the first input of the first element AND, the output of the first element AND is connected to the first input of the element OR, the output of which is connected zero trigger input, a single trigger output is connected to the first input of the second element, the second input of which is connected to the output of the pulse generator through the start button contacts, the output of the pulse generator through the reset button contacts is connected to a single trigger input and the first output of the counter is connected with the decoder, the first output of the decoder is connected to the first input of the gate element And, the second input of which is connected to the output of the delay element and the second input of the first element And, the output from The probing element I is connected to the first input of the tested and reference blocks 3.

The disadvantage of this device is the insufficiently complete control of the object, which is the information transfer unit that converts the information transfer rate with two buffer accumulators, since it is not carried out to generate a verification test for writing one frame into the checked circuit with simultaneous reading and analysis. the results of passing the preceding frame from the circuit under test, which is necessary for monitoring such a device for converting speed.

The aim of the invention is to expand the functionality of the device.

This is achieved by the fact that the device additionally contains a verification test block, a frequency divider, a word count counter, two additional AND elements: two additional delay elements, two additional triggers, two additional OR elements, the second output of the decoder being connected to the first input of the first additional element OR, the second input of which is connected to the zero input of the second additional trigger, with the installation input of the frequency divider, with a single input of the trigger, the output of the first additional The OR input is connected to the single input of the first additional trigger, the zero input of which is connected to the output of the second additional OR element, the first output of the word count counter is connected to the first input of the second additional OR element, the second input of which is connected to the second output of the word count counter and a single input of the second additional trigger, the output of the first additional element And is connected to the input of the block verification test and with the counting input of the counter of the number of words, the output of the second element And connected to the counting input of the frequency divider and the first input of the first additional element And, the second input of which is connected to the output of the first additional delay element, the single output of the first additional trigger connected to the input of the first additional delay element, the output of the frequency divider connected to the first input of the second additional element And, the second input of which is connected to the output of the second additional element of the rear} kk, the unit output of the second additional trigger is connected to the input of the second g An additional delay element, the output of the verification test block is connected to the second input of the tested block.

The drawing shows a functional diagram of the proposed device.

The device for monitoring information transmission units contains the checked block 1, the reference block 2, the comparison block 3; first element AND 4, delay element 5, gate element AND 6, first additional element AND 7, counter 8, decoder 9y first additional element OR 10, first additional AND trigger, second secondary element OR 12, frequency divider 13, second additional delay element 14, the second additional trigger 15, the word number counter 16, the verification test block 17, the second additional element And 18, the second element And 19, the first additional delay element 20, the element OR 21, the trigger 22, the pulse generator 23, the start button 24, the button reset 25. Identical outputs of blocks 1 and 2 are connected; | K, the inputs of the comparison unit 3, the output of which is connected to the first input of the first element AND 4. The second input of the first element AND 4 is connected to the output of the delay element 5 and the input of the gate element AND 6, the output of which is connected to the first inputs of the tested 1 and reference 2 blocks. The input of the delay element 5 is connected to the output of the second additional element And 18 and to the counting input of the counter 8. The first output of the counter 8 is connected to the input of the decoder 9, the first output of which is connected to the first input of the strobe element 6 and the second output is connected to the first input of the first additional element OR 10. The output of the first additional element OR 10 is connected to the single input of the first additional trigger 11, the zero input of which is connected to the output of the second additional element OR 12. The first input of the second additional An additional element And 18 is connected to the output of the frequency divider 13, and the second input

connected via a second additional delay element 14 to a single output of the second additional trigger 15. The pulse output of the last discharge of the word number counter 16 is connected to the first input of the second additional element OR 12, and the pulse output of the penultimate discharge of this counter is connected to the second input of the second additional element OR 12 and with a single input of the second additional trigger 15. The input of the word number counter 16 and the input of the verification test block 17 are connected to the output of the first additional element TA 7, the first input of which is connected to the output of the second element AND 19 and the second input of frequency divider 13, and the second input - with the output of the first additional delay element 20. The input of the first additional delay element 20 is connected to the unit output of the first additional trigger 11. The first input the element OR 21 is connected to the output of the first element AND 4, the second input is with the pulse output of the last digit of counter 8, and the output is with the zero input of the trigger 22. The single output of the trigger 22 is connected to the first input of the second element I 19, the second input d through which the starter contacts 24 connected to the output of the pulse generator 23. The pulse generator buttons Output 23 is also connected via a reset button contacts 25 to the zero input of the counter 8, the frequency divider 13, the second additional trigger

15, the word count counter 16 and the single input trigger 22.

The device works as follows. When you press the reset button 25 counters 8 and

16, the frequency divider 13 and the trigger 15 are set to the zero state, and the trigger 22 is set to one state, in which a potential is present at the first input of the element 19 that allows the pulse to pass through this element through the second input.

At the same time, the AND trigger is set to one, with the result that at the second input of the element 7 there is a potential that allows the pulses to pass through the first input of this element.

When you press the start button 24, the generator pulses 23, pass through the element I 19, and start the input to the frequency divider 13 and to the first input of the element 7. From the output of the element 7, the pulses will follow to the input of the test test block 17 to form the word frames of the verification test and gating the recording of each word in the checked block 1.

Simultaneously from the output of the element And 7 pulses will be fed to the input of the counter 16, counting the number of words of each frame of the verification test. As soon as the input of the counter 16 receives as many pulses as there are words in the frame, all bits of the counter 16, except for the last, are set to the zero state, the tiergger 11 will also be set to the zero state, and the trigger 15 to the single state. As a result, at the input of element 7 there will be a potential that prohibits the passage of imimuls to the input of the verification test block 17 and to the input of counter 16, and at the input of element 18 there is a potential allowing the passage of pulses from frequency divider 13 to the input of counter 8 and the delay element 5 to the input of the gate element and 6 and the input of the element 4. On the other input of the gate element 6, signals from the output of the decryptor 9 will be received. In this case signals from the output of the gate element 6 will be read from checked 1 and reference 2 blocks into comparison block 3 for a one-by-one comparison of each word. The first signal from the output of the decimator 9, the trigger I will be set to "1, the pulses from the output of the element 7 will be fed to the input of the counter 16 and the input of the verification test block 17 and the formation and recording of the second frame of the verification test in the checked block 1 will begin frames from checked 1 and reference 2 blocks into comparison block 3.

After the number of pulses equal to twice the number of words is received by the input of the counter 16, the counter 15 will overflow and the overflow pulse of this counter will again set the trigger 11 to the zero state.

Similarly, the counter 8, after receiving at its input a number of pulses equal to twice the number of words of the verification test frame from the pulse output of the last bit, generates an overflow pulse, which through the OR 21 element sets the trigger 22 to the zero state, resulting in the first input of the AND element 19, a potential will be established prohibiting the passage of pulses through this element, and the device will stop its operation.

If the word from the tested block corresponds to the reference unit, the comparison unit 3 generates a signal which, through element 4 and element 21, switches trigger 22 to the zero state, as a result of which the device stops its operation and the number in counter 8 shows in which from two drives and in what his cell malfunction is fixed.

Compared to the known devices, the functionality has been expanded, since a more complete control of the information transfer unit is implemented, which coordinates the information transfer rate with two selectable buffer accumulators.

Claims (3)

Invention Formula A device for controlling information transmission units containing a test and reference blocks, a comparison block, two AND elements, a delay element, an AND gate element, an OR element, a counter, a decoder, a pulse generator, a trigger, start and reset buttons, and the outputs being checked and the reference blocks are connected to the inputs of the block compared, the output of which is connected to the first input of the AND element, the output of the first element AND is connected to the first input of the OR element, the output of which is connected to the zero input of the grigger, the single output of the trigger dinene with the first input of the second element And, the second input of which through the contacts of the start button is connected to the output of the pulse generator, the output of the pulse generator through the contacts of the reset button is connected to the single trigger input and the installation input of the counter, the first output of which is connected to the decoder, the first output of the decoder is connected with the first input of the gate element And, the second input of which is connected to the output of the delay element and the second input of the first element And, the output of the gate, its element And is connected to the first input of the wire The standard and reference blocks are distinguished by the fact that, in order to expand the functionality, it additionally contains a verification test block, a frequency divider, a word count counter, two additional elements AND, two additional delay elements, two additional triggers, two additional elements OR, the second output of the decoder is connected to the first input of the first additional element OR, the second input of which is connected to the zero input of the second additional trigger, with the installation input of the divider h A single trigger input, the output of the first additional element OR is connected to a single input of the first additional trigger, the zero input of which is connected to the output of the second additional element OR, the first output of the word count counter is connected to the first input of the secondary OR element, the second input of which is connected to the second the output of the word number counter and the single input of the second additional trigger; the output of the first additional element I is connected to the input of the verification test block and the counting input of the word number counter, the output of the second element I is connected to the counting input of the frequency divider and the first input of the nerve additional element I, the second input of which is connected to the output of the first additional delay element, the single output of the first additional trigger is connected to the input of the first additional delay element, the output of the divider frequencies are connected to the first input of the second additional element And, the second input of which is connected to the output of the second additional element of the delay, are single output of the second latch coupled to an additional input of the second additional delay element, a screening test block output is connected to the second input unit checks emogo. Sources of information taken into account in the examination 1. USSR author's certificate number 330453, cl. G 06 F 11/02, 1970. 2. USSR author's certificate number 341087, cl. G PS 29/00, 1970. 3. USSR author's certificate number 238236, cl. G 06 F 11/00, 1967.