SU530462A1

SU530462A1 - Frequency multiplier

Info

Publication number: SU530462A1
Application number: SU2086464A
Authority: SU
Inventors: Юрий Константинович Майоров
Original assignee: Предприятие П/Я А-1902
Priority date: 1974-12-18
Filing date: 1974-12-18
Publication date: 1976-09-30

Description

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Изобретение относитс к измерительной технике, автоматике, в частности к системе регулировани авиационных двигателей.The invention relates to measurement technology, automation, in particular to an aircraft engine control system.

Известен умножитель частоты, содержащий генератор импульсов, соединенный с фор ;мирователем элементами И и ИЛИ, диод:ными ключами и накопительным конденсатоipoM , а выход формировател св зан с входом ;генератора дополнительной цепью обратной св зи, содержащей устройство пересчета ГIJ. A frequency multiplier is known, which contains a pulse generator connected to the form, the AND and OR elements of the world, a diode: key switches and storage condensate I, and the output of the driver is connected to the input of the generator by an additional feedback circuit containing the GIJ recalculation device.

Однако дл такого умножител характерны :частотные ошибки в переходном режиме и фанзовые ошибки в установившемс режиме работы .However, for such a multiplier are characteristic: frequency errors in the transient mode and fanless errors in the steady state operation.

Наиболее близким по технической сушности к предлагаемому умножителю вл етс умножитель, содержащий последовательно соединённые первый счетчик и делитель частоты , входы которых объединены и через линию задержки подключены к входной шине и к входу запоминающего устройства, входы которого соединены с выходами чеек первого счетчика, и опорный генератор, выходы которого подключены к входам второго счетчика и делител частоты 23.. The closest in technical drying to the proposed multiplier is a multiplier containing serially connected first counter and a frequency divider, the inputs of which are combined and through a delay line connected to the input bus and to the input of the storage device whose inputs are connected to the outputs of the cells of the first counter, and the reference generator The outputs of which are connected to the inputs of the second counter and frequency divider 23 ..

Такой умножитель частоты имеет невысокуйэ точность из-за по влени неравномерности временных- интервалов между выходными импульсами.Such a frequency multiplier has low accuracy due to the appearance of irregularity of time intervals between output pulses.

Цель изобретени - повышение точности умножени .The purpose of the invention is to increase the accuracy of multiplication.

С этой целью в предлагаемый умножитель частоты, содержащий два счетчика, делитель частоты, запоминающее устройство, делитель частоты и линию задержки, введены элемент совпадени и дополнительна лини задержки, подключенна к выходу элемента совпадени и к второму входу второго счетчика, выходы чеек которого соединены с входами элемента совпадени , а входы чеек-с выходами запоминающего устройства.For this purpose, a matching element and an additional delay line connected to the output of the matching element and to the second input of the second counter whose outputs of the cells are connected to the inputs are introduced into the proposed frequency multiplier comprising two counters, a frequency divider, a memory device, a frequency divider and a delay line. the matching element, and the inputs of the cells with the outputs of the storage device.

На чертех е представлена структурна электрическа схема умножител частоты.In the drawing, an electrical frequency multiplier circuit is shown.

Claims

The frequency multiplier consists of a reference oscillator 1 connected to the input of a frequency divider 2 with a division factor, the desired multiplication factor, the output of which is connected to the input of the first | Counter 3. The outputs of the counter cells 3 are connected to a memory device 4, the outputs of which are connected to the second counter 5, performed subtractive. The input of the counter 5 is connected to the reference generator 1. The input bus 6 is connected to the readout circuit of the counter 3 in the storage device 4 and to the input of the delay line 7, the output of which is connected to the reset circuit of the first counter 3 and the frequency generator 2. Output of the multiplier connected to the coincidence element 8, the inputs of which are connected to the outputs of the cells of counter 5 and to the input of the additional delay line 9, the output of which is connected to the reading circuit of the device 4 to the second counter 5. The multiplier works as follows After passing Neither the delay 3 of the next pulse arriving at the input bus 5 of the frequency multiplier is reset to the zero of the counter 3 and frequency divider 2. Then the accumulator 3 accumulates 3 pulses from the output of frequency divider 2. By the time the next frequency multiplier arrives at the input the pulse in counter 3 records the number of G-I frequency of the reference oscillator; input frequency period; divider division factor; - dividing frequency divider ratio. The input pulse of the frequency multiplier goes to the reading circuit of the meter 3 to the memory 4. The pulse from the output of the delay line 7 resets the counter 3 and the frequency divider 2 to zero. Thus, the device 4 stores all the time corresponding to the period of the input frequency. This number is not erased, and can only change if the input frequency changes. The pulses of the reference oscillator 1, arriving at the input of the subtracting counter 5, at some point bring it to the zero state. At the moment of its falling into the zero state from the output of the coincidence element 8, a pulse arrives at the output of the frequency multiplier. The same pulse arrives at the input of the additional delay line 9, after passing a pulse through which the reading of device 4 is recorded in counter 5. The next pulse at the output of the frequency multiplier appears after time i K. -on Thus, the accuracy is increased due to that the second counter has no connection to the input of the frequency multiplier. Claims of the invention A frequency multiplier comprising a serially connected first counter and a frequency divider, the inputs of which are combined and connected via a delay line to the input bus and to the input of a storage device whose inputs are connected to the outputs of the cells of the first counter, and a reference oscillator whose outputs are connected to the inputs of the second a counter and a frequency divider, distinguished by the fact that, in order to increase the multiplication accuracy, a matching element and an additional delay line are added to it, the element connected to the output and the matches to the second input of the second counter, the outputs of the cells of which are connected to the inputs of the match element, and the inputs of the cells to the outputs of its device. Sources of information taken into account in the examination of the invention: 1. Avt.st. The USSR № 366550, N 03 K 1/16, 07.06.71.

2. Avt.Sv. USSR № 337947, H 03 K 23/00, 28.12.70 (prototype).