SU1718398A1 - Redundant computer system reconfiguration controller - Google Patents

Abstract

The invention relates to computing and can be used in the construction of parallel computing systems with increased reliability. The purpose of the invention is to increase the efficiency of diagnosing computing systems with a small time reserve by reducing the detection time of the failed processor. The reconfiguration control device contains six AND elements, two delay elements, three AND groups, an OR group, a clock generator, a processor readiness register, the first and second shift registers, a matching encoder, an OR element, a HE element, and a lock trigger. The device reduces the detection time of the failed processor from m to three control cycles. 4 ill., 2 tab. & Yo

Description

The invention relates to computing and can be used in the construction of fault-tolerant multiprocessor computing systems (VS).

The purpose of the invention is to increase the efficiency of diagnosis.

FIG. 1 shows a scheme of a reserved aircraft; in fig. 2 is a device for managing reconfiguration of a redundant aircraft; in fig. 3 and 4 are timing diagrams of the operation of the control device.

The reserved C (Fig. 1) contains 1i.l2, -1m. iro + i redundant processors, information output switches 2i, ..., 2p, memory modules 3i ...., 3m, control device 4, input group 5t, ..., 5m. 5m + i control device control, switches 6i ,, .., 6m information input, group

7i outputs, .... 7m. 7t + 1 processor control and device switching output groups 8i, ..., 8m, a switch 9 of the comparison, a output 10 of the control of the comparison of the device, a block 11 of the comparison and an input 12 of the comparison of the device.

The control unit (Fig. 2) contains the first element AND 13, the first delay element 14, the first group of elements OR 15i, ..., 15m, 15nvH, the processor readiness register 17, the second group of elements AND 18i, ..., 18m, 18m + i, the third group of elements And 19i.,., 19m, 19t + 1, second element And 20. generator 21 clock pulses, third 22 and fourth 23 elements And, first shift register 24, second shift register 25, matching encoder 26, output 27 of the generator 21 clock pulses, outputs 28i Start,

00

with

H) 00

29i Lock Record. 30 | Stop from the group of outputs 7i, ... 7t, 7t + control device processors, fifth 31 and sixth 32 elements And, the second delay element 33, the element OR 34, the element NO 35 and the trigger 36 of the lock.

Processor readiness register 17 contains information about the state of the processors (healthy or defective), which is determined by the state of the corresponding register bits 17. The 1st bit is in the zero state, the 1st processor is healthy, if in one unit it is faulty. The generator 21 is intended for general synchronization of the operation of the system and separation of the computational process into clock cycles by generating start signals of the processors and control signals for the switches.

The first shift register 24 is designed to determine the pair of processors to be scanned (if the i-th register bit is in the single state, this means that the 1st and (I + 1) -th (Jf.) Processors are checked in the current clock cycle. m) if in the unit state (t + 1) -th bit, then check (t + 1} -th and first processors to control the comparison switch 9. To get the output of the Signal blocking signal to that processor from a pair of tested which was monitored in the first cycle of two adjacent control cycles, contains information on the number of the processor being controlled an auto clock in two clock cycles (the corresponding register bit in a single state).

The second shift register 25 is designed to control the output switches 2t and information input 6i (I 1, t) based on the state of the corresponding bits. If the 1-bit of the second register 25 is in the zero state, then the switches 2i and 6i connect the (I + 1) -th processor to the i-th memory module, the 1-bit unit provides the connection (i + 1) of the processor to the (i + 1) -th memory module (1 1, yyyy-1), the unit state of the m-ro bit is the connection of (t + 1) -th processor to the first memory module. The second shift register 25 can be made on the basis of a reverse shift register, while the information and control inputs of this register must be switched in such a way that when shifted down to the high register digit (DO), T is recorded, and when shifted up to the youngest bit d (D3) recorded O.

The encoder 26 matching is designed to form the installation code of the second shift register 26 in the case of receipt of one of the inputs 51 5t on one of the inputs. 5t control

signal devices from the means of control of the corresponding processor, i.e. a signal indicating a processor failure, the need to use the matching encoder 26 is caused by the required distribution, in order to preserve the system performance, the remaining m healthy processors to work with the m memory modules, since the failed processor detected by internal control is excluded from the configuration for The recovery module, and the memory module, if in the current cycle its information was not processed in parallel by two processors, remains without a processing processor. On

timing diagrams (Fig. 3 and 4) signals

assigned positions of the same output.

The principle of operation of the aircraft is

in the following.

Each redundant processor is connected to one of the memory modules through the respective input and output switches in each clock cycle. In the initial state, all the processors are intact, with each

The clock is assigned to a pair of scanned processors that are connected to the same memory module and execute the same instructions on the same source data. The results of the pair of processors are compared.

  In the next cycle, a new pair of scanned processors is assigned. If in the current control cycle there was an incomparison between the results of the operation of a pair of inspected processors, then the control unit keeps this information for one tact, and a new pair of inspected processors is assigned to the next control cycle. In case of non-comparison of the results of work and in a new pair of inspected processors, a decision is made about the failure of the processor, which is controlled in both pairs, otherwise the system is transferred to the previous configuration. If at the end of the next cycle of work, the results in a pair of controlled processors coincided - this means that the incomparability of the results of work in this pair took place was caused by a single failure. If, at the end of the next cycle of work, an incomparability of results occurred, then a decision is taken about the failure of the processor, which was controlled in the last two cycles.

8 further until the recovery of the failed processor and its inclusion

In the configuration, system health monitoring is carried out only by built-in processor monitoring tools. After restoring the failed processor, the system again functions in redundancy mode.

Reserved In C works as follows.

In the initial state, when all the processors b, ... 1m, 1m are also intact, in all bits of the register 17 of the processor readiness are written zeros. High level signals from the inverted outputs of register 17 allow passage through the corresponding elements of And 19i, ..., 19m, 19t + | to the outputs 7i, ..., 7m, 7m-n of the controllers of the processors of the control unit of the trigger signals of the corresponding processors from the generator 21.

The control of switching processors to certain memory modules is technically carried out using a second shift register 25, the bit states of which determine the signal levels at the respective control switch switching outputs 8i, ... 8m.

In the initial state, the code 000 ... 00 is written in the second register 25. The order of connecting processors to memory modules with this code is listed in Table. one.

Thus, in the first clock cycle, the Nits 12. processors of the information of the first memory module 3 will be monitored. This is evidenced by the contents of the first shift register 24, in which the code 1000 ... 00 is written in the initial state. The correspondence of the codes of the first register to 24 pairs of scanned processors is shown in Table 2.

After the counting is performed, the results from the information outputs of all the processors arrive at the information inputs of the comparison switches 9. From the output 10 of the device comparison control, the control- ing input of the switch 9 enters the code, switching the information of the negative processor editors to the inputs of the TV unit Comparison. In the first cycle, these are the outputs of the processors, 1i and

12. The output information of a pair of scanned processors is compared in comparison block 11, the output of which, with a positive comparison result, produces a low level signal which, acting on the comparison input 12 of the control device, prohibits the operation of the AND element

13. After that, the counting results from the information outputs of the unchecked and one of a pair of scanned processors through the switches 2 information outputs arrive at the inputs of the memory modules 3 and are recorded in them. The output will be recorded in the memory module.

4

processor from a pair of verifiable, which was controlled in this and previous cycles (Table 2).

This is achieved by blocking the recording of the output of another scanned processor, i.e. processor, which is controlled in the first cycle of two adjacent control cycles. For this, the bits of 1.2 t, t + 1 of the first register

24 is transmitted to the inputs 182. 18z 18t + 1

At the third group of elements And at the resolution level at the second inputs of elements 19, a high level at the output of one particular element 19 is transmitted to the corresponding output bus 7 of the controllers of the device. In the first measure, this is output 292 Record Lock.

On the next clock pulse, the contents of the first register 24 and register 25 are shifted, while the codes 010 ... 00 and 110 ... 00 will be recorded in them, respectively, and in the second clock, processors 12 and 1z-B will be monitored (t + 1 ) th cycle the contents of the first register 24 will be the following: 000 ... 01. a second register

25 respectively 111 ... 1.1. After that, on the next clock pulse, the first shift register 24 and the second shift register 25 are reset: 100 ... 00 and 000 ... 00, respectively.

The processor failure is detected by external control, as well as by means of the built-in control, if they allow detecting this failure.

Let the i-th cycle of the system work (Fig. 3). In this cycle, processors 1i and 1j + i are assigned as a pair of processors to be checked. Suppose that the results of their work did not coincide, and at the output of block 11 a high-level signal was generated. This signal is fed to the input 12 of the device comparison and then to the inputs of the first element And 13 of the first delay element 14, the element 35 and the sixth element 32. The element 11 (D-flip-flop) delays the signal arriving at its input by one cycle. Therefore, the low level of the signal from the output of the delay element 14 prohibits the passage of the signal of non-comparison through the element 13. Since the output of the second delay element 33 is also low, the passage of the signal of the comparison through the sixth element 1/1 32 is also prohibited. The control device does not change its operation.

B. Next i + 1 cycle (Fig. 3), processors 1i + i operate in parallel and Let there be an incomparison between the results of the operation of a pair of processors under test in this cycle. The signal can not be compared with the output of block 11 is fed to the input 12 of the comparison

control device and passes through the first AND 13 element, which will be opened by a high level signal from the output of delay element 14 (the result of incompatibility in the previous cycle), and the OR element 34 to one of the Inputs of elements AND 15 of the first group. The appearance of a high level signal at the output of the OR 34 means processor failure / The number of the failed processor is determined by the content of the first register 24, the output of i + 1-bit of which in the current I + 1-mtakte forms a high level that allows the failure signal to pass through the AND 15z-1 element on the OR 16n-1 element and through it to the input of the register 17. At the same time, the corresponding register register 17 of processor availability is set to one, at the direct output of which a stop signal is generated processors 1 | -n. arriving at the output bus 7 of the processor control, at the inverse output .- a low-level signal, which, by closing the element 19i + i, prohibits the passage of the start signals 27 from the generator 2.1 to the output bus 7 of the processor control. The low level from the inverted output of the i + 1-th register register 17, which enters the input of the second element And 20, forms a low level at the output of this element, which enters the input of the elements And 18i, .., 18m, 18t and prohibits passing the write blocking signals to the output control bus 7i, ... 7m, 7m + i processors. In addition, a low level from the output of the element And 20 enters the input of the fourth element And 23, prohibiting changes in the contents of the first 24 and second 25 registers pulses 27 from the generator 21.

Thus, the system is prepared for operation with m healthy processors. Starting from the next clock cycle, the system will continue to function with m healthy processors without external control; the functions of the stopped processor 1i + i will be performed by the neighboring processor 1i + 2. Processor health monitoring will be carried out only by internal control.

If in Г.- + 1st cycle from the comparison block 11, the high level signal did not arrive at the comparison input 12 of the control unit (Fig. 4). those. the results of the pair of processors being tested matched, then the high level signal from the first delay element 14 (the result of the comparison in the previous cycle) passes through the fifth AND element and goes to the input of the lock trigger 36 installation, to the upward shift inputs of registers 24 and 25, and at the entrance of the second

element 33 delay. By this signal, the contents of registers 24 and 25 are shifted up one bit, and the lock trigger 36 is set to one, 5 thereby blocking the contents of the first 24 and second 25 registers down through the next clock pulse from the generator output .21. Thus, in the next I + 2 nd cycle (Fig. 4), the

0 processors 1j and 1i + i. If at the end of their work from the output of the comparison unit 11 to the control input 12 of the control unit there is no signal about the non-comparison of results, then the high level signal from the output of the second

5, the delay element 33 will not pass through the sixth AND 32 element; by these signals, the blocking trigger 36 is nullified and the single signal appearing at the inverse output of the trigger 36 resolves in the next cycle

0 passing through the fourth element AND 23 clock pulses from the output 27 of the generator 21. The control device does not change its operation, since in this case, received in the i-th clock cycle from the comparison block 11

5, a high level signal was initiated by a single-ended failure of a pair of inspected processors.

If, on the i + 2nd cycle (Fig. 4), a high-level signal arrives from the comparison block 11, indicating a discrepancy in the results in the pair of tested processors 1i and 1j + i, then a decision is taken about the failure of processor 1i. The high level signal received at the comparison input 12 allows the signal from the output of the second delay element 33 to pass through the sixth element 32. The control device is configured to work with m healthy processors. In this case, the functions

0 failed processor 1 | will execute the adjacent processor 1st-1.

Thus, the proposed device allows reducing the detection time of the failed processor from m + 1 to three

5 control cycles and therefore can be used for aircraft with a small time reserve.

Claims (1)

Apparatus of the Invention for managing the reconfiguration of a redundant computational 0 of the system, containing the first and fourth elements AND, a group of elements OR, the first and third groups of elements AND, the first delay element, the processor readiness register, the clock generator, 5 the first and second shift registers, the encoder of the negotiation, whose inputs and the first inputs of the elements of the OR group are connected to the corresponding inputs of the device control input group, the outputs of the encoder encoder to the information inputs the second shift register, the reset input of which is connected to the output of the first bit of the first shift register, the synchronization and shift inputs of the second shift register are connected to the outputs of the third and fourth elements And, respectively, the outputs of the second shift register are connected to the group of control switching outputs of the device, the outputs of the first the shift register is connected to the control output of the device comparison and the first input of the corresponding AND elements of the first group, the outputs of which are connected to the second inputs of the corresponding elements OR groups, device comparison input to the first input of the first element AND and through the first delay element to the second input of the first element AND, the outputs of the elements OR of the group are connected to the information inputs of the processor readiness register, the direct outputs of the register of the number of processors of the second and third groups of elements AND are connected with the corresponding outputs of the group of outputs for controlling the device's processors, the inverse outputs of the processor readiness register are connected to the first inputs of the corresponding elements AND of the third group and to the inputs a second AND gate, the forward and inverted outputs are connected to first inputs of the fourth and The third elements And, respectively, to the second inputs of which and to the second inputs of the elements And the third group is connected to the output of the clock, the first the inputs of elements AND of the second group are connected to the corresponding outputs of the first shift register, and the second inputs to the direct output of the second element I, the output of the fourth element I to the input shift of the first shift register, which is , in order to increase the diagnostics efficiency, the fifth and sixth elements are entered into the control unit. The second delay element, the OR element, the element NOT and blocking trigger, the output of which is connected to the third input of the fourth And element, the outputs of the first and sixth And elements - to the first and second inputs of the OR element, the output of which is connected to the second the inputs of elements AND of the first group, the input of the device comparison is connected to the first input of the sixth element AND, and through the element NOT to the first input of the fifth element I. The second input is connected to the output of the first the delay element, and the input is connected to the gate inputs of the first and second shift registers, to the input of the blocking trigger, and through the second delay element to the second input of the sixth And element and the input reset trigger lock. o1I1 ... 1P1 3 pgn ... j. j. 1 2J w + 2 0 .. OO. .... 6- 61 12 OO 0O 1O Of o oh oh t O00 Table table 2 t - 1 (1111 “„ m- if . - -0 | Ol l 0 | H   i, “i - I I I I I J -E - E Ј: IVjiG T-Hvrg c CO Th Fig 5 Fig: 4