SU1647561A1

SU1647561A1 - Modulo two multiplier

Info

Publication number: SU1647561A1
Application number: SU894698020A
Authority: SU
Inventors: Олег Николаевич Музыченко
Original assignee: Войсковая часть 31303
Priority date: 1989-05-29
Filing date: 1989-05-29
Publication date: 1991-05-07

Abstract

Изобретение относитс к области автоматики и вычислительной технике и может быть использовано дл по- строени систеМ передачи и переработки дискретной информации. Цель изобретени - сокращение аппаратурных затрат и повышение быстродействи . Устройство содержит элементы И1 - 18, элемент ИЛИ 19, элемент ИЛИ-НЕ 20, элемент ИЛИ 21, элемент ИЛИ-НЕ 22, элемент ИЛИ 23, элемент ИЛИ-НЕ 24, элементы И 25, 26, 27. 1 табл., 1 ил.The invention relates to the field of automation and computing and can be used to build systems for the transmission and processing of discrete information. The purpose of the invention is to reduce hardware costs and increase speed. The device contains elements I1 - 18, element OR 19, element OR-NOT 20, element OR 21, element OR-NOT 22, element OR 23, element OR-NOT 24, elements AND 25, 26, 27. Table 1, 1 silt

Description

Изобретение относитс к вычислительной технике и может быть использовано дл построени систем передачи и переработки дискретной информа- ции.The invention relates to computing and can be used to build systems for the transmission and processing of discrete information.

Цель изобретени - сокращение аппаратурных затрат и повышение быстродействи .The purpose of the invention is to reduce hardware costs and increase speed.

На чертеже представлена схема устройства дл умножени по модулю семь.The drawing shows a diagram of an apparatus for multiplying modulo seven.

Устройство дл умножени по модулю семь содержит элементы И 1-18, элемент ИЛИ 19, элемент ИЛИ-НЕ 20, элемент ИЛИ 21, элемент ИЛИ-НЕ 22, эле- мент ИЛИ 23, элемент ИЛИ-НЕ 24, элементы И 25-27.A device for multiplying modulo seven contains elements AND 1-18, element OR 19, element OR-NOT 20, element OR 21, element OR-NOT 22, element OR 23, element OR-NOT 24, elements AND 25-27 .

В таблице приведены выходные сигналы элементов схемы дл всех разрешенных входных комбинаций сомножителей, не превышающих 6, а также дл входных комбинаций, когда значени сомножителей равны ,The table shows the output signals of the circuit elements for all allowed input combinations of factors that do not exceed 6, as well as for input combinations, when the values of factors are equal,

Из таблицы видно, что при подаче на входы всех разрешенных комбинаций сомножителей-устройство формирует- на выходе двоичный код числа ()mod 7. При подаче на входы запрещенных входных комбинаций , устройство также формирует пра- вильный результат, однако, не всегда приведенный, т.е. в отдельных случа х на выходе формируетс код модул .The table shows that when all the allowed combinations of factors are fed to the inputs — the device forms a binary code of the number () mod 7. When the forbidden input combinations are fed to the inputs, the device also generates the correct result, however, it is not always given . in some cases, a module code is generated at the output.

Claims

Invention Formula

A device for multiplying modulo seven, containing six groups of AND elements, three AND elements and three OR elements, characterized in that, in order to reduce hardware costs to increase speed, three OR-NOT elements are introduced into it, and each elements AND contains three elements AND, the input of the first bit of the first factor of the device is connected to the first inputs of the first elements AND of each group, the input of the second bit of the first factor of the device is connected to the first inputs of the second elements AND of each group, the input of the third bit first multiplier device

five

0

5 o

five

d 5 -Q

Va is connected to the first inputs of the third elements AND of each group, the input of the first bit of the second factor of the device is connected to the second inputs of the second and third elements of the first group, the second inputs of the first element of the second group, the first and third elements of the third group, the second element of the fourth group, the first and second elements And the fifth group and the third element And the sixth group; the second input of the third element And the second group, the second input of the second and the third input of the third element And the third group, the second input of the first element And the fourth group, the third entrance of the first and the second input of the third element And p of that group and the second input of the second element And the sixth group, input The third bit of the second device multiplier is connected to the third inputs of the first and third elements AND of the first group, the second input of the second element AND of the second group, the third inputs of the first and second elements AND of the third group, second eye input of the third element And the fourth group, the third inputs of the second to the third elements And the fifth group and the second input of the first element And the sixth group, the outputs of the first, second and third elements And the second, fourth and sixth groups are connected to the first, second and third inputs, respectively the first, second and third elements OR, the outputs of which are connected to the first inputs of the first, second and third elements AND, the outputs of which are connected respectively to the outputs of the first, second and third bits of the result of the device, and torye inputs - outputs from the first, second and third OR-NO elements, first, second and third inputs are connected to outputs of the first, second and third AND gates, respectively. but first, third and p of that group.