KR920002745Y1 - System for high-speed and rotation - Google Patents

Abstract

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Description

Fast shift and rotate system

1 is a schematic diagram of a conventional rotate and shaft system.

2 is a block diagram of a fast shift and rotate system of the present invention.

3 is a logic table of the masking logic portion 14 of FIG.

4 and 5 are tables and one embodiment showing conditions for converting right shift data into left shift data.

6 shows a simplified embodiment with only the function of a left shift.

* Explanation of symbols for main parts of the drawings

11a-11a, 11b-13b, 21a-23a, 21b-23b: buffer

14: masking logic part

The present invention relates to bit shift and rotate in a digital circuit, and more particularly, to a high speed shift and rotate system capable of realizing a rotate and shift operation only through passage of a gate circuit without using a clock.

1 is a schematic diagram of a conventional rotate and shift system, as shown therein, a shift register 1 for performing a shift operation by attaching parallel data, and providing a shift pulse to the shift register 1; A control signal generator (not shown in the drawing), which is composed of a clock generator 2 and generates control signals in accordance with a situation to be processed, is further connected thereto.

In the conventional system configured as described above, a process of performing an n-bit shift operation is performed. First, one-byte or one-word data to be shifted is latched in the shift register 1, and then shift data is shifted to the clock generator 2. Remember (shift number = n).

Subsequently, the control signal generator outputs a control signal to the control line, and outputs n pulses to the shift register 1 while decreasing the shift data recorded in the clock generator 2 one by one to thereby perform n-bit shift operation. It was to be performed. However, in such a conventional system, since data processing is performed sequentially by data latching, clock pulse data input, and clock generation, a considerable amount of time is required, and thus there is a problem that it cannot be applied to a circuit requiring high speed.

The present invention devised a system capable of processing data by only passing through a gate circuit without using a clock signal in performing data rotation and shift operations in order to solve such a conventional problem. It explains in detail.

2 is a block diagram of the high-speed shift and rotate system of the present invention. As shown in FIG. 2, the data lines D'7-D'o are rotated 1 bit, 2 bits, 4 bits, and rotated in series to the input terminals. A buffer (11b-13b) connected to one of the buffers (11a-13a) and connected to the buffers (11b-13b) in which the data lines (D'7-D'o) are serially connected to the input terminals. 11a-13a and the data lines K7-Ko and M7-Mo of the buffers 11b-13b having the input lines in the order of common connection to each other to form a pair, and the buffers 13a, ( 13b) by connecting the data line D7-Do to the output data line D7-Do through the masking logic unit 14. FIGS. 3 to 6 are attached to the operation and effect of the present invention. Detailed description with reference to the following.

The input terminals A7-Ao of the buffer 11a are sequentially connected to the data lines D'6-D'7, and the output terminals B7-Bo of the buffer 11a are the data lines K7-Ko. The data lines D'6-D'7 are rotated to the data lines K7-Ko, respectively.

By passing through the buffer 12a in this manner, two bits are rotated, and again four bits are rotated through the buffer 13a.

On the other hand, the buffers 11b-13b serve to pass each input as it is, and the outputs of the six buffers 11a-13a and 11b-13b have three states, and the buffers 11a, 11b, and ( 12a, 12b) and (13a, 13b) have enable terminals (eo-e2) having opposite logics to prevent data collisions.

Here, based on the above description and explaining that bit rotate data of 1 and 0.1 is applied to the enable terminals eo-e2 of the buffers 11a-13a and 11b-13b as an example, the buffer 11a ) Is enabled while the buffer 11b is disabled, so that the data d'7-d'o on the data line D'7-D'o is not allowed to the buffer 11a. 1 bit is rotated and data on the data line K7-Ko is output in the order of d'6-d'o, d'7, and buffer 12a is disabled while buffer 12a is enabled. The data d'6-d'o and d'7 are loaded onto the data line M7-Mo without being rotated through the buffer 12a. In addition, since the buffer 13a is enabled and the buffer 13b is disabled, the 1-bit shifted data d'6-d'o and d'7 on the data line M7-Mo are again stored in the buffer ( 4 bits rotated through 13a) and then d'2, d'1, d'o, d'7, d'6, d'5, d'4, and d'3 on the data line (D7-Do). After rearranging and loading, the input data d7-do is rotated 5 bits to the left and outputted on the data line D7-Do. The data loaded on the data line D7-Do is output to the data line D ″ 7-D ″ o through the masking logic unit 14 performing a logic operation as shown in the third diagram. In this way, the input data can be rotated left and right and shifted left and right.

4 and 5 are tables and one embodiment showing conditions for converting right (R) shift data into left (L) shift data, and FIG. 6 is a simplified embodiment showing only the function of left shift. to be.

As described in detail above, the present invention has the advantage that it can be applied to a system requiring high-speed data processing because the data can be processed only through the gate circuit without using a clock signal in rotating and shifting data. .

Claims (1)

The data lines D'7-D'o are rotated 1 bit, 2 bits, and 4 bits, respectively, to the serially connected buffers 11a-13a, and to the serially connected buffers 11b-13b. The data lines K7-Ko and M7-Mo of the buffers 11a-13a, 11a-13a, and 11b-13b, which are mutually exclusive buffering operations, are connected one by one. And the data lines D7-Do of the buffers 11a and 13b are connected to the output data lines D "7-D" o through the masking logic unit 14. High speed shift and rotate system.