SU1605211A1 - Apparatus for program control of object - Google Patents

Abstract

The invention relates to automation and computing and can be used in the design of automatic control systems, including various complex objects, such as automated and robotic systems and flexible technological systems consisting of groups of inhomogeneous equipment, including machine tools, robots, test sets. etc., working relative to each other in asynchronous mode for different local programs. The invention allows to expand the functionality of the device, increase its speed in a multiprogram mode and reduce the laboriousness of developing control programs. For this purpose, a device for programmatically controlling an object, which contains a block 1 of sensors, a block 2 of comparison, a block 4 of program processing, a block 5 of program memory and data, a block 8 of actuators, a bus 9 of monitored parameters, a bus 10 of control actions, is entered 3 request processing, block 7 for selective control of actuators, containing a register, a gate-pulse selector, a group of multiplexers on three outputs, a group of D-flip-flops with set and reset inputs, a group of switching elements. 1 hp f-ly, 5 ill.

Description

The invention relates to automation and computing and can be used in the design of systems for automatic control of objects, including, for example, automated and robotic complexes and flexible automated technological systems consisting of groups of inhomogeneous equipment, including including machine tools, robots, test setups, etc., working relative to each other in asynchronous mode according to different local programs.

The purpose of the invention is to increase the speed of the device in multiprogram mode.

FIG. 1 shows a block diagram of the proposed device; Fig 2 - diagram of the sensor unit; FIG. 3 is a block diagram of a comparison block; FIG. 4 is a block diagram of a program processing block; FIG. 3 is a block diagram of a selective actuator control unit.

The device (1) contains a sensor unit 1, a comparison unit 2, a request processing unit 3, a program processing unit 4, a program and data storage unit 5, the program processing unit 4 and a program and data storage unit 5 constituting the control unit 6, block 7 of selective control of actuators, block 8 of executive mechanisms, bus 9 of monitored parameters, bus 10 of control actions, group 11 of inputs and outputs connecting request processing block 3 and program processing block 4, address bus 12, pin 13 data bus 14 management.

The sensor unit (FIG. 2) consists of a group of 15 two-position switch1; and

25 jn

or 0

.c 5

One-dimensional elements such as toggle switches, limit switches, relay contacts, etc. At the position of the switches shown in the diagram, the B, ... outputs of block 1 will receive a logical zero signal. In the lower position of any of the switches, the signal of the logical unit will be sent to the corresponding output.

The comparison unit (Fig. 3) contains ha of the comparison circuits 16 with two n and discharge codes for the DB and Bc inputs, the Group BD input forms a bus 9 of monitored parameters “To the group input and EE, the register output 17 is connected. Register 17 contains the group input D, which forms the bus 13 of the device data, as well as the address input C of the selection of the register, which belongs to the bus 12 of the addresses of the device; and the control input W for writing information to the register from the bus 13 of the data that relates to the control bus 14 of the device; Unit 2 of comparison, depending on the specific x claims may contain several (in general on the number of monitored parameters) of these nodes, as shown in fig.Z outputs C, o. "to the comparison circuit comparing the image of the output unit group

The program processing unit 4 (FIG. 4) contains the central processing element 18 together with the support means — the system controller 19, the clock generator 20, the interrupt controller 21, the address bus buffer 22. In addition, in FIG. 4 shows the timer 23, the decoder 24 devices. Input-output, inputs IR., "OIR interrupt.

Inputs-outputs DO..D of the system controller 19 form a bus 13 of the device data (FIG. 0, outputs of the system controller; M — read AW, wipe, M — write to memory,

Writing to external devices, K-reader of external devices, IWTA — confirming the ability to service a request — form the device control bus 14 (Fig. 1).

 buffer 11 address bus together with the outputs of the decoder 24 I / O devices form a bus 12 addresses about

The selective actuator control unit 7 (Fig. 5) contains a register 25, a group of 26 multi-conversion. Information from the on-off sensors of unit 1 enters the first group of inputs of the request-processing unit 3. The information on the bus 9 controlled parameters is fed to the first inputs D of the comparison circuit 16 (FIG. 3) of the comparison block 2 This information is compared with the information recorded in registers 17o in the case of equal codes on two inputs DA and Dg, the circuit we have 16 comparisons at its output, according to the corresponding signal (for example

plexors, gate pulse selector 27, 15 logical units). In this way.

a group of 28 D-flip-flops, a group of 29 switching elements made on transistors 30, p ..30 „„ Block 7 also includes limiting resistors 31

if register 17 registers not the expected value of any parameter and if the given parameter of the control object reaches this

31 and a group of diodes 32, ... 32 ", 20 values, then a comparison circuit 16, Fig 5 shows the input entry Wj of the register 25, individual address inputs CS.o.CS, outputs of the selective control unit 7 actuators are connected to count-25 nation yes-no to lecturers of corresponding transistors

The device works as follows

The information coming from the control object is generally of two types: discrete information, which characterizes the state of the object or its individual elements (on-off, forward-backward, left-right, etc.), represent which is possible with the help of dat30

gives a signal indicating the presence of such a situation. The signals at the outputs of C. C and C circuits are essentially discrete information.

and have the same

the nature of the signals at the outputs of the sensor block 1

The signals from the outputs of the comparison unit 2 are sent to the corresponding group of input requests of the interrupt. Of the request processing unit 3.

The requests for requests for blocking requests processing block have a different level of priorities. Depending on the specific task, certain outputs of the sensor unit 1 and the comparison unit 2 should be connected to the inputs of the request processing unit 3 with the corresponding priority. The selection of the mode 40 of the operation of the request processing unit 3 is also decided for a specific task.

35

as well as analog, reflecting the quantitative side of any process (heating temperature, voltage, mechanical force, etc.). As a rule, for further processing, and in particular for processing on an EBM, such an analogue The information inquiries of requests for blockings in the processing unit of requests are of different priorities. Depending on the specific task, certain outputs of the sensor unit 1 and the comparison bank 2 should be connected to the input of the request processing unit 3 with the corresponding priority. The selection of the mode 40 of the operation of the request processing unit 3 is also decided for a specific task.

When a request signal is received, any of the inputs to the block

- r - X1r - r --- tf iJUJCLfi nn fid. JIIUWUH on OLD OJIOK

is cretized (compiled) when processing requests, it is analyzed

power of analog-digital converter, at the output of which a code is formed, equivalent to the numerical value of the corresponding analog value

Therefore, in the proposed device, the sensor unit 1 (FIG. 1) perceives the information of the first type (discrete) type on / off, yes, and the comparison unit 2 on the bus 9 of monitored parameters perceives the information of the second type — analog, but converted into some code as a result analog-to-digital priority If currently there are no requests with a higher priority, the request processing block at one of the outputs generates a signal

50 rsha, which is supplied to one of the IR, ... IR inputs of the interrupt controller 21 of the program processing block 4 (FIG. 4). If this signal is for a given time for the controller 21

JJ snaps has the highest priority, the latter generates an OT signal (interrupt request) for the central processing element 18 (Fig. 4). IGGA signal (request resolution

d

smooth transformation. Information from the on-off sensors of unit 1 enters the first group of inputs of the request-processing unit 3. The information on the bus 9 of monitored parameters is fed to the first inputs D of the comparison circuit 16 (FIG. 3) of the comparison block 2 This information is compared with the information previously recorded in the registers 17 ° In case of equality of the codes at the two inputs DA and Dg, the comparison circuit 16 Wits Corresponding signal (for example.

15 logical units). In this way.

logical unit). In this way.

if some expected value of a parameter is written to register 17 and if this parameter of the control object reaches this

values, then the circuit 16 is compared with the type of yes-no

gives a signal indicating the presence of such a situation. The signals at the outputs of C. C and C comparison circuits are essentially discrete information that have the same

the nature of the signals at the outputs of the sensor block 1

The signals from the outputs of the comparison unit 2 are sent to the corresponding group of input requests of the interrupt. Of the request processing unit 3.

The requests for requests for blocking requests processing block have a different level; high priority. Depending on the specific task, certain outputs of the sensor unit 1 and the comparison unit 2 should be connected to the inputs of the request processing unit 3 with the corresponding priority. The selection of the mode of operation of the request processing block 3 is also decided with reference to a specific task.

Upon receipt of a request for resolution signal to any of the inputs, block 3

tf iJUJCLfi nn fid. JIIUWUH on OLD OJIOK

request processing analyze it

priority If at present there are no requests with a higher priority, the request processing block on one of the outputs generates a signal that stops at one of the IR, ... IR inputs of the interrupt controller 21 of the program processing block 4 (Fig 4) . If this signal for the given time for the interrupt controller 21 has the highest priority, the latter generates an O signal (interrupt request) for the central processing element 18 (Fig. 4). IGGA signal (request resolution.

 sixteen

interrupt resolution) from the system controller 19 (FIG. 4), the crash controller 21 (FIG. 4) sends the first byte of the CALL command (transition to the program) to the data bus 13, and the CAS ... j inputs of the query processing unit 3 ( FIG. 4) - the number of the supervised controller inside the processing unit for, POSOV “With the arrival of subsequent signals

; The INTA input of the processing unit 3 (requests, the selected slave controller, has the same number on the CAS ,,. CASj lines) sends 2 bytes of the address of the routing processing routine to the bus 13 data (or, in other words, the request processing interrupt from the control object).

The signaling of the IHTA control bus 14 is provided to the bus 13 of this interrupt vector. A prejudicion vector is an address or pointer defining a certain entry point into the program for treating off trespasses. How to proceed with the execution of the chipping program, which was started by the breaking vector, the return address is placed on the stack. The last action is performed in the same way as when the subroutine is accessed. Perceived on the data bus 13, the chipping vector, the central processing unit 18 places this address on the device address bus 12 and reads the memory cell of the program memory and data block 5 (FIG. 1) with this address. At this address there can be some control word, which is then transmitted via bus 13 of the device data to block 7 for selective control of the actuators. So, for example, even if earlier the command for switching on the relay number K was sent to block 7 of the selective control of the executive mechanism. As a result, an element of the object in the accepted position was received, and a request was sent to the request processing block 3. The request processing block formed a distortion vector , which entered the block 4 processing programs. The program processing unit has entered the processing mode.

given perryshan. At the address specified in this interrupt vector, in block 5 of the memory, a program is stored that analyzes the situation and forms a control word with the requirement of

eight

Q

five

Q 5 o j. Q hp

five

switch the relay to number K. This control word enters the selective actuator control unit 7, and the necessary requirement is fulfilled.

In case any request from the control object requires execution after a certain period of time (technological delay), the operation of the device proceeds as follows. The address of this interrupt vector will be the service routine of the timer 23 of the program processing block 4. At the same time, timer 23 records the time delay code stored in the device data bus 13, which is stored in block 5 of program memory and data, the timer is started to count the pulses at the CLK input, and an internal interrupt request is generated by the IR input ( interrupt controller 21: At this request, the device generates a control word that enters the selective actuator control unit 7.

The program processing unit 4 and the program and data storage unit 5 constitute the control unit 6. In the general case, this control scheme is a complete technological product: a mini or micro computer, a technological controller based on computing tools, in particular microprocessor technology, etc., whose technical implementation is standard. ,

As already mentioned, a control word is fed from block 4 of processing programs to block 7 of selective control by executive mechanisms via the device data bus 13 Since, in general, the format of the control word, and in other words, the number of actuators, can exceed the data bus width (for example, in this particular case, the data bus width is 8, however, the actuators may be greater, for example, 8,16,24, etc.), then in the register 25 (Fig. 5) the control word on the data bus 13 is entered byte by byte The operation of individual CS .... CSn signals of the device address bus 12 (selection of the area inside the register) and the signal Vp of the device control bus 14 The parallel control word thus formed at the output of the register 25 is fed to the corresponding information inputs D of the multiplexer group 26 Individual signal at the input V of the multiplexers allows the passage of information from the information inputs of the D multiplexers to one of the three outputs. The choice of the required output is carried out using a combination of codes to the address s inputs A and A. multiplexers

In accordance with this combination, one of the modes of operation of the block 7 is selected. In the selective setting mode (00), the input code (control word) passes to the setting inputs S of the flip-flops 28o 1 .., 28. p. Those bits of the input code, where the unit was recorded, set the corresponding triggers to the single state on inputs S, the state of the remaining triggers remains unchanged.

ie selective reset (10) input

The code passes to the third multiplexer outputs. Those bits of the input code, where the unit was recorded, by the PV inputs. reset the corresponding triggers. The state of the remaining triggers remains unchanged. Thus, in order to set or reset any trigger, it is sufficient to write one to the corresponding control code bit, and to all the others - zero. In the mode of non-selective reception (01) the input code is fed from the second output of the multiplexers to the D-inputs of the trigger and the signal from the output of the selector 27 strobe pulse

X CS A,. BUT,

W.

When entering the inputs C, information is recorded in these triggers.

Depending on the level of the logic signal at the outputs of the flip-flops 28, the transistors 30 are in the open or closed state, switching-off actuators such as relays or electromagnets are turned on and off.

Thus, the control of the actuators of the block 8 () is performed using the control word, which is recorded in an intermediate register 25 (see Fig. 5) through the input data threshold of the device for several cycles of operation, and then

d 0

25

thirty

35

40

45

50

five

at the next cycle, multiplexers are written in parallel to some register formed by .28оPo triggers. Let all triggers be set to the initial state (logic zero level at the outputs of all triggers). In this case, the control word code will contain all zeroes, and the operation mode will be Next: 01 - non-selective installation

By this command, all eight triggers are set to the zero state, and the eight corresponding actuators will be disabled. Let now, according to the program (or programs), it is necessary to make the installation of the first set of triggers into a single state. In this case, it is necessary. It is necessary to use mode 00 for selective installation, and the command code will be 11110000 00.

In accordance with this code, the commands on the S-inputs of the first four triggers of the incoming T signals, setting them to one state. Now, according to the program, it is necessary to set the four remaining triggers to one state. If it were not for the selective setting and reset means, the control word must it would be 11111111, since the first four triggers must receive a signal of their installation again, so as not to change their previous state, and a new installation signal must arrive at the remaining triggers. In this case, when there are no means for selective installation and reset, when addressing to individual triggers or groups of triggers, to change their state, it is necessary to take into account each time the current state of all without exclusion of triggers, i.e. data exchange between local programs, which allows each local program to take into account the actions of other programs. In our case, the command code will look like this: 0000 1111 00.

Thus, the advantages of the proposed control of actuators using the selective control unit are particularly noticeable when working with several groups of actuators in asynchronous

mode on several local non-BHCHMijiM programs

Claims (1)

Invention Formula 1 o Device for software control of an object, containing a comparison unit connected by information inputs to a bus of monitored parameters, a sensor block, a program memory and data block, a program processing block, an actuator block, which is different in that the device introduced a request processing unit and a selective actuator control unit; the outputs of the sensor unit and the comparator unit are connected to the corresponding inputs of the request of the partitions of the request processing unit The group of information outputs and the group of expansion inputs of which are connected to the corresponding group of interrupt inputs and the group of outputs of the expansion of the program processing block, the group of address outputs of the program processing block is connected to the groups of address inputs of the block of matches, the request processing block, the block of program memory and data and a block of selective control of executive mechanisms, a group of inputs / outputs of the data of the program processing unit is connected to. groups of inputs, data outputs of the request processing block, block program and data memory, as well as to the data input groups of the comparison unit and selective actuator control unit, the output group of the interrupt control, writing and reading the program processing block is connected to the groups of the corresponding write control inputs of the block, the comparison, the corresponding control input groups interrupting programs and data of the request processing block, program and data memory block, and block write control input selective control of actuators, a group of outputs of commands of the block of selective control of actuators of coe piHena with a group of information inputs of the block of actuators 2o The device according to claim 1, characterized in that the selective control unit of the actuating mechanisms contains a register, a gate-selector selector, a group of multiplexers for three outputs, a group of D-flip-flops with installation and reset inputs, a group of diodes, a group of limiting resistors and a group of switching elements, implemented on transistors, the emitters of which are connected, the collectors form a group of outputs of the block commands, and are also connected via counter-connected diodes to the power source, the direct outputs of D-flip-flops are connected through boundaries transistors with bases of transistors, the first outputs of the group multiplexers are connected to the installation inputs of the corresponding group triggers, the second outputs of the group multiplexers are connected to the information inputs of the corresponding D-triggers group, the third outputs of the group multiplexers are connected to the reset inputs of the corresponding trigger group data inputs group multiplexers are connected to the corresponding register outputs, the group of information inputs of the register is connected to the group of data inputs of the block, the inputs are resolved neither the register, the address inputs and the resolution inputs of the gate-pulse selector, as well as the address inputs and resolution inputs of the group multiplexers are connected to the corresponding address inputs of the block, the register record input is connected to the record input of the gate-pulse selector and connected to the block recording control input , the output of the selector-iTopa strobe-pulse is connected to the synchronization inputs of the D-flip-flops of the group. dk FIG. 2 "ABOUT 7 - ; 2 - I h G / 77 R % eJ lso trol rryphony cucjrreiiHbiu controller operesno bus buffer timer (Rig. :; sJeaiutppaTTrai 13 1and 32.1 26 5