JPH03108040A - Data storage device with improved same data repeated write mechanism - Google Patents

Abstract

PURPOSE:To shorten the time required for write operation by providing a representative data holding means and substituting one write operation to the representative data holding means for write of the same data to respective storage positions of a block. CONSTITUTION:When an operation code 4a of the instruction inputted to an instruction register 4 indicates that the same data should be stored in a series of elements in a vector register 1, a control circuit 15 updates contents of a representative state register 2 selected at present to '1' at the time of the storing operation of a representative register 3. Next, data from a data source 9 is stored in the representative register 3 selected at present through a bus 17, and selectors 10 and 11 are controlled to select a count up/down value 4. An element address 4b and an element count 4c are increased/reduced by 4. Thus, storage to one representative data register 3 is substituted for successive storage to four elements to shorten the operation time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data storage devices, and more particularly to a mechanism for simplifying the operation of writing the same data to a series of storage locations. The invention is particularly suitable for intermediate storage devices used for processing vector data, for example so-called vector registers.

[Conventional technology]

In many fields of use, particularly in scientific calculations, database processing, and the like, information processing devices are required to process larger amounts of data in shorter times.

For such processing, it is important to process the data flow between the main memory and the arithmetic unit at high speed. In order to achieve the above objective in vector processing, which performs the same operation on a series of data, scientific computers, commonly called supercomputers, have a high-speed intermediate memory called a vector register between the main memory and the arithmetic unit. It is common to provide equipment. The vector data in the main memory is first transferred to the vector register and then supplied to the arithmetic unit.The output of the arithmetic unit is stored in the vector register and then transferred to the main memory or other is supplied to the arithmetic unit for calculation. Vector data consists of a large number of elemental data, and therefore a vector register consists of a large number of individually addressable elemental registers.

In high-speed processing storage devices with a large number of individually addressable storage locations, such as vector registers, for writing, reading, or initializing, essentially
It is necessary to access individual storage locations sequentially.

As an improvement, the patent application filed in 1983 by the same applicant as the present application
-330237 is.

We propose a status register that is provided corresponding to each block of vector registers and indicates that all element registers in that block have been cleared to zero or reset to a predetermined value. This state register is set to a predetermined state instead of clearing or resetting the individual element registers in the corresponding block, thereby reducing the time required to clear or reset the vector register.

[Problem to be solved by the invention]

In data array processing such as vector processing, particularly in processing large-scale data arrays, arbitrarily specified data of the same value is often used repeatedly many times. In such a case, according to the conventional method, each storage location is
The same data must be written to them sequentially by specifying one address. The above-mentioned clearing or resetting mechanism uses a predetermined special value (all N Q #
j, all II II I+, etc.), and cannot be used to set arbitrarily specified values or unknown values where only the data source is specified.

An object of the invention is to simplify the writing of the same data to all storage locations within a block, regardless of the value.

[Means to solve the problem]

According to the present invention, in addition to the representative state holding means, representative data holding means is provided corresponding to each block. If the same data is to be written to all memory locations in a certain block, this data is written to the corresponding representative data holding means instead of each memory location, and
setting the corresponding representative state holding means to the first state; otherwise updating the contents of at least the designated storage locations such that each storage location within the block holds respective data; , as six representative data holding means provided with write control means for setting the corresponding representative state holding means to the second state.

Instead of providing dedicated storage means, one predetermined storage location within each block may be used.

The write control means stores the corresponding representative data in response to the fact that the corresponding representative state holding means is in the first state when only some storage locations in a certain block are designated for writing. Preferably, initialization means are provided for writing the contents of the holding means in this block at least to storage locations that are not intended to be updated.

Regarding reading, in response to the state of the representative state holding means corresponding to the block to which the specified storage location belongs, if it is in the first state, the contents of the corresponding representative data holding means are read out, In the case of two states, it is preferable to provide a read control means for reading out the contents of the designated storage location.

[Effect]

In the present invention, when the same data is to be written to all storage elements in a certain block, the data is written to the representative data holding means, and writing to each storage location is omitted. Therefore, the processing time for instructions that write the same data to multiple consecutive storage locations is significantly reduced. When writing of this type is performed, the representative state holding means is set to the first state, and when writing of another type is performed, the representative state holding means is set to the second state. Therefore, the representative state holding means indicates whether the contents of the representative data holding means or the contents of each storage location are valid, thereby making it possible to know the location of the correct data.

If one of the storage locations in each block is used as representative data holding means, the amount of hardware can be reduced.

According to such a structure, in a block whose corresponding representative state holding means is in the first state, the data held at each storage location is invalid. When writing new data only to some memory locations within such a block, the initialization means of the present invention converts invalid data in storage locations that are not updated within this block to valid data in the representative data holding means. , thereby ensuring that each storage location within the block holds valid data after the write operation.

Further, the read control means in the present invention reads the contents of the corresponding representative data holding means when the corresponding representative state holding means is in the first state, and reads out the contents of the corresponding representative data holding means when the corresponding representative data holding means is in the second state. Read the contents, thereby ensuring that valid data is always output.

〔Example〕

In the following, the invention will be detailed as applied to vector registers.

In the embodiment shown in FIG. 1, the vector register 1 is
It consists of 256 element registers (hereinafter simply referred to as elements) having consecutive addresses, and four elements having consecutive addresses form one block. Therefore, there are 64 element blocks. Representative status register group 2
and representative data register group 3 each consist of 64 registers, which is the same as the number of blocks, and each of these two groups of registers has the address that specifies the element of vector register 1 excluding the least significant two bits. Therefore, the element block, representative state register, and representative data register are associated in a one-to-one relationship. Each representative data register has the same length as the elements of vector register 1, and is used to store the same data when the same data is to be stored in all elements in the corresponding block. Each representative state register has a length of 1 bit and holds 1 if the corresponding representative data register holds valid data on behalf of all elements in the block, and 0 otherwise. ” to be retained.

The instruction register 4 holds the instruction being executed.

A loop-connected adder 5 and an element address register 6 form an element address increment circuit that successively supplies different element addresses, and a loop-connected subtracter 7
and element count register 8 form an element number decrement circuit that indicates the number of remaining elements to be accessed. The data source 9 generally represents the source of data to be stored in the vector register 1, for example a group of general purpose registers. Selectors 10 and 11 are each adder 5
The selector 12 selects either the data source 9 or the representative data register group 3 as the source of input data to the vector register 1. , selector 13 selects vector register 1 or representative data register group 3 as a source of data to be sent as vector register output.
The selector 14 selects an element address from the element address register 6 or an initialization address from the control circuit 15, which will be described later, as information for specifying the element in the vector register 1.

The control circuit 15 receives the element address from the element address register 6 and the element callan 1 from the element count register 8.
- and a state instruction bit from a selected representative state register in representative state register group 2, and generates various control signals. The main control signals are a signal p for controlling selectors 1o and 11, a value q to be set in the selected representative register, an output selection signal for controlling selector 13, and a signal for performing block initialization, which will be described later. These are an initialization address and a control signal to selector 12.14.

The function of the control circuit 5 will be explained in more detail later.

The operation code 4a of the instruction that has just entered the instruction register 4 is
Assume that it indicates that the same data should be stored in a series of elements in vector register 1.

The element address field 4b of this instruction indicates the start address N of this series of elements, the element count field 4c indicates the number M of this series of elements, and the data source field 4d indicates one position in the data source 9. (For example, -) of a general-purpose register. The first element address N is transferred to the element address register 6, and the number of elements M is transferred to the element count register 8. The contents of the element address register 6 are repeatedly incremented by 111 It or '4'' selected by the selector 10 by the adder 5 to designate the elements in the vector register 1 one by one. The contents of 6, except for its two least significant bits, are sent to path 16 and used as addresses for representative state register group 2 and representative data register group 3.

The contents of the element count register 8 are iteratively decremented by the subtractor 7 by '1' or It 4 II selected by the selector 11 to indicate the number of unprocessed elements.

Control circuit 15 executes the specified storage operation as described below.

FIG. 2 summarizes the storage control function of the control circuit 15. Cases A to 3 are cases in which the current contents of the selected representative state register are 11071, and at this time, each element in the block to which the designated element belongs holds valid data. In case 1, the element address is "n4" (n is 0 or a positive integer), which points to the first element in the block, and the count (content of element count register 8) is the number of elements that make up the block. The number is equal to or greater than "4". These conditions indicate that the same data should be stored in all elements in this block, and at this time, the representative data register storage operation, which is a feature of the present invention, is performed. The control circuit 15 updates the contents of the currently selected representative state register to 1'', stores the data from the data source 9 in the currently selected representative data register via the path 17, and then updates the contents of the currently selected representative state register to 1''. and 11 to select the count increment/decrement value "4", and increment and decrement the element address and element count by 4", respectively. Thus, 4
Sequential storage into multiple elements is replaced by storage into one representative data register, reducing operating time.

Case 2 is a case where the element address points to the first element in the block, but the count is less than "4", so storage of the same data ends in the middle of the block, and Case 3
is a case where the element address does not point to the first element within the block, so an intermediate element within the block is specified, and
In these cases, data is stored in the single element currently specified. The control circuit 15 maintains the state of the selected representative state register at 0'', stores the data from the data source 9 via the path 18 in the selected element in the vector register 1, and then
and 11 to select the increment/decrement value "1", and increment and decrement the element address and element count by 1", respectively. Under normal conditions, the selector 12 selects path 18, and the selector 14 selects the element address and element count by 1". Select path 2o from register 6.

Cases 4 to 6 are cases where the current content of the selected representative state register is '1'', and in this case, the data held by each element in the block to which the specified element belongs is invalid and is not valid. The data is held in the selected representative data register.

In case 4, the element address and count indicate that the same data should be stored in all elements in this block, as in case 1.

The control circuit 15 stores data in the representative data register and increments and decrements the element address and element count by "4 II" in the same manner as in case 1. However, the contents of the 1 representative state register are #1. It is kept at j+.

In cases 5 and 6, as in cases 2 and 3, data from the data source is stored in the currently selected element. However, this time, as indicated by the value H171 in the representative state register, the contents of all elements in the block are invalid, and instead the contents of the representative data register are valid. Therefore, the contents of elements other than the designated element must be replaced with the contents of the representative data register. For this purpose, block initialization is performed first. That is, the control circuit 15 switches the selector 12 to select the path 19 from the representative data register group 3, and also switches the selector 14 to select the path for the initialization address. Next, the control circuit 15 sequentially generates addresses of successive elements within the five blocks by modifying the lowest two bits of the element address data received from the element address register 6, and sends these to the initialization address bus. , thus transferring the contents of the currently selected representative data register to all elements within this block. Thereafter, control circuit 15 restores selectors 12 and 14 to store the data from the data source on path 18 into the element pointed to by the element address on path 20, and then restores the element address and element count. Increment and decrement by II 1 #, respectively, and finally update the contents of the selected representative state register to mI OII.

Thereafter, any one of cases 1 to 6 is repeated depending on the input condition, and when the count reaches 1101+, the execution of this instruction is completed.

In a read operation, the leading element address and element count are entered into element address register 6 and element count register 8, respectively. As in the storage operation, one element in vector register 1, one representative state register in representative state register group 2, and one representative data register in representative data register group 3 are assigned to element address registers. 6
selected according to the content of The control circuit 15 checks the contents of the selected representative state register 1, and if it is '0'', selects the output of the vector register 1, and if it 1 n, selects the output of the representative data register group 3. The selector 13 is controlled by an output selection signal.The element address increment value and the element count decrement value are always 111 II.

FIG. 3 shows another embodiment. In this example,
Instead of providing a special representative data register group 3, the leading element within each block is used as a representative data register. However, instead of the first element, as long as you predetermine
It is clear that elements in any other positions can be used as representative data registers.

In FIG. 3, parts that do not require changes to the mechanism in FIG. 1 are omitted. The representative data register group 3 and selector 13 in FIG. A mask circuit 31 is added. The storage control function of control circuit 32 differs from that shown in FIG. 2 with respect to storage in the representative data register in cases 1 and 4 and block initialization in cases 5 and 6, as described below.

In cases 1 and 4, the control circuit 32 stores the data from the data source in the element specified by the element address, increments the element address and element count by II 4 II, and increments the element address and element count, respectively, as in the other cases. Decrement.

In these cases, the element address points to the first element within the block, so the first element naturally functions as the representative data register.

In block initialization in cases 5 and 6, the control circuit 32 first transfers the contents of the leading element (representative data register) in the corresponding block to the representative data save register 30.
Read to. The contents of this register 3o are then sequentially transferred to the second and subsequent elements within this block, thereby realizing block initialization.

The read operation in the embodiment of FIG. 3 is the same as in the embodiment of FIG. 1 insofar as the selected representative status register indicates II OUP. At this time, the mask circuit 31 passes all bits as they are. When the selected representative state register indicates Jl 11j, the control circuit 32 controls the mask circuit 31 by the control signal t to force the least significant two pits 1 to dI OOn of the element address data. Therefore, instead of the contents of the specified element, valid data in the first element (representative data register) in the block to which the element belongs is output.

The block size can be chosen appropriately, and the control function shown in FIG. 2 can be applied to any block size by replacing the number It 4 II in the entry with the number of elements making up the block. One entire vector register may be treated as one block.

Block initialization can also be limited to only those elements that actually require initialization. It is easy to use the specified element address and element count to identify elements that are not scheduled to be updated and issue initialization addresses only to them. Although this modification complicates the logic configuration of the control circuit, it can further reduce processing time.

It is clear that the present invention is applicable to systems having multiple vector registers, and is also applicable to a wide range of general storage devices.

〔Effect of the invention〕

According to the present invention, by installing the representative data holding means, the operation of sequentially writing the same data to each storage location in a block is replaced by a single writing operation to the representative data holding means. The time spent on write operations is significantly reduced, and the amount of hardware increases only slightly, especially if specific storage locations within each block are used as representative data holding means.

Appropriate block initialization means and successive control means solve the problem regarding the mismatch between the contents of the representative data holding means and the contents of the storage location.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a vector register system according to the present invention, and FIG.
FIG. 3 is a diagram summarizing the storage control function of the control circuit in the figure, and FIG. 3 is a block diagram showing another embodiment of the vector register system according to the present invention. 1... Vector register, 2... Representative status register group, 3... Representative data register group, 6... Element address register, 12... Selector for selecting representative data for block initialization, 13...Selector that selects a vector register or representative data register as an output data source, 14...Selector that selects an element address or initialization address, 15.32...Control circuit, 3
o: A save register that initializes representative data in a specific element, and 31: A mask circuit that converts a specified element address into an element address of a specific element that holds representative data.

Claims (1)

[Scope of Claims] 1. Data storage means having a plurality of storage locations that can be specified independently, and representative data holding means and representative state holding means provided corresponding to each block consisting of a certain number of storage locations. If the same data is to be written to all memory locations in a certain block, the data is written to the corresponding representative data holding means instead of each memory location, and the corresponding representative state holding means is also written to the corresponding representative state holding means. otherwise, updates the contents of at least the designated storage location and sets the corresponding representative state holding means so that each storage location in the block holds its own data. and write control means for setting the data storage device to a second state. 2. The data storage device according to claim 1, wherein one predetermined storage location within each block is used as representative data holding means corresponding to that block. 3. In claim 1 or 2, the write control means determines that the corresponding representative state holding means is in the first state when only some storage locations in a certain block are designated for writing. A data storage device including initialization means for responsively writing the contents of the corresponding representative data holding means to at least a storage location in this block which is not scheduled for update. 4. In claim 1, 2 or 3, further, in response to the state of the representative state holding means corresponding to the block to which the storage location designated for reading belongs, if the state is the first state, A data storage device comprising read control means for reading the contents of the representative data holding means, and reading the contents of the specified storage location if the state is the second state.