SU1531068A1 - Device for measuring a period - Google Patents

Abstract

This invention relates to a measurement technique. The goal is to simplify the device. For this, a quantized interval block 3, a controllable distributor of 6 pulses, and a group of input control buses 14 are introduced into it. The device also contains a threshold amplifier shaper 1, counting trigger 2, two counters 4 and 5 pulses, RS trigger 7, element 9, control block 8, input information bus 10, reference frequency bus 11, output bus 12, and output information group tires 13. 2 Il.

Description

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The invention relates to measurement techniques and can be used in information processing systems.

The purpose of the invention is to simplify the device.

Figure 1 shows the functional diagram of the device; figure 2 - timing diagram of the device.

The device for measuring the period contains a threshold amplifier driver 1, a counting trigger 2, a block

3 quantization intervals, counters

4 and 5 pulses, a controlled distributor of 6 pulses, an RS flip-flop 7, a control block 8, an AND 9 element, an input information bus 10, a reference frequency bus 11, an output bus 12 Reference, a group of output information buses 13 and a group of input tire

14 controls The inputs of the threshold amplifier 1 and the counting trigger 2 are connected respectively to the input information frequency 10 and 1 11 of the reference frequency.

Counter Information Outputs

5 impulses are connected to the first group of information inputs of control unit 8, the output of which is connected to the R input of the RS flip-flop 7, the direct output of which is connected to the first

the input element and 9.

The output of the threshold amplifier 1 is connected to the first input. Starting a controlled distributor

6 pulses and the first input of the interval quantization unit 3, the second input of which is connected to the input of the counting flip-flop 2, the output of which is connected to the third input of the interval quantizing unit 3, the first and second co-outputs; Secondly, they are connected respectively to the counting inputs of counters 5 and 4 pulses, and the pulse counter 5 is complete with preset, and informational; the outputs of the pulse counter 4 are connected to the information inputs of the pulse counter 5, the information outputs of which are connected to the group of output information buses 13 of the device, the group of input buses 14 of the control which are connected to the second group of information inputs of the block

In control, and the output bus 12 From

the count is connected to the output of the element 9, the second input of which is connected to the first output of the controlled distributor 6 pulses, the second and three

Q, Q

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These outputs are connected respectively to the input of information input to the pulse counter 5 and the combined zeroing input of the pulse counter 4 and the S input of the RS flip-flop 7, and the clock input of the controllable pulse distributor 6 is connected to the device frequency reference bus 11.

The interval quantization unit 3 contains the element OR 15 and the AND-NOT elements 16 and 17. The first input of the interval-quantization unit is connected to the first inputs of the OR elements 15 and AND-NOT 17.

The second and third inputs of the interval quantization block are connected to the second inputs of the OR 15 and NAND 17 elements, respectively, the output of the last of which is connected to the first input of the AND 16 element, the second input of which is connected to the output of the OR 15 element, and the output is connected to the first the output of the interval quantization unit, the second output of which is connected to the output of the element IS-NOT 17.

The controlled pulse distributor 6 contains a shift register 18, a D-flip-flop 19 and an OR-NOT element 20. The clock input of the D-flip-flop 19 is connected to the first input. The start of the controlled pulse distributor, the second clock input of which is connected to the clock input of the shift register 18, the first output of which is connected to the first input of the SHS-NOT 20 element and the first output of the controlled pulse distributor, the second output of which is connected to the second input of the OR-NOT 20 element and the second output of the shift register 18, the third output of which is connected to The output of the controlled Pulse distributor and the third input of the CM-HE 20 element, the output of which is connected to the information input of the shift register 18, the fourth output of which is connected to the single input of D- trigger 19, the D input of which is connected to the bus of the logical zero, and The direct output is connected to the input of the shift register register 18..

In this case, the control unit 8 is executed on the code comparison unit.

The device works as follows.

In the initial state, the counter of 4 pulses and the trigger 7 are zeroed.

The input information bus 10 receives an input signal with a fixed51

Noah .Hi-f; border frequencies and test- i iiioiUMH T;,;; : Amshpgudm (figa),

The threshold ycHniiTe, ni .- (jj:, - m1-; rosette 1 converts the input signal into a square-shaped pulse (Fig. 26) received at the first input of block 3 of the 1-st intervals. The interval between the midpoints of the pulses .

The pulses of the reference frequency f on the bus 11 arrive at the second input of the interval quantization unit 3 and the input of the counting trigger 2, from the output of which the pulses of frequency f / 2 arrive at the third input of the interval quantization unit 3.

During the pulse duration, at the output of the threshold amplifier 1, the first and second outputs of the interval quantization unit 3 generate pulses of the reference frequency f / 2 (Fig. 2b and d), which are fed to the counting inputs of the counters 5. and 4 pulses, respectively.

At the same time, a code corresponding to half the pulse duration appears in the indicated counters.

On the falling edge of the pulse at the output of the threshold amplifier 1, a pulse distributor 6 is triggered, and in the first, second and third outputs of which a single pulse is formed, shifted relative to each other by the value of the reference frequency period (FIG. g)

A pulse from the second output of the controlled distributor of 6 pulses (Fig. 2e) contents (code equal to half the duration of the first pulse of the input signal) of the counter of 4 pulses is rewritten into the counter of 5 pulses with a preset.

A pulse from the third output (Fig. 2g of the controlled distributor of 6 pulses zeroes the pulse counter 4, sets RS-flip-flop 7 (Fig.2i) to one state and unlocks the AND element.

In the pause between the pulses of the measured signal, the quantization pulses arrive only from the first output of the quantization block 3, and their frequency is equal to f. In this case, pulses go to the counter of 5 pulses, the number of which corresponds to the pause duration.

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During the duration of the second pulse of the measured signal, the pulses of frequency f / 2 arrive at the inputs of counters 4 and 5 of needles. As a result, at the end of the second pulse of the measured signal, the code 5 recorded in the counter 5 corresponds to the sum of the durations of the intervals half

Q of the first impulse, pause and half of the second impulse or the duration of the first period.

At the end of the second pulse, the controlled

5 dispenser 6 pulses.

The impulse from its first output steps through the unlocked element I 9 to the output bus 12 Countdown. With this impulse, the code of the measured period

0 from counter 5 can be rewritten from the output bus 13 to an external device.

If the input signal is attenuated at the output of the threshold amplifier 5 of the driver 1, which is set to a predetermined threshold level providing the required excess noise, the next pulse is not generated.

If the interval between the pulses of the measured signal S1 exceeds the maximum permissible value of the period, the code counted by the pulse number 5 will exceed the code of the number set on the control input buses 14, resulting in a pulse at the output of the control unit 8 (FIG. 2h) switching RS - trigger 7 to the zero state (Fig. 2i). This locks the element

Q and 9, which prohibits the arrival of a command. The countdown to the input bus 12, the absence of which does not allow reading information from the output information bus 13.

As the amplitude of the input signal increases, the first pulse from the output of the threshold amplifier 1 in the new series of pulses of the measured signal starts up the equalizer distributor 6 pulses and the operation of the device is repeated in accordance with the considered algorithm.

However, the first pulse from the output of the controlled distributor 6 pulses, corresponding to an unreliable measurement result, is output to the output bus 12. The countdown through the AND 9 element does not arrive, since the last

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locked by zero signal from the output of the RS-flip-flop 7.

The second impulse from the output of the controlled distributor 6 impulses of information about the duration of the first impulse of the series is copied from the impulse counter A to the impulse counter 5, as a result of which, if the permissible duration of the period is not exceeded, the unit level is removed from the output of the control unit 8.

By the third pulse from the output of the controlled distributor of 6 pulses, the RS flip-flop 7 switches to the single state, unlocking the AND 9 element, which is prepared to form the next command at its output. The countdown arrives at the output bus 12.

Further, the measurement process proceeds as described.

Claims (3)

1. A device for measuring a period, containing a threshold amplifier driver, a counting trigger, two pulse counters, an RS trigger, a control unit, an And element, an input data bus, a reference frequency bus, an output bus Reference and a group of output information buses, an ethsonone bus the frequency is connected to the input of the counting trigger, the input information bus is connected to the input of the threshold amplifier amplifier, the information outputs of the first counter are connected to the first group of information inputs of the control unit It is connected to the R input of the RS flip-flop, the direct output of which is connected to the first input of the AND element, characterized in that, for the purpose of simplification, an interval quantization block, a controlled pulse distributor and a group of input control buses are additionally introduced, and the output the threshold amplifier-amplifier is connected to the first input of the controlled pulse distributor and the first input of the interval quantization unit, the second input of which is connected to the input of the counting trigger, the output of which is connected to the third input of the quantum Vani intervals, the first and second outputs of which are connected with 50 five about p g five 0 responsibly to the counting inputs of the first and second pulse counters, the first pulse counter is preset and the information outputs of the second counter are connected to the information inputs of the first counter, whose information outputs are connected to the group of output information buses of the device, the group of input control buses of which are connected to the second group of information inputs of the control unit, the output bus The countdown is connected to the output of the element I, the second input of which is connected to the first output of the control unit distributor pulses, second and third outputs of which are connected respectively to the input information input into the counter and to the combined reset input of the second counter and an 8-entry RS- flip-flop, a clock input and the second controllable pulse distributor coupled to the bus master unit frequency. 2 o Device according to claim 1, characterized in that the interval quantization unit contains two AND-NOT elements and an OR element, the first input of which is connected to the first input of the first AND-NE element and the first input of the interval quantizing unit, the second and third inputs of which are connected respectively, to the second inputs of the liJlH element and the first NAND element, the output of which is connected to the first input of the second NAND element, the second input of which is connected to the output of the OR element, and the output connected to the first output of the interval quantization unit, the second output of which Connected to the output of the first NAND element. 3. The device according to claim 1, characterized in that the controlled pulse distributor contains a shift register, an OR-NOT element and a D-flip-flop, the clock input of which is connected to the first input. The launch of the controlled pulse distributor, the second clock input of which is connected to the clock input the shift register, the first output of which is connected to the first input of the element OR NOT and the first output of the controlled pulse distributor, the second output of which is connected to the second input of the element OR-NOT and the second output of the shift register, the third output of which is connected to the third output of the controllable pulse distributor and the third input of the element Ш1И-НЕ, the output of which is connected to the information the input of the shift register, the fourth output of which is connected to the single input of the D-flip-flop, the input of which is connected to the logical zero bus, and the direct output is connected to the input of the zeroing of the shift register. fig.g