SU1529232A1 - System for interfacing terminal devices with computer - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated control systems for input-output data using input-output terminals, such as display stations, in real-time dialogue mode. The aim of the invention is to expand the class of tasks. The essence of the invention is that the input devices allow for interactive control of data input / output templates and input / output transaction parameters. The system contains a group terminal control device, a multiplex channel, an exchange control device, two code converters, random access memory, two switches, a buffer memory, direct access memory, a command encryption unit, a mode encoder. 2 hp f-ly, 8 ill.

Description

The invention relates to automation and computing and can be used in automated control systems for input-output data using input-output terminals, such as display stations, in real-time dialogue mode.

The purpose of the invention is to expand the class of tasks to be solved by providing interactive control of templates and parameters of data input / output transactions.

Figure 1 shows a block diagram of a system for interfacing terminals with a computer; 2 is a block diagram of an exchange control device; FIG. 3 is a block diagram of a command encryption unit; 4 is a block diagram of the first code converter; FIG. 3 is a block diagram of a second code converter; figure 6 - structural schema node synchronization; 7 -, the block diagram of the first address builder; FIG. 8 is a block diagram of a second address generator.

The system for interfacing the terminals with the computing machine (FIG.) Contains a group control device 1. terminal and, connected to terminal devices 2, buffer storage device 3, exchange control device 4, multiplex channel 5, command information block 6, mode encoder 7, direct memory

Tsistoda 9 first 9 and second 10 code converters, first 11 and second 12 switches and an operational storage device 13, first information 14 and first address 15 inputs and the first clock input 16 whose records are informational 17 and address 18, the second address driver (FIG. 8) contains the first 300 and second 301 registers, a delayed high-speed switch 302, accumulating adder 303 and a switch 304, as well as inputs and outputs 305-316 of the former generator,

(Estema works as follows.

System to interface terminals with

Dami and clock input 19 records sy-Q computer designed

topics one to twenty first

outputs 20-40 of control device 4

exchange, inputs and outputs of 41-96 blocks

siste

The exchange control device 4 (FIG. 2) forms an ax 97 and a first 98J second 99, a third 100 fourth 1019 sixth 102 (seventh 103 and fifth 104 nodes of synchronization, fourth 105, second 106, first 107 and third 108 elements OR, first 109 and the second software address formers, the first 11Ij second 112 and third 113 registers and the decoder 114d as well as the inputs and outputs 115-189 nodes of the device. / 5

The command encryption unit 6 (FIG. 3) includes a synchronization node 190, first 1915 second 192, third 193 registers, comparison circuit 194, shift register 195, first 196 and second 197 about associative memory node, delay element 198, address register 199 and memory node 200, as well as inputs and outputs of 201-225 block nodes

The first code converter 9 (figo4) contains a decoupler 226 code converters 227 code multiplexer 228s element 229 ea, cores 5 bbBi 230 and second 231 registers addr of data exchange between user and computer terminals and interactive control of input-output templates and process parameters

f5 input-output dan1x „

As the terminal devices 2 and the interface of which to the computer is provided by the system, television tabular-sign can be used.

2Q indicators.

The multiplex channel can be implemented according to the well-known (Kagan BSM Kanevsky MM. Digital computers and systems M „: Energia, 1975, s, 510, fig. 9о2).

The group control device 1 of the terminals in the system comprises the interface of terminal devices with channel 5 and can be implemented as a hardware group control device, which in this case, together with the RAM, forms a non-programmable display module.

Group device 1 provides an exchange with sixteen terminal devices 2 "Interfacing with channel 5 is carried out in accordance with the requirements of the input and output interface OST 4GO, 304" 000 and OST 4 "D0.304,

3.5

sa ;, the first 232 and second 233 registers

40 001. The exchange with channel 5 is carried out both in exclusive and multiplex modes, and the reading is always in, exclusive.

Selection of terminal device 2

and the entrances and exits of the 234-249 nodes transform.

The second transducer. Code 10 (FIG. 5) contains a demultiplexer 250, transducers 251 of the coding multiplex-d5 is carried out at the address received by the op 252, delay element 253, the first of the channel during the initial output 254 and the second 255 registers addresses first 256 and second 257 registers and inputs

Borki in accordance with the requirements of the input-output interface. In the process of its operation, the group I device 1 provides for the execution of the following channel commands: Pro-: I / O believe, record,

and outputs 258-273 converter nodes,

The synchronization node (6) form the generator 274. contacts, the counter 275 and the comparator 276, as well as the inputs and outputs 277-283 elements of the node.

The first address shaper 109 (FIG. 7) includes a switch 284 element SHSh 285 with a delay: a common adder 286 and a register 287 of the same inputs and outputs 288-299

accumulating - and so

for providing data exchange between user terminals and computers and interactive control of input / output patterns and process parameters

input-output data

As the terminal devices 2 and the interface of which to the computer is provided by the system, television tabular-sign can be used.

indicators.

The multiplex channel can be made according to the well-known (Kagan BsMts, Kanevsky MM. Digital computers and systems M „: Energia, 1975, p. 510, fig. 9о2).

The group control device 1 of the terminals in the system comprises the interface of the terminal devices with channel 5 and can be implemented as a hardware group control device, which in this case together with the TZI forms a non-programmable display module.

Group device 1 provides exchange with sixteen terminal devices 2 "Interfacing with channel 5 is carried out in accordance with the requirements of the input and output interface OST 4GO, 304" 000 and OST 4 "D0.304,

001. The exchange with channel 5 is carried out both in exclusive and in multiplexed modes, and the reading is always in, exclusive.

Selection of terminal device 2

carried out at the address coming out of the channel during the initial output.

5 is performed at the address coming from the channel during the initial output.

five

Borki in accordance with the requirements of the input-output interface. In the process of its operation, the group I device 1 provides for the execution of the following channel commands: Pro-: I / O believe, record,

Count, Major Refinement,

Erase / Write, Count Manual

input and draw

In addition to the indicated commands, the orders transmitted for the terminal devices 2 in the data are decoded.

At normal completion of the operation initiated by the terminal device 2, channel 5 of the status byte with the pointer terminated Channel terminated, WU finished, upon completion of the channel initiated, the status byte of the terminator terminated first, and then after completion of the operation on the terminal 2 - status byte with pointer CU ended.

The mode encoder 7 is designed to form start commands for channel input and output procedures transmitted to multiplex channel 5 and input initialization commands transmitted to instruction encoding unit 6 by input and output initialization signals sent to its inputs 79 and 42, respectively. In the course of its operation as part of the system, the encoder 7 transcodes the input and output initialization signals into I / O control commands in accordance with the communication interface of the peripheral and operational devices. th memory channels with the EU computer.

The system provides input mode and data view mode

In the data entry mode, the service procedure is performed at the initiative of the group device 1 after the next time the polling of the terminal devices 2 is revealed, the requirement to service one of them is revealed. In this case, the group device 1 sends to the channel 5 a service request by which the latter generates and transmits an input initialization signal to the input 79 of the encoder 7. The input command from output 80 generated by the encoder 7 is transmitted to input 81 of channel 5, and the input initialization command from output 82 is transmitted to input 83 of unit 6. At the input command, channel 5 receives from group device 1 to input 77 data entered from one of the terminal devices 2, and their transfer to the output 72. In the output mode, the initial sampling is initiated by the encoder 7 after entering the output signal of the initialization signal at input 42 from the output 21 of the device 4. In this case, the output command from the output 80 is transmitted to the input 81 of channel 5 by the encoder 7. By the output command, channel 5 organizes the reading of information from the memory

ten

20

25

j.

thirty

35

45

0

five

device 3 at input 77 and its transfer from output 76 to the input of group device 1.

Block 6 is designed to organize the processing of I / O commands, which are the service part of messages received from the first output 72 of channel 5. The service part of messages contains the identifier (physical address) of the terminal device 2, from which information is entered, and the identifier (code ) activated on the terminal device 2 function keys.

The storage device 3 is intended for the operative storage of information entered in the terminal devices 2 and data intended for output to the terminal devices 2,

Direct access memory 8 provides long-term storage of data organized as a sequential set of fixed-length records with direct organization, and a direct method for accessing this data set. The memory capacity of one record is equal to the memory capacity of the storage device 3.

The first code converter 9 is designed to convert binary-bit codes to DKII codes.

The second code converter 10 is used to convert DRC codes to binary bits.

The direct information connection of the system with the computer is provided through the common memory field of the random access memory 13, exchanged with which the computational Mishina performs on the output and the first information 17, the address 18 inputs and the clock input 19 of the system record (direct control channel) ,

The data entry-output process consists in sequentially performing one or several input-output operations from their next aggregate implemented in the system:

1. Data entry — in this case, from the twelfth output 31 of the device 4, a high level signal is fed to the input 55 of the first switch I1, after which the communication circuit of the output 72 of channel 5 with the input 75 of the memory device 3 is closed. Thus, the data entered from the terminal 7 is recorded in memory device 2 a device 3j

2. Entering a pattern — writing the character codes that make up the image frame: data entered from terminal device 2 and read into memory 3 into memory 8. At the same time, from the fourth output 23 of device 4, a high level signal is sent to the input 44 of the record of memory 8, after which the contents of the storage device 3 are read into the last one at the input 70 and are written to the set

data in the record, whose address is

you

given by the address codeJ read from the third output 22 of device 4 to the address memory input 8;

3, Template output — reads the character codes constituting the writing of the data set of the memory 8 into the memory 3. At the same time, from the output 24 of the device 4, a high level signal is supplied to the input 45 of the reading of memory 8 and to the input 46 of the first switch 11J, after which the communication circuit of the memory output 8 with the input 75 of the storage device 3 and the contents of the record of the data set whose address is set is closed by the address code read from the third turn 22 of the device 4 4 The memory address 8 is copied to the memory 3;

 characters rewriting the DKI code group from the storage device to the storage device 3, 1 of this from the nineteenth of the first stage 38 of the device 4, a high level signal is fed to the input 63 of the second switch 12, after which the communication circuit of the storage device 3 closes the information store. -union input of the random access memory 13, In accordance with the 4th clock produced by the twenty-first output 40 of the device 4, a sequence of clock pulses 5 supplied to the input 65 of the entry of the operative memory unit 3 at the last address, za and the tangible address codeJ read from the twentieth output 39 of device 4, to the address input 64 of the operational storage device 13 is copied from the memory 3, the information recorded in it at the address specified by the address code read to address an input 47 of the memory device 3 from the sixth output 25 of the device 4;

eight

29232 Q

15

20

about

35

25

.

40

50

55

5. Symbols output - copying the DCC code group of characters from the operative storage device 13 into the storage device 3. At the fourteenth output 33 of the device 4, the high level signal is fed to the input 57 of the first switch 11j and the operational backup link is closed. of the informing device with the information input 75 of the memory of the device 3. In accordance with the sequence of clock pulses supplied to the input 48 of the memory device 3, produced in the seventh 26 of the device 4, the one at the address specified by the address code read from the sixth output 25 of the device 4 to the address input 47 of the storage device 3 is rewritten from the operational memory 13 of information recorded therein at the address specified by the address code read to the address input 64 of the device 13 from the twentieth exit 39 devices 4;

6 o Entering numbers - converting DKOI codes of digital data groups into binary-bit codes in accordance with their format of representation in the memory of the random access memory 13 In accordance with the sequence of clock pulses produced at the Sixteenth output 35 of the device 4 and fed to the input 59 the transducer 10 records, into the latter, by its information input 68, is read from the information storage device 3, recorded in it at the address specified by the address code read into the address 47 of the input 47; the device 3c of the sixth output 25 of the device 4

After the DRCI codes of the digital data group to be formed are copied to the converter 10, the output signal 37 from the eighteenth output 37 of the device 4 is fed to the input 61 of the converter 10 and the input 62 of the second switch 12 closes the communication circuit of the output of the converter 10 with input 66 random access memory 13, in accordance with the sequence of clock pulses produced at the seventeenth output 36 of the device 4 and fed to the input 60 of the 1st converter .10, and angshogic after

The timing of the clock pulses operated at the twenty-first output 40 of device 4 n fed to record 65 of random access memory 13 at the last input 66 is read from converter 10 information obtained as a result of converting digital data group data codes into digital binary code of this data, which is recorded in the random access memory 13 at the address specified by the address code, which is read to the address input 64 of the random access memory 13 from the twentieth outputs 39 devices a 4;

7. Output of numbers - conversion of binary-bit codes of numbers into a group of DOCK sneakers in accordance with the format of the representation of numbers in the memory of the random access memory 13 and their image templates for thermals

device 2. At the same time, the corresponding 25 address house, which is read into

With a sequence of clock pulses produced at the eighth output 27 of the device 4 and fed to the input 49 of the transducer 9, into the memory device 13, the last memory information 13 recorded in it is read from the memory device 13 by means of its information-jg memory. at the address specified by the address code, which is read into address input 64 one - ay memory device 13 from the twentieth output 39 of the device 4, After the binary-bit codes are written to the converter 9, dlezhaschie transformation into DKOI codes, with the outlet 30 of the eleventh device 4, a high level signal is supplied navhod transducer 9 and 53 to the input 54 of the first commutator II.

35

40

3 through the channel 5 and the group device 1 to the terminal device 2, and from the second output 21 of the device 4, the high level signal is fed to the input 42 of the encoder 7, which for the latter is an output initiation signal, which is an output command transmitted from output 80 to input 81 of channel 5, a channel output procedure is launched, and the information recorded in memory 3 is transmitted to terminal device 2 in accordance with its physical address recorded in

The communication circuit is closed by the output converters of the service part of the common flow of the output device 9 with the information input 75 of the storage device 3. Further, in accordance with the sequence of clock pulses produced at the ninth output 28 of the device 4 and fed to the input 50 of the converter readout 9, and a similar sequence of clock pulses produced at the seventh output 26 of the device 4 and fed to the recording input 48 of the storage device 3, the latter is read from the converter by its information input 75. 9 information received as a result

myy data

Each of the listed I / O operations is assigned an I / O command. I / O commands are set with uniform codes and recorded in interactive mode using terminal device 2 into random access memory 13. I / O command codes from the random access memory 13 can be read into memory of block 6 by the additional command Sampling commands. Team Kyborka teams is

ten

binary bit numbers

0

g

to the DKOI codes of their image, which is written to the memory device 3 at the address specified by the address code, which is read into the address 47 of the memory device 3 from the sixth output 25 of the device 4;

8. Write the code - write a special code at the current address in the storage device., 3, From the thirteenth output 32 of the device 4, a high level signal is fed to the input 56 of the first switch 11, after which the communication circuit of the fifteenth output 34 of the device 4 o closes. the pulse of the clock, filed with the seventh output 26 of the device 4 to the input 48 of the recording of the storage device 3,

 about

the latter, via its information input 75, is read from the fifteenth output 34 of device 4 a special code which is recorded in memory 3 at the address given by the coaddress input 47 of memory 3 from the sixth output 25 of device 4;

9. Data output - the output of the memory contents of the storage device.

va 3 flows through channel 5 and group device 1 to terminal device 2, and from the second output 21 of device 4, the high level signal is fed to the input 42 of the encoder 7, being for the latter an output initialization signal, on which the output command transmitted from output 80 to the input 81 of channel 5, the channel output procedure is launched and the information recorded in the memory 3 is transmitted to the terminal device 2 in accordance with its physical address recorded in

myy data

Each of the listed I / O operations is assigned an I / O command. I / O commands are set with uniform codes and recorded in interactive mode using terminal device 2 into random access memory 13. I / O command codes from the random access memory 13 can be read into memory of block 6 by the additional command Sampling commands. The command of the command is executed by block 6, all other commands are transmitted for execution from the output 85 of block 6 to device 4 through. its output and initialization are executed at the clock signal, | received at input 91 of the device 4 JC output 87 of the block 6 "Clock signal; completing the input-output command is transmitted from the first output 20 of the device 4 to the input 41 of the block 6o

Claims (3)

Invention Formula the input of the buffer memory The system for interfacing the terminal is 5 Devices, the first output of the exchange control device is connected to the clock input of the command encryption unit, the output group of which is connected to the group of command inputs of the exchange control device, the second output of which is connected to the second input of the third, fourth and fifth encoder the outputs of the exchange control device are connected respectively to 20 one. fishing with a computer, containing a group terminal control device, a multiplex channel, a random access memory, an exchange control device, a command encryption unit, the first switch is different from that, in order to expand the class of solved problems, it contains a sim encoder, a buffer memory device - 25 address, clock inputs of the memory, the second switchboard of the first and second direct access and combined input code converters and memory before reading the direct access memory and direct access a, with a group of informational information inputs of the first mat onn-control inputs and outputs group control unit ter-ZO connected to the inputs of the address and for minarms | 1In the group of system inputs-outputs for connection to terminals, information inputs and output of a group control device for the terminals of the terminals are connected respectively with the first information,:., ion output and multiplex-channel input, the second information output of which is connected to the first information inputs of the command encryption unit and the first switch, the second and third information inputs of which are connected respectively to the direct access memory outputs and the first code converter, the information input of which It is connected to the output of the random access memory, the fourth information input of the first switch, the second information input of the command encryption unit and the system output for connection to the information bus of the computer, the first and second outputs of the mode encoder are connected respectively to the mode inputs of the command encryption unit and a multiplex channel, the control output of which is connected to the first input of the mode encoder, the output of the buffer storage device is connected to the second information input of the multiplex channel, the information inputs of the direct access memory and the second code converter and the first information input of the second KOMMJ controller, the second information input of which is connected to the output of the second code converter, the output of the second switch is connected to the first information input operational memory of its device, the output of the first .tor is connected to the information switch, the sixth and seventh output5 0 g the buffer storage device records, the eighth and ninth outputs — with the write and read inputs of the first code converter, the tenth output — with the control inputs of the first and second code converters, the odnoad output, with the clock inputs of the first code converter and the first switch, which control the inputs of which are connected to the twelfth by the fifteenth exits of the exchange control device, the sixteenth and eleventh outputs of which are connected to the write and read inputs of the second code converter, the eighteenth output — with so input inputs of the second .converter code, and the second switch, from the nineteenth to the twenty-first outputs are connected respectively to the control to msh 1 input of the second switch, the first address and clock inputs of the RAM, the second information, address inputs and write input which are the system inputs for connecting to the computer outputs of the same name 2, the system under item 1, of tl and h a yu sch a. the fact that the device CA | P {1c five It contains a decoder, an encoder, seven synchronization nodes, three registers, four OR elements and two address generators, the information inputs of the decoder and encoder are combined and are the first input of the group of command inputs of the device, the clock inputs of the decoder and encoder are combined and are the second input the house of the group of command inputs of the device, the first output of the decoder is the second output of the device, the second to the eleventh outputs of the decoder are connected respectively: the second output is connected to the first clock input The first address driver also has the first input of the first element OR, the third with the start input of the first synchronization node is the nineteenth output of the device, the fourth with the first inputs of the second and third OR elements and the thirteenth output of the device the input of the second address generator and with the second input of the first element OR, the sixth with the start input of the second synchronization node and is the fourteenth output of the device, the seventh with the second input of the third element I.GSh and is the fourth you the device’s stroke, the eighth with the third input of the third element OR is the fifth output of the device, the ninth with the start input of the third synchronization node, the tenth with the start input of the fourth synchronization node, the eleventh with the start input of the fifth synchronization node and is the twelfth output of the device, the first to the sixth outputs of the encoder are connected respectively: the first to the first information input of the first address generator, the second to the information input of the second address generator, the third speaker to the inputs The first and second synchronization nodes, the fourth with the information inputs of the first and second registers and is the tenth output of the device, the fifth is the third output of the device and the sixth is the fifteenth output of the device, the second information input of the first driver of the address is the third input the group of command inputs of the device, the control input of the first address generator is the fourth input of the group of command inputs of the device, , . - 25, 5 0 with the third input of the first terminal and the initial setup of the second address generator, the second clock input of which is connected to the output of the second OR element, the second input of which is connected to the first output of the first synchronization node, and the first input of the fourth OR element the first output of the device, the second output of the first synchronization node is connected to the fourth input of the first OR element, the fifth input of which is connected to the first output of the second synchronization node, the second output of which is The fourth output of the device and connected to the second input of the fourth OR element and the third input of the second RSHI element, the third input of the fourth OR element is connected to the first output of the third synchronization node and is the ninth output of the device, the second output of the third synchronization node is the eleventh output of the device and connected to the start input of the sixth synchronization node, the mode input of which is connected to the output of the second register and to the mode input of the fourth synchronization node, the first input of which is seventeen device output and connected to the fourth input of the second OR element, the fifth input of which is connected to the first output of the fifth synchronization node, the second output of which is connected to the sixth input of the first OR element, the seventh input of which is connected to the first output of the seventh synchronization node, whose mode input is connected with the input of the third sync uplift mode and with the output of the first register, the second output of the seventh sync node is the sixteenth output of the device and connected to the fourth input of the fourth element IL11, output which is connected to the second clock input of the first address generator, the output of which is the twentieth output of the device, the eighth input of the first ILR element is connected to the first output of the sixth synchronization node, the second output of which is the device output and connected to the sixth input of the second ILA element, the second fourth output The synchronization node is connected to the start input of the seventh synchronization node and is the eighteenth output of the device, the third element is connected to the ninth input of the first element OR, | output which is the first output of the device, the output of the third register is connected to the input of the fifth synchronization node mode, the output of the second address generator is the sixth output of the device, 3. The pop-up system is different from the fact that the command encryption unit contains a synchronization node, three registers, a comparison circuit, a shift register, two associative memory nodes, a delay element, an addi register,: a and a memory node, the information input of which is the second information input of the block, and the reading input is the clock input of the block and is connected to the write input of the third register and to the input of the delay element whose output is the first output of the group of outputs of the block and which course is connected an address input of the memory unit, the input of which is connected to the recording output circuit Equals comparison, unequally output of which is connected to a clock input of the second node associative memory and to the input address register entries, whose information input is connected to the output of the second associative memory node, whose information input is connected to the shift register output, to the information input of the first sociable memory node and to the first information input of the comparison circuit, clock input which is connected to the first output of the synchronization node, to the clock input of the first node of the associative memory, and is the second output of the group of outputs of the block, the second information input of the comparison circuit is connected to the output of the second register, the stroke of the first register is connected to the input of the synchronization node mode, the startup input of which is the mode input of the block and connected to the input of the zero setting of the shift register, whose information input is the first information input of the block, and the clock input is connected to the output of the synchronization node, the output of the memory node connected to the information input of the third register, the output of which is the third output of the group of outputs of the block, the output of the first node of the associative memory is the fourth output of the group of outputs of the block fieL F (4o.1