SU1509869A1 - Multifunction module - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in multichannel redundant systems for highlighting the reliability of a result by means of code voting, for quantifying the quality of functioning of such systems, in multichannel ranking systems in particular for sampling codes and in statistical information processing systems. The purpose of the invention is to expand the functionality. The device contains a memory unit 1, a control unit 2, a sorting unit 3, counters 4, 5, 19, a pulse generator 6, pulse shapers 7, 11, 12, registers 13, 14, 18, comparison circuits 15, 17, a group of elements OR 16, OR elements 20, 21, AND 22 group of elements. The device compares an arbitrary number of codes and determines the most (least) reliable result by the most (least) frequently found code with indication of the level of confidence of the result. 1 il.

Description

From to

00

about

The invention relates to automation and computing technology and can be used in multichannel redundant systems for highlighting the reliability of a result by means of code voting, for quantifying the quality of functioning of such systems, in multichannel ranking systems in particular for sampling codes and in statistical information processing systems.

The purpose of the invention is to expand the functionality.

The drawing shows a block diagram of a device for comparing codes.

The device contains a memory block 1, a control block 2, a sorting block 3, counters and 5 pulse generator 6, pulse shaper 7, trigger 8, AND 9 and 10 elements, pulse shaders 11 and 12, registers 13 and 1, comparison circuit 15 , a group of elements OR 16, a comparison circuit 17, a register 18, a counter of the number of coincidences 19, elements OR 20 and 21, a group of AND 22 elements, information input 23 of the device, input 2k of the comparison end, output 25 of confidence, information output 2 6 of the device.

The device works as follows

In the initial state, the counters, 5 and 19, registers 13, And and 18 are reset, trigger 8 is set to one (the initial installation circuit is not shown). Generator 6 pulses stopped. At the resolution inputs of the counter k and register 18 there is a logical potential coming from the output of trigger 8. Since registers 13 and 1 of sorting unit 3 contain codes equal to zero, the potential of logical 1 from the first output of the comparison circuit 15 enters the first input of the And 9 element and at the input of the driver 11 pulses. As a result, the register 13 remains reset to the first state, and the AND 9 element is open at the first sxo

do

In memory block 1, M contains the number of k-bit codes from which it is necessary to select the most frequently encountered, i.e., the most reliable and determine how many times it occurs among all the codes. Device

o

five

0

five

allows you to select the most reliable code by means of code voting with any threshold and method of sorting by repetition frequency values. The device operates in cycles. To select the most reliable code by means of code voting, the device requires i work cycles, where i 1, M, i.e. determined by the cell number of the memory unit 1 storing the most reliable code. To select the most reliable code by the sorting method according to the repetition frequency, the device requires M operation cycles, since in the i-M operation cycle, the repetition frequency of the code stored in the i-th cell of memory 1 is determined. At the same time, in the last cycle of operation of the i-ro cycle, the most often repeated code of the series of codes stored in the cells of the 1.pam block is determined. In order to perform a device operation cycle, it is necessary (M - i) cycles. In the first cycle of the M th operation cycle, the information output 26 of the device is given the value of the most frequently encountered code and the repetition value of this code.

Operation of the device for comparing codes in the selection mode of the most reliable code by means of code 5 voting with any threshold.

To start up the device, a starting pulse is applied to compare the codes to the start input (not shown) of the pulse generator 6. First, the pulse from the generator output 6 pulses is fed to the read input of memory block 1 and the front edge reads the code from the first cell. From the outputs of memory block 1, the code from the first cell enters the first group of inputs of the comparison circuit 17 and, by the installation inputs, is written into the register 18, at the recording resolution input of which the potential of the logical 1 output of the trigger 8 is found. At the same time, the first and second groups of the circuit inputs The comparison code receives the code from the same cell of the memory block 1, as a result of which the output of the comparison circuit 17 has the potential of logical 1, which adds one to the contents of the counter 19 of the number of matches. With its falling edge, the first pulse from the generator's output is 6 pulses re0

0

five

0

drives trigger 8 to the zero state and adds one to the contents of counter 4.

Thus, from the output of the trigger 8, the potential of the logical O prohibits the recording of the information inputs into the register 18, into the counter 4, and enables the counting of pulses by the counter IS of the number of coincidences.

At the outputs of the bits of the counter k, the address of the next in order cell of memory 1 is set. The following (M - 1) pulses, coming from the generator output of 6 pulses, with their leading edges read codes from the following orderly cells of memory 1 to the first group of inputs of the comparison circuit 17, while the second input group of the comparison circuit 17 stores The code from the first cell of memory block 1 is written in register 18. The input to the installation of the zero state of trigger 8, the pulses confirm the zero state of the trigger. These pulses, with their falling edges, change the contents of counter 4 so that after the i-th pulse received from the generator output 6 of the pulses at the outputs of the bits of counter k, there is a code corresponding to the address of the (i + 1) -th cell of memory 1. The match number counter 19 counts the number of code matches from the first cell of memory block 1 with the codes from the remaining cells.

If all M codes stored in memory block 1 are the same, from the output of the comparison circuit 17, M comparison signals will go to the counting input of the counter 19 of the number of matches in one operation cycle of the device. As a result, the counter 19 of the number of coincidences will overflow and the potential of the logical 1 from the overflow output of the counter 19 will go to the input of the stop of the pulse generator 6, to the output 25 of the device reliability, through the OR element 20 to the inputs of the AND 9 and 10 elements and through the OR 2-1 element on the control the input of a group of elements and 22.

Since, in the initial state, the AND 9 element is open on the first input, when the potential of logical 1 from the output of the OR 20 element arrives at its second input, the AND 9 element opens and the potential of the logical 1 enters the input of the recording resolution

509869

13. At the 1st - kth installation input of register 13 at a given time. There is a code stored in all M cells of memory block 1, which comes from the outputs of bits per of the horn 18, and on (k + 1 ) -m - 2k-M setup input of register 13 is the unit code, i.e. the maximum value of the repetition rate code that comes from the outputs of the bits of the counter 19 of the number of matches. From the outputs of register bits 13, the value of the most frequently encountered state code and the value of the frequency of repetition of this code through the group of elements OR 1b and opened through ele- le. ment OR 21 group of elements And 22 arrive at information output 20 26 of the device. At the output 2k of the device, a zero code remains.

From the information output 2b of the device, the value of the most frequently encountered code and the value of the repetition rate of this code are provided to the consumer. The appearance of the potential of logical 1 at the output 25 of the reliability of the device indicates that the repetition rate of this code is greater than or equal to the established code vote threshold. Since in the initial state the counter of the number of matches was reset, then the code vote threshold was equal to M. When writing in the initial state of the code — n — the initial installation in the counter 19 of the number of coincidences, the counter recalculation coefficient, and hence the threshold for code vote 40 will be equal to (M - n). However, in both the known and proposed devices, it is not possible to set a code vote threshold (M - n) less than 0.5 M ,. those. less than half the number of cells in memory block I. This is due to the possible loss of true information about the value of the most frequently occurring code, since the device stops working when the number of code comparisons is reached, which is equal to the established code vote threshold. If the code vote threshold (M - n) is set to less than 0.5 M, a situation is possible when the device stops working after comparing the number of codes that is less than half the size of memory block 1, and among the remaining unmatched codes it can be

thirty

35

45

50

55

a true valid code, the more common code that has a higher code voting threshold. For these reasons, the selection mode of the most reliable code by the sorting method according to the repetition frequency values is more preferable.

If not all of the M codes stored in memory block 1 are the same) in the first cycle of comparing the code from the first cell of memory 1 with the codes from the remaining (M - 1) cells of memory 1, the output of the comparison circuit 17 will go i, comparison signals to the counting input of the counter 19 of the number of matches. As a result, the hit count counter 19 counts the frequency i, from the token of the first code stored in register 18. If the hit count counter 19 did not overflow when counting the comparison signals, on the falling edge of the M-th counting pulse of the first cycle, the count will overflow

The overflow pulse from the output of the counter enters the counting input of the counter 5, to the input of the element OR 20 and to the input of the driver 7 pulses. On the leading edge of the short pulse arriving with the pulse shaper 7, the trigger 8 is set to one. The potential of logical 1 from the direct output of the trigger 8 is fed to the inputs of the write resolution of the counter k, register 18 and to the reset input of the counter 19 of the number of coincidences. The leading edge of the overflow pulse adds one to the contents of counter 5. From the bits of counter 5, the modified code goes to the set inputs of counter k and is written to it by a logical signal .1 received at the write enable input from the forward trigger output 8,

Thus, at the end of the first cycle of comparing the codes at the outputs of the bits of the counter k, the code corresponding to the address of the second cell of the memory block I is displayed.

Since the registers 13 and 1 are reset to zero in the initial state, and the element 9 is open at the first input, the overflow pulse from the counter output goes through the elements OR 20, and 9 to the input of the register recording resolution 13- pulse enables recording of information from the setup inputs to

0

50

five

0

five

0

five

register 13- At the 1st - kth installation input of register 13 in the first cycle of the device operation there is the code of the number stored in the first cell of memory 1, which from the outputs of the bits of register 18, and at (k + 1) - m - 2k-M setup input of the register 13 is the code of the frequency i of the repetition of this code, which comes from the bits of the counter 19 of the number of matches. From the outputs of the discharge - to. In register 13, the value of the frequency of repetition of code i is fed to the first group of inputs of the comparison circuit 15, on the second group of inputs of which there is a minimum code of zeros from the outputs of the bits of the register 14. Since the value of the code of the frequency i is different from zero, the potential of logical 1 from the second, output of the comparison circuit 15 goes through the one-shot 12 in the form of a pulse to the reset input of register 1A and opens element 10 of the first input. Therefore, in the second cycle of the device, the value of the code i repetition frequency from the counter output 19 matches will be recorded in register 1 by a signal at the second input of the element And 10.

The (M 4-1) th pulse, coming from the output of the generator of 6 pulses, begins the second cycle of code comparison. The input to the read of block 1 of memory, the (M + 1) -th pulse, with its leading edge, reads the code from the second cell of block 1 of memory. From the outputs of memory block 1, the code from the second cell enters the first group of inputs c; comparison schemes are written to the register 18, and the potential inputs from the output of the trigger 8 are found at the input resolution of the record. At the same time, the first and second groups the inputs of the comparison circuit 17 receive a code from the same cell of the memory 1, resulting in the output of the comparison circuit 17 a potential of logical 1 appears, which adds one to the contents of the counter 19 of the number of matches. By its falling edge (M – f 1) -th pulse from the output of the generator 6 pulses, the trigger 8 is switched to the zero state and adds one to the contents of the counter k.

Thus, from the output of the trigger 8, the logic of the logical O is forbidden. There is no entry on the setup inputs of the first compared number that comes from the outputs of the register bits 13 If the code of the frequency i of the first compared number is less than or equal to the code of the frequency i of the second compared number, the potential of logical 1 from the first output of the comparison circuit 15 goes through shaper 11 im9 - -150986910

formations in register 1b, in counter k, and enables pulse counting by counter 19 of the number of coincidences. At the outputs of the bits of the counter k, the address of the next order is set, i.e. the third, memory block 1. The next (M - 2) pulses, I coming from the output of the generator 6 pulses, with their leading edges of pulses in the form of a pulse to the input, reset the codes from the next 13 registers and open the (M - 2) -x perk cells of memory 1 entry element 9. And on the first group of inputs of the circuit 17 If the code of the charter is i, the first comparison is compared, while on the second: the group of inputs of the comparison circuit T 15 is stored the code from the second cell

the comparison enters through the pulse shaper 12 as a pulse to the reset input of the AND register and opens the element AND 10 at the first input. Thus, in the register 13 or 14, the values most often remain

number is greater than the frequency code of the second compared number, the potential of logical 1 from the second output of the circuit 1 5

memory unit 1, recorded in register 18. The input to the amplifier in the zero state of the trigger 8, the pulses confirm the state of the trigger ..

These pulses, with their falling edges, change the contents of counter k in such a way that after (M + i) -ro pulse received from the generator output 6 pulses at the discharge of the bits of counter k, the code corresponding to the address of the (i + 1) -th block cell 1 memory. The counter 19 of the number of matches counts

meeting code and frequency

token of this code i

"101 COP

And

the register in which the lower value of the code repetition rate and the given code were stored will be reset by a reset signal from the corresponding output of the comparison circuit 13. From the outputs of the bits

the number of matches of the code from the second whose-30 registers 13 and H value is the most

1d of the first compared number that comes from the outputs of register bits 13 If the code of the frequency i of the first compared number is less than or equal to the code of the frequency i of the second compared number, the potential of logical 1 from the first output of the comparison circuit 15 goes through the driver 11 pulses in the form of a pulse reset - sa register 13 and opens the first input element And 9. If the code of the charter i, the first

pulses in the form of a pulse to the reset input of the register 13 and opens the element I 9 on the first input. If the code of the charter i, the first

number is greater than the frequency code of the second compared number, the potential of logical 1 from the second output of the circuit 1 5

meeting code

token of this code i

"101 COP

And

the register in which the lower value of the code repetition rate and the given code were stored will be reset by a reset signal from the corresponding output of the comparison circuit 13. From the outputs of the bits

ki of block 1 of memory with codes from the remaining cells of block 1 of memory. As a result, the number of coincidences counter 19 counts the frequency i of the code repetition stored in register 18. The (M - 1) -th pulse of the second code comparison cycle, with its falling edge, causes the counter to overflow. An overflow pulse, coming from the output of counter k, prepares 40 control unit 2 for the third code comparison cycle, similarly to the second cycle described earlier and through the OR 20 element and the I 10 element opened at the first input to the I register recording resolution. At the 1st - k-M setup input of the register lA in the second cycle of the device operation there is a code of the number stored in

Frequently encountered numbers and repetition rates of a given code through a group of elements OR 16 match a group of inputs of elements AND

In the i-M cycle, where i 1, Ы, the device for comparing codes works in a similar way. However, in the i-th code block cycle, the device requires 6 clock pulses from the generator output to the number of clock pulses equal to (M - i, since the code comparison stored in 1 - {i - 1) is stored in the memory block. i - 1) - the number of previous work cycles

Thus, in the i-th cycle, the slave of the device is compared to from the i-th cell of block 1. Memory stored in register 18 with codes from

the second cell of memory block 1, which is -. (M - i) -x cells of memory block 1

comes from the outputs of the register bits 18, and on the (k + 1) -m - 2k-M installation input of the register I is the code i of the repetition frequency of the given number. From the outputs of the bits of the register k, the value of the repetition rate of the code ij is fed to the second group of inputs of the comparison circuit 15, the first group of inputs of which contains the code of the frequency

55

Scheme 17 Comparison. The counter 19 of the number of matches counts the repetition rate of the i-ro code. The sorting unit 3 determines, by the value of the repetition frequency of the codes, the most common code value for the i cycle of the device operation for comparing the code

If, when calculating signals, it is comparable in the i-M cycle of operation of the counter device

Frequently the numbers and the frequency of repetition of a given code through a group of elements OR 16 arrive at a group of inputs of elements AND 22.

In the i-M cycle, where i 1, Ы, the device for comparing codes works in a similar way. However, in the i-th comparison cycle, the device requires 6 clock pulses from the generator output to be equal to (M - i), since the codes stored in 1 - {i - 1) of memory 1 have already been compared in ( i - 1) - the number of previous work cycles.

Thus, in the i-th cycle of the device operation, the code from the i-th cell of block 1 is compared to the memory stored in register 18 with the codes from

(M - i) -x cells of memory block 1

(M - i) -x cells of memory block 1

Scheme 17 Comparison. The counter 19 of the number of matches counts the repetition rate of the i-ro code. The sorting unit 3 determines, by the value of the repetition frequency of the codes, the most common value of the code for the i device operation cycles for comparing the codes.

If when calculating the comparison signals in the i-M device operation cycle, the counter

19 coincidences overflowed, i.e. The repetition frequency of the i-ro code exceeded the established threshold for code voting, the device stops working as in the case described earlier. At the output of the device comparison end, a zero code remains. The potential of logical 1 at the output 25 of the reliability of the device testifies that the repetition rate of the i-ro code has exceeded the established threshold for code voting. From the information output

ten

the counter 19 of the number of coincidences and the occurrence of the signal of logical 1 at the output 25 of the reliability of the device will occur only if all the codes recorded in memory block 1 are the same. In other cases, the operation of the device for comparing codes ends with the arrival from the output of the sorting unit 3 of the values of the most frequently encountered code and the repetition rate of the given code through the group of elements And 22 to the information output 26 of the device

26, the device has the most value, the frequency of the comparison termination signal, of the encountered code and the repetition rates of the given code are issued to the consumer.

Counter 5 counts the number of cycles of operation of the device.

If during M cycles of operation of the device for comparing codes, the counter 19 of the number of coincidences do not overflow with, i.e. there is no code whose repetition rate exceeds the set threshold for code voting, the falling edge of the first pulse of the M-th cycle comparing the codes from the generator output 6. pulses to the counting input of counter k causes overflow of counters A and 5C of the output of overflow of counter 5 potential logical 1 arrives at the output 2 of the device comparison end and through the OR element 21 to the input group of the AND 22 elements. From the output of the sorting unit 3, the values of the most frequently found code and the repetition frequency of the given code through the element group Tov and 2 arrive at the data output device 2b. The occurrence of the potential of logical 1 at the output 2 of the device indicates the end of the code comparison process, and from the information output 26 of the device, the values of the most frequently encountered code and repetition rates of this code are given to the consumer.

The operation of the device for comparing codes in the selection mode of the most reliable code by the sorting method according to the repetition frequency values is similar to the described operation of the device in the selection mode of the most reliable code using the code voting method with any threshold. The difference is that the voting threshold is equal to М, i.e. . maximum. Overflow

the counter 19 of the number of coincidences and the appearance of the signal of logical 1 at the output 25 of the reliability of the device will occur only if all the codes recorded in memory block 1 are the same. In other cases, the operation of the device for comparing codes ends with the arrival from the output of the sorting unit 3 of the values of the most frequently encountered code and repetition rate of the given code through the group of elements And 22 to the information output 26 of the device

0

five

0

five

0

five

0

five

course 25 device.

To determine the least reliable result by the least frequent code indicating the level of unreliability of this code, it is necessary from counter 19 of the number of matches to (k +: 1) -e - 2k-e installation inputs of registers 13 and 14 of sorting unit 3 to submit the reverse code of repetition frequency compared numbers

For this purpose, the inverted outputs of the counter 19 of the number of matches can be used. The operation of the device for comparing codes in this case is similar to that previously described. In this case, the information output device 26 receives the values of the least frequently encountered code and the frequency of repetition of this code according to the comparison termination signal appearing at the device output 25.

Claims (1)

Formula of gain nor A device for comparing codes containing a comparison circuit, a register, a memory block, three counters, a pulse generator, a trigger, an element I, and the information input of the device is connected to the information input of the memory unit, the address inputs of which are connected to the output bits of the first the counter, and the outputs with the inputs of the first group of the comparison circuit and with the information inputs of the register, the outputs of the bits of which are connected to the second group of inputs of the comparison circuit, and the input of the recording resolution connected with. the reset input of the second counter, the counting input of which is connected to the equality output of the comparison circuit, and the overflow output is the output of the device reliability, the output of the generator A pulse torch is connected to the control input of the readout of the memory unit and the counting input of the second counter, the overflow output of which is connected to the counting input of the third counter, and the information inputs are connected to the discharge outputs of the third counter, the overflow output of which is the output of the device comparison end, different By the fact that, in order to expand the functionality by defining the most frequently encountered code, a second comparison scheme, the second and third registers, the second element I, and a group of elements: OR, a group of elements AND, three pulse drivers, two OR elements, the overflow output of the second counter is connected through the first pulse generator to the installation input in the trigger state, the installation input in O of which is connected to the output of the pulse generator, and the output t with the resolution input of the second counter and the first register whose outputs of the bits are connected to the first groups of information inputs of the second and third registers, the second groups of information inputs of which are connected to you by the bits of the first counter, the output of the overflow which is connected to the stop input of the pulse generator and the first inputs of the first and second OR elements, the second inputs of which are connected respectively to the overflow outputs of the second and third counters, the output of the first OR element is connected to the first inputs of the first and second electrodes: And the outputs of which are connected respectively with the enable inputs of the recording of the second and third registers, the outputs of the bits of which are connected respectively with the first and second groups of inputs of the comparison circuit and respectively with the first and second inputs and the elements of the OR group, the outputs of the elements of the OR group are connected to the information inputs of the AND elements of the group, the control inputs of which are connected to the output of the second OR element, and the outputs are the information outputs of the device, the output Less than - the second comparison circuit is connected to the second input of the first element AND and through the second pulse shaper - with the installation input into the second register O, and the output More is connected to the second input of the second element I and through the third pulse shaper - with the installation input into the third register O.