SU1758864A2 - Pulse selector by step period - Google Patents

Abstract

The essence of the invention: the device comprises: a delay line (1), a block (2) for extracting the first pulse, 3 elements AND

Description

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The invention relates to the field of impulse technology, in particular to selectors for the following period, and can be used in automation and computer technology to select signals from the background noise.

A pulse selector is known, which contains a device for selecting the first pulse, an IL-I element, a delay device, a gate driver, an AND element, a scaler, and two flip-flops.

However, this device does not have sufficient noise immunity and speed in the presence of periodic noise at the input.

The closest in technical essence to the present invention is a pulse selector comprising a counting device and a serially connected device for selecting the first pulse, the OR element, the delay element, the gate forming device and the AND element, the second input of which is connected to the input of the selector and the first input of the device for selecting the first pulse , output to the first input of the counting device, the output of the selector and the second inputs of the device for forming gates and the OR element, the third input connected to the output ohm of the delay element, the second input of which is connected to the second input of the first pulse extraction device, as well as to the output of the conversion device, the second input connected to the output, and the second output to the third input of the gate forming device 2.

The disadvantage of this selector is the large time it takes to select a selectable sequence when there is periodic noise at the input.

This is due to the fact that the setting of the prototype selector is made only on the very first pulse of the input sequence.

The aim of the invention is to increase the speed by reducing the time taken to select a selectable sequence under the influence of periodic noise.

To this end, the pulse selector along.with. No. 871324 additionally introduced the first trigger, the second and third elements AND and the delay line, the first input of which is connected to the input bus and to the first input of the second element AND, the output to the second input of the second element And, and the second input to the first output of the scaling unit, moreover, the output of the second element And is connected to the first input of the third element And, the second input of which is connected to the output of the first

trigger, and the output with the fourth input of the first OR element and with the first input of the first trigger, the second input of which is connected to the first output of the counting

block.

Figure 1 shows a structural electrical selector circuit; Fig. 2 are diagrams explaining the operation of the selector; FIG. 3 is a structural electrical delay line circuit,

The pulse selector for the next period contains the delay line 1, the block selection of the first pulse 2, the elements And 3,5,10, trigger 4, four-input element

5 OR 6. delay element 7, gate forming unit 8, counting unit 9. The input pulses are fed to input 11, the output pulses are removed from output 12.

0 Selection block of the first pulse 2. element OR 6, delay element 7, gate forming unit 8 and AND element 10 are connected in series.

The output of the AND 10 element is connected to the first input of the conversion unit 9, the output of the selector 12, and the second inputs of the gate forming unit 8 and the element OR 6.

The second input element And 10 is connected to the input of the selector 11 and the first inputs 0 of the selection unit of the first pulse 2, element 3 and delay line 1. Delay line 1, element 3 and element 5 are connected in series.

The output of the trigger 4 is connected to the second 5 input element And 5, and the first input of the trigger 4 with the output element And 5 and the third input element OR 6.

The fourth input of the OR element 6 is connected to the output of the delay element 7, the second 0 input of which is connected to the second inputs of the delay line 1, the block of the first pulse 2, the trigger 4 and the output of the counting block 9.

The second input of the conversion unit 9 is connected to the output of the second, and the second output with the third input of the unit for the formation of the gates 8.

For example, a similar block of device 1 can be used as a block for selecting the first pulse; moreover, a resolution signal must always be sent to its third input.

The delay element should not be blocked from restarting and each time it is started it should count the delay of 5 minutes.

As a delay element 7, for example, counters can be used.

The gate forming device may, for example, be similar to the corresponding prototype device.

An example of the execution of the delay line is shown in Fig. 3.

The remaining elements of the device are potential type logical elements.

The delay line (FIG. 3) consists of a clock pulse generator 17, flip-flops 18 and 20, pulse counter 19, storage blocks 21 and 22, and an OR element 23, with the output of the reference pulse generator 17 connected to the counting input of the pulse counter 19 and the input reset trigger 18, the setup input of which is connected to the first input of the delay line 1, and the output to the information inputs of the storage units 21 and 22, the outputs of which through the OR 23 element are connected to the output of the delay line 1, the address inputs with the outputs of pulses counter 19, the output overflow neither is connected to the counting input of the trigger 20, the first input of which is connected to the control input of the write mode - reading the storage unit 21, and the second with the same input of the storage unit 22, the reset inputs of the first and second storage units, as well as the pulse counter are connected to the second input of the delay line one.

Consider the work of the proposed selector.

Let a pulse sequence consisting of a selectable sequence (FIG. 2b) and periodic disturbance pulses (FIGS. 2a, c) be applied to its input 11.

Suppose that the very first impulse of the supplied sequence belongs to a selectable sequence of pulses

This impulse is extracted by block 2 and, having passed through the OR 6 element, triggers a delay element 7, which delays this impulse by T -t / 2, where T is the period of the selected pulses, t is the strobe width.

The pulse delayed by element 7, by starting the gate forming unit 8, determines the beginning of the gate generated by block 8 for the next pulse of the input sequence. In addition, this pulse passes through the element OR 6 and restarts the delay element 7, thereby determining the new position of the next gate relative to the input pulse.

The arrival on the element OR 6 of the output pulse coincides with the arrival on this element of a pulse from the output of element 5, which is formed as a result of the coincidence of the pulse of the input sequence on the element 3 and the input pulse delayed in delay line 1 for a time equal to the selected period T And 3. the pulse passes to the output of the element And 5 and by its falling edge, resets the flip-flop 4, prohibiting the passage of subsequent pulses from the output of the element And 3 to the output of the element And 5.

Due to the simultaneous arrival at the element OR 6 of the pulse from the output of AND 5 and the output pulse, as well as the fact that the trigger is reset and the passage of the pulses from the output of the element 3 through the element I 5 is subsequently impossible — the pulse from the output of the element 5 to the operation of the selector does not render.

When a pulse is passed, the output pulse does not form and the gate is fully formed. The trailing edge of the strobe changes the state of the conversion unit 9, which in turn changes the mode of operation of the strobe forming unit 8 so that with each successive pulse the width of the strobe formed by the gate increases by t. Since the restarting of the delay element 7 is not performed by the output pulse due to the absence of the latter, the leading edge of these gates is shifted by t / 2 from the previous gate with each step of the missing pulse. The maximum allowable number of missed pulses can be any equal to m. This number determines the coefficient of the conversion unit 9.

Any output pulse generated at the output of the selector 12 before the number of missed pulses was t, resetting the counting unit 9, sets it to the initial state.

If a m + 1 skip of selectable pulses occurs in addition, the counting unit 9 will overflow. The overflow pulse of this block will reset the first pulse selection unit 2, delay line 1, delay element 7, and also switch trigger 4 to the state allowing the pulse from output of element 3 to the output of element 5. The selector will come to its initial state.

Thus, if the very first input pulse belongs to the selective sequence, then the additionally generated pulse at the output of the AND 5 element does not affect the operation of the selector. Now suppose that the very first pulse belongs to the interference pulse (see Fig. 2).

The process of forming the first gate will be similar to that described above. Further two cases are possible.

1. In the case of an input sequence pulse in this strobe (FIG. 2e), the restarting pulse additionally generated at the output of element 5 and the restarting pulse (the first pulse in figure 2 d) will not affect the operation of the selector, since it coincides in time with the pulse restart, formed at the output of the element 10. The work in this case does not differ from that described above (see Fig. 2e).

2. In the event that the input pulse does not reach the pulse gate at the output of the And 10 element, no restarting of the delay element 7 occurs from the output of the And 5 element (figure 2).

Since the pulse from the output of the element AND 4 is formed in the additional channel as a result of the coincidence on the element AND 3 pulses lagging behind each other for a time equal to T (see Fig. 2c), where T is the period of the selected sequence, then the probability that this impulse belongs to the selected sequence will be higher.

Thus, restarting of the delay element 7 will be effected by a pulse that has passed the preliminary selection in the additionally organized channel due to coincidence of only those pulses on the AND 3 element that are spaced apart by a time T. This allows an increase in the signal-to-noise ratio selector and, consequently, reduce the time of selection of the selectable sequence in the presence of periodic noise at the input. After restarting the delay element 7 by a pulse from the output of the element 5, the further operation of the selector does not differ from that described above (Fig. 2e).

Note that the most effective performance of the proposed selector is achieved when working with periodic noise, having a period close to selectable, and with an increase in the amount of noise acting on the selector input

Evaluation of the performance of the selector was carried out using mathematical modeling.

Line delay works as follows.

In the initial state, the counter 17 and the storage units 21 and 22 are reset.

The first input pulse, coming from the input of the selector to the first input of the delay line 1, with its leading edge sets the output of the trigger 18, and hence the information inputs of the storage blocks 21 and 22, state 1.

This state is currently recorded in the memory of that storage unit.

which is currently in recording mode, at the address set on the bit outputs of the counter 19.

The leading edge of the pulse output

the reference pulse generator 17 changes the state of the counter, and hence the change of the address of the storage blocks. The falling edge of this pulse resets the trigger 18. The trigger 18 is ready for

0 receive the next input pulse.

The volume of the counter 19 and the frequency of the generator 17 are selected in such a way that the cell address of the storage unit in which the time of arrival of the input pulse is recorded

5 in accordance with the discharge outputs of counter 19 only after a time equal to the selected period. The storage unit at this moment is already in Read mode. This cell is being read.

0 The read pulse through the element OR 23 arrives at the output of the delay line 1, which means to the second input of the element AND 5 of the selector, the further passage of the signal in the selector described above. In this way

5 due to the fact that since the moment of entry of the input pulse to the storage cell, until the appearance of this pulse at the output of the storage unit, a time equal to the selected cycle elapses, the input pulse is delayed by this time.

The operation modes of the storage blocks are changed by the overflow pulse of the counter 19. This pulse changes the state at the outputs of flip-flop 20, and therefore at the control inputs of the Record mode - reading of the storing blocks 21 and 22, and since these inputs are connected to different outputs of flip-flop 20, then at that moment when

0 one storage unit is in write mode, the other is in read mode at this point. This ensures the continuity of the recording and reading of the input pulses.

5 The delay line is reset when the counter 19 and the storage blocks 21 and 22 are reset by a pulse arriving at the second input of the delay line from the counting selector unit.

0 Formula of invention

Claims (2)

1. Pulse selector for the period following on auth.St. No. 871324, characterized in that, in order to increase speed by shortening the selection of a selectable pulse sequence under conditions of periodic interference, a first trigger, second and third elements And and a delay line, the first input of which is connected to the input bus, are entered into it and with the first input of the second element I, the output with the second input of the second element I, and the second input with the first output of the counting unit, with the output of the second element I connected to the first input of the third element I, whose second input with It is connected with the output of the first trigger, and the output with the fourth input of the first OR element and with the first input of the first trigger, the second input of which is connected to the first output of the counting unit. 2. The selector according to claim 1, characterized in that the delay line comprises a clock pulse generator, second and third triggers, a pulse counter, first and second memory blocks and a second OR element, the output of which is connected to the output a - i ... B y ilII -LJ.-JI i .u. .  and .L ... LJILJLJj-j-j .., T1 .. ,, I / I j iiiii.i L n. Ljl FIG. jo The second bifi 6 "S -i is the delay lines, and the first and second inputs are with the outputs of the first and second storage units, respectively, whose address inputs are bitwise connected to the outputs of the pulse counter, the control-write-read control inputs, respectively, with the first and second outputs of the third trigger, and the information inputs with the output of the second trigger, the installation input of which is connected to the first input of the delay line, the second input of which is connected to the reset inputs of the first and second storage blocks and a pulse counter, the counting input of which is connected to the output of the clock pulse generator and the reset input of the second trigger, and the overflow output with the counting input of the third trigger. Jiii . - t