SU1411712A1 - Device for testing analog functional elements of automatic systems - Google Patents

Abstract

This invention relates to monitoring means and can be used to dynamically test analog functional elements. The purpose of the invention is to improve the accuracy of the device and its simplification. The device contains a source of 2 test signals, a wideband delay line 3, a sampling unit 4, an ADC 5, a recorder 6, a synchronizer 7, a modulation pulse shaper 8, the elements OR 9, 10, 25, 26, the elements AND 11, 12, 21, 2 -9, 30, element 31, triggers 13, 14, 22, 23, comparator 15, generator 16 of reference step voltage, delay elements 20, 24, drivers 27, 28 pulses, two discharge counter 32, frequency divider 33, The generator 16 has a D / A converter 7, a reversible counter 18, elements AND 19. The device makes it possible to reduce the random component of the sampling rate ii, signals to reduce measurement error and to eliminate the effect of noise adjustable time delay unit. In addition, the device provides asynchronous mode of block interaction, which allows the use of slow-acting ADCs and a recorder. 1 hp f-ly, 1 ill. from 9

Description

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The invention relates to technical means of control and can be used for dynamic testing of analog functional elements, automatic control systems and data processing in order to determine their dynamic characteristics.

The purpose of the invention is to increase the accuracy and simplify the device.

The drawing shows a diagram. devices.

The circuit contains the object under test I, the source 2 test signals a broadband delay line 3, block

4 samples, analog-to-digital converter (ADC) 5, recorder 6, synchronizer 7, modulation pulse shaper 8, first 9 and second 10 elements OR, first AND and second 12 And elements, first 13 and second 14 triggers, comparator 15, reference voltage generator 16 (gene) with a cyro-analog converter (DAL) 17, reversible counter 18 and elements AND 19, first element 20 delay, third element And 21, third 22 and fourth 23 triggers, second element. 24 delays, third 25 and fourth 26, OR elements, first 27 and second 28 single pulse generator, fourth 29 and fifth 30 AND elements, NOT 31 element, two-bit counter 32, frequency divider 33, reset input 34, input 35 launch.

In the initial state of the device to which it switches by a reset signal received at input 34, the zero output signals of the flip-flops 13 and 14 block AND 11 and 12, the output single signal of the trigger 22 unblocks AND 21, the contents of counter 18 become for example, one, which leads to the appearance of the output of the DAC 17, respectively, of a single voltage level; the divider 33 is set to the position at which the desired deduction factor is reached, the trigger 23 switches to the position at which its corresponding output signal, for example, one, sets the forward direction of the counting counter 18 and unlocks the AND 29 element , and the second output signal of the trigger 23 (zero-blocking element I-30, two bits

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 the counter 32 is set to the zero state.

The device works as follows.

Trigger 14 is triggered by the trigger signal at input 35, and its modified output unlocks element 12 of the first signal of synchronizer 7 (its trigger threshold is set to the level where it corresponds to the beginning of the change or the beginning of the period of the source 2 test signal) transmitted via the unlocked element 12, the trigger 13 is switched, and its output signal releases the element 11. The periodically generated test signal is compared in the comparator 15 with the set output voltage level of the DAC 17, equality or inequality of which the comparator is you, tsa appropriate signals.

For testing objects, standard mbno.harmonich.e are usually used ;;:. Skins (for example, cosine) or pulsed (such as delta functions) periodically repeated signals with one maximum. When comparing such signals with the established output level of the gene 16, the comparator 15 forms a square pulse corresponding to the logical values of the binary signals 0-1-0 (or vice versa). The source 2 of the test signals, the comparator 15 and the GOS 16 form a node of an adjustable time delay. As the output changes. the voltage of the GOS output signals of the comparator 0-1 and 1-0 sequentially offset in time from the beginning of the test signal

defined step 1

In accordance with the signals of the comparator, the signal at the output of the test object is sampled. At the same time, the test signal is used simultaneously to temporarily sweep the signal at the output of the test object with its time scale conversion (stroboscopic conversion) - But since the test signal can be alternating, for example, monoharmonic, then to implement a time sweep signal at the output of the test object

In accordance with the full duration of the test signal, the drivers of 27 and 28 pulses are used in the circuit. The shaper 27 generates pulses at times of equality of the level of the GOS test signal with the increase of the latter, and the shaper 28 - with the fall of the test signal. The transfer of the impulse of one or another former occurs through the corresponding elements of And 29 and 30, switched by trigger 23.

With the start of operation of the device for sampling the output signal of the test object, the pulses of the former 27 are used and the AND 29 element is released. In order for the driver circuits to be identical, the element HE 3 is included at the input of the driver 28.

The first impulse of the former 27, which occurred after switching the trigger 13 and releasing the element 11, passes through the element 1 and through the element 9 and enters the reset inputs of the trigger 13 and 14, these triggers reset and again block the elements 1 1 and 1 2.

The shaper 8 periodically generates short pulses for sampling in block 4 a sample of the test signal transmitted through object 1. Discretization is performed at times relative to the beginning of the test signal and at its level determined by the set output voltage of the GOS 16.

The transmission of the test signal to the input of the test object is delayed by the broadband line 3 for the delay in the formation and transfer of the sampling pulse to the sampling unit. This delay is due to inertia, i.e. the total delay of the comparator formers 8.27 (28), elements 26 and 29 (30).

With a delay in the element 20 at the time required to establish the voltage at the output of the sampling unit, the ADC 5 is triggered by a comparator signal (more precisely; a pulse formed from the leading or trailing edge of this signal), but due to blocking the element 11, despite periodic molded comparato

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the comparison signal signal, only one signal from the sequence of these comparison signals is transmitted to the trigger circuit of the ADC. The transfer of the next signal to the output of the element I I1 and the subsequent next start of the ADC are delayed by the time required for the previous cycle of analog-digital conversion and recording, and are synchronized with the beginning of the appearance of the current test signal or the beginning of the period of this signal. This asynchronous mode of interaction allows the use of slow-acting and simple ADCs and a recorder, regardless of the generation frequency of the test signals.

On the signal of the end of the measurement, the ADC starts the recorder 6 and records the current coded discrete value of the test signal measured at the output of the test object.

With each definite number n of the signals of the end of the ADC measurement, simultaneously with the beginning of the nth registration cycle, the signal of the divider 33 adds one to the contents of the counter 18 and the output voltage of the generator-p 16 increases by one step.

The number n is determined by the recalculation factor of the divider 33. Due to this, the n-time accumulation mode of one and instantaneous values of the test signal measured at the output of the test object, i.e. in the sample block. with the possibility of their subsequent additional statistical processing. Thus, the accuracy of determining the characteristics of the test object is further improved.

The signal of the end of registration, transmitted through the released element 21 and the element OR 10, performs the next launch of the device and the described sampling cycle of the next current instantaneous value of the test signal, its coding and registration are repeated as described.

When the currently set generator voltage level exceeds the amplitude of the test signal, the signal at the comparator output stops changing. Therefore, with the transfer of the synchronizer signal through the released element 12 to the input of the flip-flop 13, the latter switches, but due to the absence of the comparator signal, it remains in this position. The output signals of the AND 2 unit counts the two-digit counter 32. Before the voltage of the GOS is 6 the amplitude of the test signal, this counter is reset every time to the zero state simultaneously with the switching of the triggers 13 and 14 of the output signal of the And 11 element. and the counter 32 starts counting the number of the following one after the synchronizer's other signals, then two such signals, counted by the counter 31, are a sign that the comparator 15 has fixed the excess by the current setting It ennym levels of the test signal generator amplitude. At the same time, the output signal of the counter 32 (the sign of the number 2 in this counter) switches the trigger 23. The modified output signals of this trigger block the element 29 and unlock the element 30 and switch the counter 18 through the corresponding element 19 to the counter in the opposite direction, those. in subtraction mode.

In addition, the output signal of the counter 32, with a delay in the element 24 necessary for establishing the signals of the trigger 23, is transmitted through the IS element. 25 to the counting input of the counter 18. In this case, the voltage of the GOS 16 decreases by one step. At the same time, the signal of the element 24 transmitted through the element of RSHI 9, the counter 32 and the triggers 14 and 13 are switched to the initial states, the signals of which block the elements 11 and 12, respectively. Further, the device continues to operate in the manner described above, but now the generator voltage in each cycle is successively reduced, and sampling pulses are formed at the spa. 1

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and also one of the trigger signals 23, which is a sign of the sign of the test signal — its rise or fall. At the same time, the counter 18 counts the number of steps of the reference voltage and the corresponding number of sampled instantaneous values of the test signal at you .10 object's course before and after the amplitude value of this signal. By signal zeroing this counter corresponding to the registration of the n-th count of the last of the instantaneous values

15 of the test signal at the first quantization level, trigger 22 is switched. The zero signal of this trigger blocks AND 21 and prohibits the next launch of the device.

20 current signal end of registration. In this case, the device stops operation before the arrival of a new reset signal and a subsequent start signal.

By the difference of the true instantaneous value of the test signal at the object's input and the corresponding discrete value of this signal

at the output of the object, the time delay of the test object can be determined, and from the combination of the indicated values of the test signal, it is possible by subsequent processing to determine the full dynamic characteristics of the test object, such as frequency response, phase response, and transition.

Claims (2)

1. Device for testing analog functional elements of automatic systems, comprising a source of test signals, a broadband delay line, a sampling unit, an analog-to-digital converter, a recorder, a synchronizer, a modulation pulse driver, a comparator and a reference step voltage generator, the first information test signal to the moment output of which is connected you time, corresponding to switching the comparator from 1 to O. In each cycle, in parallel with the ADC code, the current counter code 1-1ka 18 is recorded, which corresponds to the true instantaneous value of the test signal at the output of source 2 at the time of sampling the test signal at the object output. the first comparator input, the second information output — with the first information input of the recorder, the reset input is the device reset input, the second comparator input, the synchronizer input and the information input of the wideband delay line are connected to the output of the test signal source, the control inputs 7 the wideband delay line and the sampling unit are connected to the output of the modulation pulse generator, the output of the wideband delay line is the output of the device for connecting the test object, the information input of the sampling unit is used to input the object's response device, and the output is connected to the information input of the analog-digital converter, information and control outputs of which are associated respectively with the second information and first control inputs of the registrar, in order to increase accuracy of operation and simplification of the device; the first, second, third and fourth elements OR, the first, second, third, fourth and fifth elements AND, the first second, third and fourth triggers, the first and second delay elements, the first and second pulse shapers , a NOT element, a two-bit counter and a frequency divider, whose information input is connected to the control output of the analog-digital converter, and the control input, the single inputs of the third and fourth triggers, and the first input of the first element OR are in the device reset house, the control input of the analog digital converter is connected to the output of the first delay element, the input of which and the second input of the first element OR are connected to the output of the first element AND, the first input of which is connected to the direct output of the first flip-flop The modulator pulse generator is connected to the output of the fourth element OR the first and second inputs of which are connected respectively to the outputs of the fourth and fifth elements AND, the first inputs of which are connected respectively to the outputs of the first and the second pulse formers, and the second inputs, respectively, with the direct and inverse outputs of the fourth trigger, which are connected respectively with the first and second control inputs of the reference step voltage generator, the control output of which is connected to the zero input of the third trigger, which is connected directly with the first entrance of the third ele VINILI Order 3653/43 m) o, 15, 20, 25 ZO - o 40, -. 45, 50 55 411712 8 And, the output of which is connected to the first input of the second element OR, the second input of which is the device start input, the second input of the third element AND is connected to the control output of the recorder, the second control input of which is connected to the forward output of the fourth trigger, zero input the one and the input of the second delay element are connected with the output of a two-bit counter, the counting input of which and the single input of the first trigger are connected to the output of the second element I, the first input of which is connected to the output of the synchronizer, second The second input is with the direct output of the second trigger, whose single unit is connected with the output of the second OR element, and the zero input, the reset input of the two-bit counter and the zero input of the first trigger, with the output of the first OR element, the third input and the first input of the third element OR connected to the output of the second delay element, the second input of the third element 1-SHI connected. with the output of the frequency divider, and the output with the installation input of the reference voltage generator, the output of the comparator is connected to the center of the first pulse generator and to the input of the element NOT, the output of which is connected to the input of the second pulse shaper, 2. The device according to claim 1, wherein the reference step voltage generator comprises a digital-to-analog converter, a reversible counter, the first and second elements And, the first inputs of which form the first and second control inputs of the generator, respectively, the second inputs are the generator setup input, and the outputs are connected respectively to the summation and subtraction inputs of a reversible counter, the reset input of which is the generator reset input, the zero output, the generator output control, and nny output coupled to the input of the digital to analog converter and serves as a second information generator output, the output of DAC is the first information the generator output. Subscription