SU1401447A1 - Arrangement for displaying information on television indicator screen - Google Patents

Abstract

The invention relates to computing and can be used in devices for outputting alphanumeric information. The purpose of the invention is to increase the reliability of the displayed information. The device contains a clock generator 1, counter 2 familiarity, counter 3 lines of familiarity, counter 4 lines of characters, driver 5 frame sync pulses, shift register 6, character generator 7, memory block 8, address switch 9, driver 10 horizontal sync pulses, buffer register 11 , address register 12, video signal generator 13, control unit 14, synchronization unit 15, interface block 16, television display 17 with corresponding connections. Improving the reliability of displaying information is achieved by separating the cycles of reading the character codes from memory block 8 and accessing the computer through the interface block 16 to memory block 8. 4 il. (L with

Description

but;

The invention relates to computing and can be used to display alphanumeric and graphic information.

The purpose of the invention is to increase the reliability of the displayed information.

FIG. 1 shows a block diagram of the device} in FIG. 2 is a block diagram 10 of a synchronization unit; in fig. 3 is a block diagram of a control unit; in fig. 4 is a block diagram of an interface block.

The device contains a clock generator 1, a counter 2 familiarity, a counter 15 hours 3 lines of familiarity, a counter 4 lines of characters, shaper 5 frame sync pulses, shift register 6, character generator 7, block 8 operational

At the addresses specified by the familiarity counter 2 and the 4 character string counter, the character codes synchronously with the beam moving across the screen of the television indicator 17 are read from block 8 and fed to the input of the character generator 7 together with the address signals from the second output of the familiarity counter 3 lines defining the current line familiarity.

From the output of the character generator 7, information about the line by line decomposition enters the information input of the shift register 6 with a positive level of the parallel recording enable signal in the shift register 6 at the fourth output of the synchronization unit 15. Recording is made by differential

memory, address switch 9, high level shaper to low clock 10 horizontal sync pulses, buffer register 11, address register 12, video signal generator 13, control block 14, sync sync block 15

, block 16, interface, zion indicator 17.

The synchronization unit 15 (Fig. 2) contains an annular register 18, consisting of a set of triggers 18-1, 18-2, 18-3 and 18-4 and consisting of two elements AND 19 NOT 21 and element AND-NOT

 25

thirty

point counter,

element

and 20, 22.

The control unit 14. (FIG. 3) contains an element of the ШШ 23, the trigger 24 for the exchange clock 35, the trigger 25 for synchronization, the OR element 26, and two I-HE elements 27 and 28.

Interface unit 16 (FIG. 4) consists of channel receivers 29, comparison unit 40 30, device selection trigger 31, register selection trigger 32, control decoder 33, control signals, channel transmitters 34, and response signal generator (KSIPN). 45

The device works as follows.

The symbols on the screen of the television indicator 17 are generated by outputting the signal at the output of the clock generator 1. After this, the content of counter 2 increases by a unit from the low level to high signal at the fifth output of the synchronization unit 15, and at a high signal level at the third output The synchronization block 15 starts the clock cycle of the microcomputer memory block 8 and the information on the constant decomposition of the sign written in the shift register 6 is converted into the sequential code of the character string and the input ate to shaper input

13 video signal. If it is necessary to access block 8, the microcomputer pre-writes to the register 12 the address at which it will be accessed. After that, the microcomputer performs a reading (or writing) cycle from block 8. The display of the information display device and the microcomputer is produced through the block 16 of the interface.

At the third output, the interface 16 when recording information into the memory unit 8 from the microcomputer generates a data recording signal, which is fed to the first input of the block

14 control.

A high signal level to a third. A high signal level in the third lighting of the corresponding combination of the code of the synchronization unit 15, the points in the dot matrix that each represents on the screen, the set of character images is stored in the character generator 7. The information to be displayed is in coded block 8, pre-filled from a microcomputer (not shown) through the block 16 of conjugation.

dividing the display and exchange cycles, switches the address switch 9. The address switch 9 disconnects from the address inputs of the block 8 address signals 55 set by the counter 2 familiarity and the counter 4 lines of characters, and connects the address signals from the findings of the register 12 address to them. Upon the arrival of a high level signal from the first address given by the counter 2 familiarity and the counter 4 lines of characters, the codes synchronously with the beam moving across the screen of the television indicator 17 are read from block 8 and fed to the input of the character generator 7 along with the address signals from the second output of counter 3 familiarity strings defining the current familiarity string.

From the output of the character generator 7, information about the line by line decomposition enters the information input of the shift register 6 with a positive level of the parallel recording enable signal in the shift register 6 at the fourth output of the synchronization unit 15. Recording is made by differential

 high level in low tact

signal at the output of the clock generator 1. After that, the unit 2 of the content of the counter 2 increases the familiarity between the low level and the high signal at the fifth output of the synchronization unit 15, and when the signal level is high, the third output of the synchronization unit 15 begins block 8 of the microcomputer memory and information about the constant decomposition of the sign recorded in the shift register 6, is converted into the sequential code of the character string and is fed to the input of the imager

13 video signal. If it is necessary to access block 8, the microcomputer pre-writes to the register 12 the address at which it will be accessed. After that, the microcomputer performs a reading (or writing) cycle from block 8. The display of the information display device and the microcomputer is produced through the block 16 of the interface.

At the third output, the interface 16 when recording information into the memory unit 8 from the microcomputer generates a data recording signal, which is fed to the first input of the block

14 control.

The high signal level in the third code of the synchronization unit 15 separating the display and exchange cycles switches the address switch 9. The address switch 9 disconnects from the address inputs of block 8 the address signals set by the counter 2 familiarity and the counter 4 lines of characters, and connects the address signals from the findings of the register 12 address to them. Upon the arrival of a high level signal from the first output of the synchronization unit 15, strobing the exchange with unit 8, a data recording signal is generated in unit 8 at the second output of the control unit 14. Upon the arrival of a low level signal of the end of the exchange clock, the second output of the synchronization unit 15 ends the data recording cycle in block 8. At the output of the trigger 31, a high level signal appears indicating the micro-computer about the end of recording information in block 8. This signal through block 16 the interface enters through the input-output device of the microcomputer channel, which completes the exchange, removes the data recording signal at the third output of the interface 16, This completes the formation of the synchronization signal exchange with the microcomputer at the third output Single 14 controlling the read information in a cycle of unit 8 interface unit 16 to the fourth output signal generates data Reading

Claims (1)

Claims. A device for displaying information on a television indicator screen comprising a clock generator, familiarity counter, familiarity row counter, character row counter, framing clock generator, synchronization unit, shift register,. character generator, main memory unit, address switch, horizontal sync pulse generator, control unit, interface block, buffer register, video signal generator and address register, the output of which is connected to the first information input of the address switch, the second information input of which is connected with the first exit counter familiarity, the second output of which is connected to the input of the downlink sync pulse generator, the output of which is connected to the first control input of the formation which is fed to the second input of the video signal blocker, the second control ka 14 management. Then the control unit 14 works in the same way as the algorithm described for the write cycle, but unlike the write cycle, it does not generate a write signal in block 8 at the second output of control unit 14, but a write signal to the buffer register 11 at the first output block 14 control, which provides the storage of information read from block 8 before transferring it to the microcomputer. After the information is recorded in the register 11, the synchronization signal is generated at the third output of the control unit 14, from which in the control unit 16 the signal of the micro-computer messages is generated about the presence of information at the device input-output. Thus, the information read into the microcomputer during the exchange cycle does not fall on the screen of the television indicator 17, since the recording signal to the shift register 6 is only developed in the image forming cycle, and the information recorded in the register 6 continues to advance in the exchange cycle. the shift in the imaging cycle preceding the exchange cycle with the microcomputer. Thereby, it is provided to increase the reliability of information display by eliminating image distortions during its modification. five about .- five 0 five The input of which is connected to the output of the HR sync pulse generator, whose input is connected to the first output of the character row counter, the clock input of which is connected to the first output of the familiarity line counter, the clock input of which is connected to the third output of the familiarity counter, the second output of the character string counter, is connected to the third information input of the address switch, the output of which is connected to the first address input of the RAM block, the second address input of which and the information input of the address register Connected to the first output of the interface unit, the second output of which is connected to the control input of the address register, the control input of the buffer register connected to the first output of the control unit, the second output of which is connected to the control input of the RAM, the output of which is connected to the information input the buffer register and to the first address input of the character generator, the second address input of which is connected to the second output of the line counter familiarity, the output of the character generator is connected to the information input of the shift register, the output of which is connected to the information input of the video signal generator, the output of which is connected to the video input of the television indicator, the output of the clock generator is connected to the clock input of the shift register, the third output of the control unit is connected to the first the control input of the interface, the information input of which is connected to the output of the buffer register, the third and fourth outputs of the interface connection us respectively with first and second inputs of the gate control unit, third, fourth and fifth control inputs which are connected respectively to the first, second and tre- .temu outputs sync block, I The input-output of the interface is the input-output of the device, characterized in that, in order to increase the reliability of the displayed information, the output of the clock generator is connected to the input of the synchronization unit, the fourth output of which is connected to the control input of the shift register, the fifth output the synchronization unit is connected to the clock input of the familiarity counter, and the control input of the address switch is connected to the third output of the synchronization unit. P Editor A. Vorovich Compiled by O. Tsapko Tehred L. Serdyukova Order 2785/47 Circulation 704 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, d. A / 5 FIG. Corrector B, But ha Subscription