SU1389007A2 - Start-stop receiver - Google Patents

Abstract

The invention relates to telegraph communication and increases the reliability of reception. The device contains an analyzer 1 marker, analyzer 2 parcels, switch 3, driver control signals (FUS) 4, clock gr.r 5, counter (C) 6, register 7, decoder 8. Switches 9-11 are introduced, clock Mr. 12, C 13, block 14 setting frequencies, block 15 of the display, e-t. OR 16, Element I 17. A message cogram consists of a marker and an informant. impulses, between which the marker time interval t is set (. After it follows the informational impulse Start 1, then the information interval t. Then the delay interval t const follows, after which the information impulses Start 2 and Stop 2 are provided with t, performing the function of the control interval. For any message, the condition of fidelity of its reception is monitored by the constant of the sum of the intervals n const. The deviation of block 15 indicates unauthorized interference with the content of the received codogram even under the condition ty + t const. its given frequency of clock pulse generation on r-12 by means of block 14, such that at the time of the formation of the correctly received codogram of FUS 4 overflows with 13, the device resistance increases. 2 or. (O

Description

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The invention relates to a telegraph communication technique and can be used in telemechanical systems and digital automation systems for recording unauthorized interference with the content of transmitted messages and is an improvement of the invention according to the author. St. No. 1142,899.

The purpose of the invention is to increase the reliability of reception.

FIG. Figure 1 shows the structural electrical circuit of the start-stop receiver; 2 shows an embodiment of a switch and a driver of control signals.

Receiving start-stop device contains (Fig. 1) analyzer. markers, parcel analyzer 2, switch 3, control signal generator 4, clock generator 5, counter 6, register 7, decoder 8, first 9, second 10 and third 11 switches, additional clock generator 12, additional counter 13, task block 14 frequency, the display unit 15, the element HJlIi 16, the element And 17.

The switch 3 contains (Fig. 2) of block 5 through this element And 34 at the input

the type element and 18-21.

Shaper 4 control signals (FIG. 2) comprises an amplifier 22, three delay lines 23-25, seven flip-flops 26-32, and two elements And 33 and 34,

Receiving start-stop device operates as follows.

The message codogram from the communication line is fed to the input of the receiving start-stop device. The codogram includes marker and information pulses. Between the marker and information pulses, a marker time interval t is set, followed by the first information pulse Start 1, then the information time interval ty, limited by the second information pulse Str 1. Next comes the delay interval t5 const, after which the following information pulses Start 2 and Stop 2 with a time interval between them 11, performing the function of the control time interval. For any message, the condition of fidelity of its reception is controlled by the constancy of the sums of time intervals,

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When a message arrives from the communication line, the pulsed messages (Fig. 1) are encoded by the analyzer 1 marker and the parcel analyzer 2. If the parameters of the marker pulse and the marker time interval tf correspond to the specified ones, then the analyzer 1 of the marker outputs a signal to the input of the imaging unit 4.

By this signal, the trigger 32 of the driver 4 (FIG. 2) goes into one state. The signal from the trigger 32 output goes to one

the input element And 18 switch 3 (Fig. 2). With the arrival of a pulse from the communication line, Start 1, the analyzer 2 parcels, to the second input of the element I 18 of the switch 3, a signal, under

the action of which the element And 18 goes into one state. The output signal of the element And 18 includes triggers 29-31. The trigger 31 goes to a single time and provides

supplying power to the clock generator 5. A single signal from the output of the trigger, 30, is fed to the second input of the AND 34 element and permits the passage of pulses from the output of the clock generator

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counter 6. Counter 6 begins to fill. The unit state of the trigger 29 prepares the And element 19 of the switch 3 for receiving a stop 1 pulse at its second input.

With the arrival of a stop 1 pulse from the communication line, the polarity of which is reversed by the start polarity of the start pulse 1, the information time interval t is organized. The parcel analyzer 2 sends a signal to elements AND 19-21 of switch 3. Elements AND 20 and 21 do not pass this signal, because the second inputs of them do not receive a counter 6 overflow signal. Element 19 also opens because its second input is single the signal from the output of the trigger 29, and the signal Stop 1 through the element And 19 is fed to the inputs Reset triggers 32 and 30 and to the direct input of the element And 33, as well as the signal Stop 1 is fed to the input of the delay line 23.

The trigger 32 goes to the zero state and removes a single signal from the input of the element I 18 of the switch 3, thereby disconnecting the passage circuit of the pulsed parcels from the analyzer 2 parcels to the driver

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4 for the time interval t. This increases the noise immunity of the device, since for the time tj the possibility of distortion of the received codogram is avoided if interference occurs in this time interval t ,. The trigger 30, the transition to the zero state, removes a single signal from one of the inputs of the AND 34 element, thereby disconnecting the output of the clock generator 5 from the counter 6. At the output of the AND 33 element there appears a single signal, since its second input, Inverse, a zero signal from the output of the trigger 27 is supplied. The output signal of the AND element 33 translates the trigger 28 into a single state, which by its output signal gives the resolution to the binary 7 in the counter 6,

In addition, the Stop 1 signal from the delay line 23 outputs after a delay time t gives a signal to the counting inputs of the flip-flops 29, 28 and 27 and one output of the AND 1-8 element of the switch 3. The flip-flops 29 and 28 go to the zero state and remove the permission signals for switching on element 19 and recording information into register 7, respectively. Trigger 27 goes into one state and outputs an inverted input of element 33, thereby prohibiting the passage of signals through this element 33, the signal to the counting input of trigger 28 the outputs of the elements And 19 and 21.

In the absence of temporal distortions of the codogram in the interval, simultaneously with a single signal from the output of the delay line 23, the signal Start 18 is received from the output element 18, which is output by the parcel analyzer 2 from the communication lines. The pulse signal from the output of the element And 18 enters the control trigger 31, 30 and 29. The trigger 31 continues to be in a single state, the trigger 30 goes into a single state, and the trigger 29 continues to be in the zero state, removing a single signal from one of the inputs of the element And 19. This excludes the possibility of the passage of signals from the output of the analyzer 2 senders to the driver 4 before the expiration of the control time interval t. Thus, when impulse noise gets into the test - the time interval of the distortion is 0

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My information does not occur, which increases the noise immunity of the device.

A single signal from the output of the trigger 30 is fed to one input of the And 34 element and allows the passage of pulses from the output of the clock generator 5 to the input of counter 6, which, after a breakdown t, continues counting the pulses. After the counter 6 is completely filled, the overflow pulse from its output goes to the inputs of the AND elements 20 and 21 and to the input of the delay line 25. The other inputs of the And 20 and 21 elements simultaneously receive a single Stop 2 signal, the polarity of which is inverse to the polarity of the Start 2 signal from the analyzer's 2 parcel output. Element And 20 generates a signal to the input of the trigger 26, which goes into one state and allows reading previously recorded information from register 7 to the decoder 8. In addition, the signal from the trigger output 26 is fed to the input of the delay line 24, which, after the delay time expires through the parcel analyzer 2, the receipt signal to the communication line, indicating that there is no distortion in the received codogram. Element And 21 duplicates the transfer to the initial state of the trigger 32.

In addition, the output signal of the And 21 element is fed to the forward input of the And 33 element and to the input of the delay line 23. Element And 33, as well as element And 19, does not work, since the resolution signal from trigger 27 does not come to its second input. In the initial state, trigger 30 prohibits by means of the AND 34 element the further overflow of the counter 6.

After the delay time t from the outputs of the delay line 23, signal signals are received that do not change the state of the device’s electrical circuit, i.e. the inclusion of the trigger 27 in one state. Element And 18 does not work, since the Start signal does not arrive at its other input at this moment in time.

An overflow pulse from the output of the counter b, arriving at the input 25 of the delay, ensures the formation

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signal Reset to amplifier 22. From the output of amplifier 22, the generated signal Reset returns to the initial state the triggers 31, 27 and 26. At the same time, to ensure a stable transition of the receiver to the zero (initial) state, the delay time of the delay line 25 exceeds state of delay line 23 of the delay In the case of a time difference between the stop 2 signal and the overflow signal i arriving at the inputs of the elements 20 and 21, the trigger 26 remains

with its initial state and with its contacts it turns off the display unit 15 and the additional clock generator 12. Disabling the display unit 15 indicates unauthorized interference with the contents of the received code even if the receiving condition t + t const start 10

stop device. By specifying in advance the frequency of the generation of clock pulses on the additional clock generator 12 using block 14 so that by the time of formation the signal is correctly received in the zero state, the qui-codogram signal by the shaper 4 reclaims about the correct reception of the message in the additional counter 13 , the communication link is not given. The imitation resistance is improved at the disadvantage of the basic invention of the many start-stop device.

consists in the fact that in the case of unauthorized intervention in the content of a legitimate intervention in the content of the transmitted message, the condition of reception accuracy is tf, + t | const can easily be simulated, which indicates that the imitodogram is not high enough, then at the moment of overflow of the additional counter 13 it entered the second input of the element 17 and the control input of the third com- plexity of the known receiving start-25 mutator 11 pulse signal from the driver 4, under the action of which the third switch 11 will again work, self-blocking and will activate the additional clock generator 12 and the display unit 15. Dp exclude possible interruptions in the operation of the display unit 15 for the response time T1 of its switch 11 the power of this display unit is carried out through the OR element 16 s

stop device.

In order to improve the imitation resistance of the main invention, the corresponding output of the former 4 is connected to the control input of the third switch 11 and to the same input of the element I 17. When a signal appears on this output of the former 4, simultaneously with the activation of the decoder 8, the third switch 11 turns on

Secondly, through the opening contacts, using the closing contacts of the first switch 10, it self-blocks, the second switch 9, which triggers the additional clock generator 12 to work, and through the OR element 16 turns on the display unit 15. An additional clock generator 12 generates pulses with a frequency specified by the frequency setting unit 14. These clock pulses are fed to the input of an additional counting-output signal of which turns on the chip 13 and is stored in it. Impulse to work the second switch 10 on

the overflow of the additional counter 13 is fed to the equalizing input of the second switch 10 and to one of the inputs of the element AND t7. The second switch 10 is turned on and the third switch 11 unlocks with its break contacts, and the additional counter 13 is turned on by the closing contact.

If by the time of full filling 55 there are three switches, a sequential additional counter 13 is not after the connected element OR and the unit stumbles the signal from the output of the former 4, then the third switch 11 returns indication and the series connected frequency setting unit has also returned to its original state contacts will turn off the display unit 15 and the additional clock generator 12. Disabling the display unit 15 indicates unauthorized interference with the contents of the received code even if the condition is correct ti reception t + t const startdogrammy not, at the time counter overflow additional 13 entered the second input of AND gate 17 and to a control input of the third kom40

at the time of coincidence of the overflow of the additional counter 13 and the formation of the correctly received sequential multiple of the overflow time of the additional counter 13 of the codogram by the former 4. At this moment - the element AND 17 is triggered,

switching time of the third switch 11.

Claims (1)

Invention Formula Starting stop device according to aut. St. No. 1142899, characterized in that, in order to increase the reliability of reception, three switches, a connected OR element and a block, are introduced. indications and serially connected frequency setting unit, dopol / 1 The downstream clock, an additional counter and an element, whose output is connected to the control input of the first switch, the signal input and output of which are connected respectively to the signal input of the second switch, to the control input of which is connected to the output of the counter, and to the first input of the OR element, to the second input of which the output of the third switchboard is connected 890078 Pa, the other output of which is connected to the control input of the additional clock generator, while the fourth output of the control signal generator is connected to the second input of the AND element and the control input of the third switch, the signal input of which is connected to one output Q of the second switch, another output which is connected to the output of the additional counter. i / e.2