SU1348831A1 - Device for computing exponential function - Google Patents

Abstract

The invention relates to computing and can be used for the hardware implementation of the operations of calculating a power function with indicators 2 and 1/2 in universal and specialized computers. The purpose of the invention is to increase the accuracy in calculating the function with the indicator 1/2. The goal is achieved by the fact that the device containing the comparison circuit 1, counter 2, multiplexer 3, accumulating adder 4, elements AND 5.6, block 7 of microprogram control, introduced the second comparison circuit 14, second multiplexer 15, switch 16 and combination combiner 17 with related communications. The device allows calculating power-law functions with exponents 2 and 1/2 with high noise immunity and high speed when developing small increments of the argument due to the organization of a recursive computation process. 5 ill., 8 tab. S (L oo 4 00 00 00

Description

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And-and | G11: the concept refers to the nanometer-hp selection technique and can be used for the hardware implementation of the operations of calculating the power function with the exponent 2 and 1/2 in the universal and specialized calculators,

The purpose of the invention is to improve the accuracy when reproducing the step of the first function with the indicator 1/2.

FIG. 1 shows a functional diagram of the device; in fig. 2 - implementation of the switch; in fig. 3 - a variant of the circuit implementation of the firmware control unit; in fig. 4 is a block diagram of his work; in fig. 5 - firmware programmable logic matrix (PLA) control unit, respectively

In the device diagram (Fig. 1), the following designations are accepted: the first comparison circuit 1, the reversible counter 2, the multiplexer 3 first, the accumulating adder 4, the first 5 and the second 6 elements And, the microprogrammed control unit 7, the input 8 of the logical zero and the input 9 logical units of the device, inputs 10, 11, respectively, start and installation inputs of the device, output 12, readiness of ata, ata, information input 13 of the poitcTBa installation, second comparison circuit 14, second mu; 1tx multiplexer 15, switch 16,. summator 17, input 18 of the mode and output 19 of the devices but.

All (devices can be implemented on the basis of widely used P computational microcircuits; .. circuitry 1.14 comparison - on K 155 SP chips; counter 2 - on micros: Khemah 155 IE7, K: mbina1 ion G1 adder 17 - on K 155 IMZ chips, multiplexers 3.15 - on K 155 KI 1 1 chips. The accumulating adder can be implemented, for example, on IM1 chip 1802 by connecting the output from the mmator to its free input. 15 connect; yyuchayut to the output of their first or second informational inputs with the completion; shchii on yppaFjJinyuschem in de edinichzhp respectively about zero signal, the CPU variant realization tion switch 16, e.g., on chips K 155 CP 11 prigeden FIG 2. mmu1ator mu contains: rT - tipleksory 20 and 21. At zero B; 112...

pale silt uprai.p yu emu ehls ls commutator 1b his G1R 1NG1 and bts | | th th infhma-ing inputs pol.kg; yuch (we are responsible to ncruid to his P (.rIyum and ptorpmu outputs with unid. M Lurnajif ; at the upstream input - cooTPi TC iiriiR ;. to the second and first outputs. li; ioK 7 of the etching contains the first 22 and the second 23 triggers, 11ЛМ 24, the generator of 25 pulses and the register 26, sikhr; 1: the outputs whose input is connected generator output

25 pulses, the first - the fourth information inputs. They are connected to the first - the fourth outputs of the ILM 24, respectively, and the first - the fourth outputs to the first - the fourth inputs of the PLM, respectively, the fifth - the seventh inputs of which are 1 cpdPr, , the fifth - the ninth outputs are the first - the fifth outputs R, S1, S2, RA, W of the control unit 7, respectively), the eighth input of the PLA 24 is connected

to the inverse output of the first trigger 22, and the ninth to the njjHMOMy output of the second trigger 23. The synchronizing input of the trip-ra 23 is connected to the ninth (, 1 m output of the PLM 2, the information input with the hopper of the SO mode of the control unit 7, t and: : -;; onchiruyushchy input rpmh-ra 22. .nt and with the reset input S (J bp 7 control, informational 1; X. (); t input 8 logical zero deviceg, and the unit no / iKji / c icH to p to the output of the PLM 24.

As triggers 22, 23, for example, K 155 TM2 microschemes can be used, as a register

26 K 155 And; 1; as GO1 24 - K 556 PT2. the operator of 25 pulses can b1,1t ri) 6pan, kachrikg-r, on the basis of mg circuits K 155 LAZ,

The work of yc rpoj iCTPa is based ;; a pei-iP {; cH) (HoM ci iot oOe descriptions of racic i, concluding-1 hr; to: you are NUMBER1 by PCL P1: snit1, 1.h with outgoing - m Subsequent on. Functions for 4a; aii; ioi; 1Г m, п; л, ч 1; and істестпо прг - ;; 1; 1 ду111 (:-ма ма ма-: function of function. . (11 I4ioii; i;: psl, ra) Are made; / groups, Ka. Kochery take into account. Ii; iToKa data, is - Si, H; -. (H) Begin1; P1 || ..1 li ivMenia functions.

1-.1 whether h; and-hs:; 1 and .4) .. I v: -itЛ i T у1 is precious, e ii, 4. That is the length of i m i i iad, the ratic 1-1 th function; -. T.; - 1: ratios V h:

Y (x-H) Y (x) + h (x); h (x-t-l) h (x) + 2,

if the value of the argument decreases: 5 Y (x) Y (x4.1) - h (x) (3)

h (x) h (x + 1) - 2 (4)

Initial values of functions: th Y (0) O, h (0) 1

l belonging to the interval

x

(x-t Condition of completion of the computational process RA x Xj when calculating the function Y X or RA 1y Y when calculating the function X Y.

Let X and Y be integers, then X is the value of y / L for all I, -and) -.

For example, when presenting X two-decimal places, the value of X 12 is the value of any YG l44, 168.

Based on the above, when calculating by recurrent relations (1) -. (4), the sign of the end of the computational process in the case of calculating the function X Y will be the hit of the given value Y in the interval Y (X), Y (x + 1) -l. In the device, the value of Y (x) is formed at the output of accumulating adder 4, the value of Y (x + 1) -1 is at the output of the combinational adder 17, the comparison of the specified argument value with the interval boundaries is performed in comparison circuits 1.14.

The device works as follows.

The initial state is given by a single signal at input 11 of the device SR. In this state, the first output R of the control unit 7 contains a single signal, which reset the counter 2 and accumulating adder 4. The second third and fifth outputs of the control unit 7 contain zero signals, and the fourth output RA contains a single signal.

The 1st squaring mode is defined by the single signal SQ 1c of the device mode input 18. In this mode, the zero signal from the fifth output W of the control unit 7 through the multiplexer 15 and the switch 16 is connected to the output 19

five

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, lb15

20

25

thirty

35

40

45

50

55

the result of the output device of the accumulating adder 4, to the second inputs of the comparison circuits 1.14 - the direct output of the counter 2.

The arrival of data at the input 13 of the device argument is accompanied by a brief single signal ST at the input 10 of the start of the device. This signal at the first R and fourth RA outputs of the control unit 7 sets the zero signal, and also the control unit .7 controls the signals from the outputs of the comparison circuits 1.14 and from the input 18 of the SQ mode. With this launch discipline, the dynamic error in performing computational squaring operations is zero if the rate of arrival of new values of the argument is not higher than the rate of formation of the result from the previous value.

If the value of the input argument X is greater than the value contained in the counter 2, then the outputs and the comparison circuits 1, 14 and the same-named inputs of the control unit 7 form a combination of signals 10 (see line 1, table 1). In this case, the control unit 7 forms at its third and second outputs a sequence of synchronization signals S2, S1. S2 increases the content of accumulating adder 4, S1 increases the content of counter 2 by one.

If the value of the input code of the argument X is less than the value contained in counter 2, then the outputs and the comparison circuits 1.14 produce a combination of signals 01 (see line 2, table 1). In this case, the control unit 7 forms at its second and third outputs a sequence of synchronization signals S1, S2. S1 reduces the content of counter 2 by one, and S2 reduces the content of accumulating adder 4, since in this case the inputs of the higher bits of the information input of accumulating adder 4 are fed through multiplexer 3 information from the inverse output of counter 2.

As a result of the described actions, the device calculates the function by formulas (1), (2) or (3), (A), respectively.

When the contents of counter 2 are equal, the value of the input argument X (code 00 at the inputs and the control unit 7) at the fourth output of the control unit and at the output 12 of the device result readiness produces a single signal, at the output 19 of the device result the value of the calculated function Y X.

The process of calculating the square root is based on the fact that during the square squaring mode, after the completion of the calculation cycle, the contents of the direct outputs of counter 2 is the square root of the value taken from the outputs of accumulating adder 4.

The mode of the 2nd square root extraction is given by the zero signal SQ 0 from the input 18 of the device mode. In this mode, a single signal from the fifth output W of the control unit 7 multiplexer 15 connects the output of the combinational adder 17 to the second input of the first comparison circuit 1, the switch 16 connects the direct output of the counter 2 to the output 19 of the result, and the second accumulator of the ad accumulator 1 4. As a result of such connections, the values corresponding to the ends of the 5th pal Y (x), Y (x + + 1) -1, 1 stop 1 into which the input argument Y will witness will be supplied to the second input of the comparison circuits 14, 1. 1 st oKOriqaHviH computational process.

After the data is received at the input 13 of the device argument by the ST signal at the input 10 of the device start, the control unit 7 sets the CROWN fourth vrxg, RA to the zero state and starts generating clock pulses S1, S2 into sequences determined by the combination of signals at its inputs

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Tab. 1 shows the operation of the device.

If the value of the input argument Y at the input 13 of the device is greater than the value Y (x + 1) -1, which contains c in the combinational adder 17, then (see line 1, Table 1) the ouixpo signal S2 will increase the content of the accumulating sums pa 4 (Y (x) - Y (x + 1), and mo sync Sig10

-

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nalu S1 - increase} the contents of counter 2 (x + 1).

If the value of the input argument Y at the input 13 of the device is less than the value Y (x) contained in accumulative adder 4, then (see line 2, table 1) the signals S1, S2 will decrease according to the content of counter 2 and accumulating adder four.

When the input argument Y falls into the interval Y (x), Y (x + 1) -l, a combination of signals 00 is received at the inputs of control unit 7 (see line 3, table 1), the clock signals are not generated, output 12 a single signal appears when the device’s result is ready, the output of the device’s result 19 is calculated

15

0

thirty

Sc

40

45

50

55

-value value.

The formation of control signals in accordance with the described algorithm is carried out by the control unit 7 (Fig. 4). If the control unit 7 is constructed, for example, on the basis of a PLA (Fig. 3), then according to the marked flowchart (Fig. 4) in accordance with a known technique, it is easy to construct a tab.G. 2 FUNCTIONS of the control unit 7 and the firmware of the IL (Fig. 5).

The presence of the control block 7 (Fig. 3) of the trigger 22 makes it possible to turn the device for the squaring into the initial position after executing the next calculation cycle if during this cycle or after its termination a pulse unit arrived at the reset input SR of the control unit 7 signal.

The presence of the trigger 23 in the control block 7 excludes the possibility of changing the mode of the device with the static signal SQ from the mode input) i during one calculation cycle (current). The ieriop clock pulses are generated (;; rp 25 pulses are determined by: eus ok-tro action and c: used by us for the erection of .at rvMr-cVropoB and cfr- 1 It; pl.

. The number of the described modes of operation of the device is a poiicTjia calculation, the value goes to ;-: y1; ktsii ocMii n.iHt) for the values of the foretep, the fault; the go value of this function. This 1i) gives you a chip high chipset fast, eG: the effect of ggi o; .: Tke M T.pykh at 713

rascheny argument. In addition, the device has high noise immunity due to noncriticality to single input data failure, since the device monitors any changes in the input argument. If the failure does not lead to a change in the signals at the outputs of the 1.14 comparison circuits, then they do not affect the final result. Otherwise, the device performs the inverse of the required action (for example, instead of the summation, the function increments are subtracted), however, after the restoration of the argument value at the device input, the process of calculating the function will continue until the true result is obtained.

Thus, even in the presence of single input data failures, a correct result will be obtained, and in the general case, the computation time can only increase.

Example 1. Mode 1 ().

The computational process of squaring the number 6 "(OOOllOj) begins after the arrival of the ST signal at the device launch input 10. In this state, the outputs of the comparison circuits 1.14, counter 2, accumulating adder 4 will vary in accordance with the table. 3

PRI mme R 2. Mode 1 ().

Suppose that after the fourth step a failure occurred, as a result of which a zero code was formed at the input. After the current step, the input data was restored and became equal to 6 (0001lOt).

The computational process will occur in accordance with the table. four.

In contrast to Example 1, the number of calculation steps here increased by two, but the final result remained unchanged.

PRI me R 3. Mode 1 ().

Suppose that the value of the argument has changed and become equal (OOOIOOj) as compared with example 1.

The computational process will proceed in accordance with the table. five.

Thus, if for squaring the number in example 1, it would take four steps to calculate the SRI, then in example 3 this operation would be carried out in two steps.

The effect of increasing the speed of the device is greater, the greater

eight

five

about

0

g

Q

g

five

Zelichina input argument and less than the value of its increment.

PRI me R 4. Mode 2 ().

The computational process of extracting the square root of the number (1001012) begins after the signal ST arrives at the device start input.

The output state of the comparison circuits 1.14, counter 2, accumulation and combination adders 4.17 will vary in accordance with the table. 6

The computational process ends when the value of the argument falls in the interval 36, the computed value of the square root is equal to blo.

PRI me R 5. Mode 2 ().

Suppose that after the fourth step of the calculation a failure occurred, as a result of which a zero code was formed at the input. After performing one calculation step, the input data was restored and became equal (100101).

The computational process will occur in accordance with the table. 7

PRI me R 6. Mode 2 ().

Suppose that the value of the argument has changed and become equal (OlOOOi) as compared to Example 4.

The computational process will proceed in accordance with the table. eight.

Thus, the result of the calculation; The square root of 16 is obtained in two steps.

Claims (1)

Invention Formula A device for calculating a power function containing a reversible counter, accumulating adder, the first multiplexer, the first comparison circuit, the first and second elements AND, the microprogram control unit, the start and initial installation inputs of which are connected to the device inputs of the same name, the first output - to the reverse inputs of the reverse the counter and accumulating adder, the second and third outputs are connected to the first inputs of the first and second And elements and to the synchronizing input of the accumulating adder, respectively, and the lateral output is the output of the output of the device, the information input of the device is connected to the first input of the first comparison circuit, the output More, which is connected to the second input of the first And element and to the control input of the first multiplexer, the first and second information inputs of which are connected to the direct and inverse outputs of the reversible counter, respectively, the summing and reading inputs of which are connected to the outputs of the first and second elements AND, respectively, the inputs of the high and low bits of the information The input of the accumulating adder is connected respectively to the output of the first multiplexer and the input of the logical unit of the device, characterized in that, in order to improve accuracy, a second multiplexer, a second comparison circuit, a switch and a combiner adder, the first information input of which is connected to the accumulator adder's output, are introduced into it and to the same input of the switch, the inputs of the higher bits of the second information input of the combinational adder are connected to the direct output rever five 0 G A bi-counter and the second information input to the mmutator, and vhog; the lower order is from the input of the logical zero of the device, the information input of the device is connected to the first input of the second comparison cxt Mbi, the input Less than which is connected to the second input of the second element AND and the output of the second feature of the microprogram control unit, the input of the first prize of the circuit and the mode input of which are connected output More than the first comparison circuit and the device mode input input, respectively, the fifth output of the firmware control unit is connected to the control inputs of the switch and the second multiplexer, the output to The first and second outputs of the switch are connected to the second inputs of the first and second comparison circuits, respectively, the first and second information inputs of the second multiplexer are respectively connected to the output of the combinational adder and the first output of the switch, the second output of the KOTopciro is output from the device. Table 1 Table (jowz .; R Compiled by N. Shelobanova Editor N. Slobod nickname Tehred A. Kravchuk Corrector M. Demchik Order 5191/48 Run 670 VNIIPI USSR State Committee for inventions and discoveries 11-3035, Moscow, Zh-35, 4/5 Raushsk nab. Polygraphic Enterprise, Uzhgorod, st. Project, 4 in OS Subscription