RU2696223C1 - Arithmetic logic unit for generating residual by arbitrary module from number - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: invention relates to computer engineering. Apparatus has three n-bit registers, where n is the number of input numbers, an inverter, (n + 1)-bit adder, a multiplexer, an electronic switch, input and output n-bit buses, and a control unit module.EFFECT: technical result consists in reduction of power consumption.1 cl, 2 dwg

Description

The invention relates to computer technology and can be used in digital computing devices, as well as in digital signal processing devices and in control systems for anthropomorphic manipulators.

A device is known for generating a remainder modulo an arbitrary number, containing the first and second register, the first and second OR elements, a calculator, a first comparison circuit and a multiplexer (USSR Author's Certificate N 1633495, class H03M 7/18, 1989).

The disadvantage of this device is the low speed of the process of forming the residue.

A device is known for generating a remainder modulo an arbitrary number, containing l blocks for the formation of partial residues, (l + 1) modulators, an adder modulo and a coefficient distribution block (RF Patent N 2324972, class G06F 7/72, H03M 7 / 18, 2008).

The disadvantage of this device is the large amount of equipment.

The closest in technical essence to the claimed invention is an arithmetic logic device for performing the division operation, containing three 8-bit registers, an 8-bit adder, a multiplexer, an inverter, a counter of the number of cycles, a circuit for generating the signs of the result, four triggers, input and output buses , a control unit module containing 8-bit divider and dividend registers, a two-channel 8-bit multiplexer, exclusive OR logic elements, an 8-bit adder, eight JK triggers, logic “NOT AND” elements, decoder, inverters, “AND” logic elements, binary 4-bit cycle counter and “OR” logic elements (Babich NP, Zhukov IA Computer circuitry. Construction and design methods: Educational allowance .-- K .: MK-Press, 2004. - 576 p. Fig. 9.22, p. 308-322).

The disadvantage of this arithmetic-logical device is the large amount of equipment.

The technical result of this invention is to reduce the amount of equipment and, as a result, reduce energy consumption by eliminating three exclusive OR elements, eight JK triggers, two inverters, an AND logic element, ten NOT AND logic elements and a logical element OR".

To achieve a technical result, an arithmetic logic device for performing a division operation containing three n-bit registers, where n is the bit depth of the input numbers, an inverter, a multiplexer, a control unit module, input and output n-bit buses, (n + 1) - a bit adder, the first control input of the first n-bit register connected to the first output of the control unit module, and the high-order output connected to the least significant bit of the first information input of the (n + 1) -digit adder, the information input is second the n-bit register is connected to the input n-bit bus, the control input is connected to the second output of the control unit module, and the output is connected to the inverter input, the output of which is connected to the lower n bits of the second information input of the (n + 1) -bit adder, the lower n the bits of the information output of which are connected to the second information input of the multiplexer, a one-bit code of the command for forming the remainder modulo is fed to the first input of the control unit module, an electronic key is entered, and the information input the first n-bit register is connected to the input n-bit bus, the second control input with the fourth output of the control unit module, and the highest bit of the output is connected to the low-order bit of the first information input of the multiplexer, to the highest bit of the second information input of the (n + 1) -digit adder , as well as a logical “1” signal is supplied to its transfer input, and its transfer output is connected to the control input of the multiplexer, the output of which is connected to the information input of the third n-bit register, the control input of which ohm is connected to the third output of the control unit module, the output is connected to the information input of the electronic key, as well as to the senior n bits of the first information input of the (n + 1) -bit adder, the outputs of the least (n-1) bits are connected to the senior (n-1 ) by the bits of the first information input of the multiplexer, the control input of the electronic key is connected to the fifth output of the control unit module, and the output is connected to the output n-bit bus, clock pulses are sent to the second input of the control unit module.

The essence of the invention lies in the implementation of the following method for calculating the remainder R of the number A modulo P. Let

 A = QP + R, (1)

where A is a positive integer from which the remainder must be calculated;

P is a positive integer called the module;

Q is a positive integer that is an incomplete quotient of dividing A by P;

R is a positive integer that is the remainder of dividing A by P.

Moreover

A = a _n-1 · 2 ^n-1 + a _n-2 · 2 ^n-2 +. . . + a ₁ 2 ¹ + a ₀ , (2)

P = p _n-1 · 2 ^n-1 + p _n-2 · 2 ^n-2 +. . . + p ₁ · 2 ¹ + p ₀ , (3)

Q = q _n-2 · 2 ^n-2 +. . . + q ₁ 2 ¹ + q ₀ , (4)

R = r _n-2 · 2 ^n-2 +. . . + r ₁ · 2 ¹ + r ₀ , (5)

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения числа A; where a _i

- coefficients taking the value 0 or 1 depending on the value of the number A;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения модуля P; p _i

- coefficients taking the value 0 or 1 depending on the value of the module P;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения неполного частного Q; q _i

- coefficients taking the value 0 or 1 depending on the value of the partial quotient Q;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения остатка R; r _i

- coefficients taking the value 0 or 1 depending on the value of the remainder R;

n is the number of digits in the representation of numbers.

The task is to find the remainder R from the known A and P. The remainder R is, in terms of number theory, a residue of the number A modulo P, therefore they say that A is comparable to R modulo P:

R (mod P). (6)A

R (mod P). (6)

The value of the remainder R can be calculated as follows:

R = A (mod P) = (a _n-1 · 2 ^n-1 + a _n-2 · 2 ^n-2 +.. + A ₁ · 2 ¹ + a ₀ ) mod P. (7)

Expression (7) can be represented as follows:

R = ((... (A _n-1 · 2 + a _n-2 ) · 2 +.. + A ₁ ) · 2 + a ₀ ) mod P. (eight)

It is known from number theory that the reduction operation is modulo invariant to addition and multiplication, i.e., the magnitude of the remainder does not depend on whether it is calculated on the sum (product) or on each term (factor), and then the corresponding partial residuals are summed ( multiplied) and the remainder is calculated modulo the result.

Based on the foregoing, expression (8) can be represented as

R = ((... (a _n-1 · 2 + a _n-2 ) (mod P) · 2 + a _n-3 ) (mod P) · 2 + ... + a ₁ ) (mod P) 2 + a ₀ ) (mod P) (9)

In this form, the task of finding the remainder R of the number A. is greatly facilitated.

и сравнивается со значением P. Если значение (t₁·2+a_n-3) ≥ P, то из (t₁·2+a_n-3) вычитается значение модуля P, то есть t₂=(t₁·2+a_n-3) - P. Если (t₁·2+a_n-3) < P, то число (t₁·2+a_n-3) остается без изменений, t₂=(t₁·2+a_n-3). Полученное в результате значение t₂ умножается на 2, складывается с

и сравнивается со значением P и т.д. На последнем (n-1)-м шаге число
(t_n-2·2+a₀) сравнивается с модулем P. Если значение (t_n-2·2+a₀) ≥ P, то из (t_n-2·2+a₀) вычитается значение числа P, то есть t_n-1=(t_n-2·2+a₀) - P. Если (t_n-2·2+a₀) < P, то число (t_n-2·2+a₀) остается без изменений
t_n-1=(t_n-2·2+a₀). Полученное в результате значение R=t_n-1 является остатком от деления числа A на число P. When calculating modulo P, the value of the expression
(a _n-1 · 2 + a _n-2 ) is compared with the module P. If the value of (a _n-1 · 2 + a _n-2 ) ≥ P, then from the number (a _n-1 · 2 + a _{n- 2} ) the value of the module P is subtracted, i.e.
t ₁ = (a _n-1 · 2 + a _n-2 ) -P. If (a _n-1 · 2 + a _n-2 ) <P, then the number (a _n-1 · 2 + a _n-2 ) remains unchanged t ₁ = (a _n-1 · 2 + a _n-2 ) The resulting t ₁ value is multiplied by 2, added to

and compared with the value P. If the value (t ₁ · 2 + a _n-3 ) ≥ P, then the value of the module P is subtracted from (t ₁ · 2 + a _n-3 ), that is, t ₂ = (t ₁ · 2 + a _n-3 ) - P. If (t ₁ · 2 + a _n-3 ) <P, then the number (t ₁ · 2 + a _n-3 ) remains unchanged, t ₂ = (t ₁ · 2 + a _n-3 ). The resulting t ₂ value is multiplied by 2, added to

and compares with the value of P, etc. At the last (n-1) -th step, the number
(t _n-2 · 2 + a ₀ ) is compared with the module P. If the value of (t _n-2 · 2 + a ₀ ) ≥ P, then the value of the number P is subtracted from (t _n-2 · 2 + a ₀ ) that is, t _n-1 = (t _n-2 · 2 + a ₀ ) - P. If (t _n-2 · 2 + a ₀ ) <P, then the number (t _n-2 · 2 + a ₀ ) remains without changes
t _n-1 = (t _n-2 · 2 + a ₀ ). The resulting value R = t _n-1 is the remainder of dividing the number A by the number P.

The operation of multiplying by two in calculating the expression (t _i · 2 + a _n-2-i ) in all cases is carried out by shifting all the digits of the multiplicable by one in the direction of the senior. Summation is carried out by applying the coefficient a _i to the least significant bit of the multiplicand. Due to the fact that the coefficients a _i can take the value “0” or “1”, and the least significant bit of the multiplicand after the shift will always be “0”, there will be no transfer to the next bit with this solution.

In FIG. 1 is a diagram of an arithmetic logic device for generating a remainder modulo an arbitrary number.

The arithmetic-logic device for generating a remainder modulo an arbitrary number, contains three n-bit registers 2, 3, 7, where n is the width of the input numbers, inverter 4, (n + 1) -bit adder 5, multiplexer 6, electronic key 8, input 1 and output 9 n-bit buses, the control unit module 10, the input of the remainder 11 formation command, the input of clock pulses 12.

The information inputs of the first and second n-bit registers 2, 3 are connected to the input n-bit bus 1. The first control input of the first n-bit register 2 is connected to the first output of the control unit 10 module, the second control input with the fourth output of the control unit 10 module, and the high-order output is connected to the low-order bit of the first information input of the (n + 1) -bit adder 5, as well as to the low-order bit of the first information input of multiplexer 6.

The control input of the second n-bit register 3 is connected to the second output of the module of the control unit 10, and the output is connected to the input of the inverter 4, the output of which is connected to the lower n bits of the second information input of the (n + 1) -bit adder 5.

To the senior bit of the second information input of the (n + 1) -bit adder 5, as well as to its transfer input, a logical “1” signal is supplied, the lower n bits of its information output are connected to the second information input of the multiplexer 6, and its transfer output is connected to the control multiplexer input 6.

The output of the multiplexer 6 is connected to the information input of the third n-bit register 7, the control input of which is connected to the third output of the module of the control unit 10, the output is connected to the information input of the electronic key 8, as well as to the senior n bits of the first information input (n + 1) - bit adder 5, and the outputs of the lower (n-1) bits are connected to the senior (n-1) bits of the first information input of the multiplexer 6.

The control input of the electronic key 8 is connected to the fifth output of the module of the control unit 10, and the output is connected to the output n-bit bus 9. At the first input 11 of the module of the control unit 10, a one-bit code of the remainder modulo command is supplied, and clock pulses are fed to the second input 12 .

In FIG. 2 is a diagram of a module of a control unit 10 of an arithmetic logic device for generating a remainder modulo an arbitrary modulus of a number.

, r-входовый дешифратор 10.4, n-входовый элемент ИЛИ 10.5, (n-1)-входовый элемент ИЛИ 10.6.The control unit module 10 contains a two-input element AND 10.1, a two-input element is PROHIBITED 10.2, r-bit counter 10.3, where

, r-input decoder 10.4, n-input OR element 10.5, (n-1) -input OR element 10.6.

The first input of the two-input element And 10.1 is the first input 11 of the module of the control unit 10, the second input is the second input 12 of the module of the control unit 10, and the output is connected to the counting input of the r-bit counter 10.3 and to the inhibit input of the two-input element PROHIBIT 10.2, the output of which is connected to the control input of the r-bit counter 10.3, the outputs of which are connected to the corresponding information inputs of the r-input decoder 10.4.

The first output of the r-input decoder 10.4 is connected to the first output of the module of the control unit 10, the second output is connected to the second output of the module of the control unit 10. Each (2k + 1) -th output of the r-input decoder 10.4, where k = 1, 2, ... , n, is connected to the kth input of the n-input OR element 10.5, the output of which is connected to the third output of the control unit 10 module. Each (2k + 2) th output of the r-input decoder 10.4, where k = 1, 2, ... , n-1, is connected to the k-th input of the (n-1) -input element OR 10.6, the output of which is connected to the fourth output of the module of the control unit 10. (2n + 2) -th output r-input A new decoder 10.4 is connected to the fifth output of the control unit 10 module, as well as to the enabling input of the two-input element BAN 10.2.

The remainder of an n-bit number A modulo P is generated in (2n + 2) clock cycles, where n is the bit depth of the input numbers.

In the initial state, the r-bit counter 10.3 is reset to zero, a logical “0” is sent to input 11 of the remainder formation command. To start the operation of the device and throughout the entire cycle of forming the remainder, a logical “1” signal is sent to input 11 of the remainder formation command of the device. In this case, the clock pulses arriving at the input of the clock pulses 12 begin to be counted by the r-bit counter 10.3. The calculation result is fed to the input of the r-input decoder 10.4, and pulses appear sequentially at its outputs with numbers 1, ..., (2n + 2).

With the arrival of the first clock pulse at the input of clock pulses 12, the logical unit signal appears on the first output of the r-input decoder 10.4, which is fed to the output y _{1 of} the control unit 10 module. The signal from the output y _{1 of} the control unit 10 module is fed to the control input of the first n- bit register 2, resulting in the reading of the code of the number A from the input n-bit bus 1 in the first n-bit register 2.

With the arrival of the second clock pulse at the input of clock pulses 12, the logical 1 signal appears at the second output of the r-input decoder 10.4 and is transmitted to the output y _{2 of the} module of the control unit 10. This signal is fed to the control input of the second n-bit register 3, as a result what is the reading into the given register of the module code P.

With the arrival of the (2k + 1) th clock pulse, where k = 1, 2, ..., n, the logical “1” signal appears on the (2k + 1) th output of the r-input decoder 10.4, from where it is transmitted via the n-input OR element 10.5 to the third output of the module of the control unit 10. Then it enters the control input of the third n-bit register 7, as a result of which the next partial remainder is read into the third n-bit register 7.

With the arrival of the (2k + 2) th clock pulse, where k = 1,2, ..., n-1, the logical “1” signal appears on the (2k + 2) th output of the r-input decoder 10.4, from where it is transmitted via ( n-1) -input element OR 10.6 to output y _{4 of} the control unit 10 module. The signal from output y _{4 of} the control unit 10 module is supplied to the control input of the first n-bit register 2, which leads to a shift of the value in it by one bit in side of the elder.

With the arrival of the (2n + 2) -th clock pulse, the logical 1 signal appears at the (2n + 2) -th output of the r-input decoder 10.4, from where it goes to output y _{5 of} the control unit 10 module and to the enable input of the two-input element BAN 10.2 . From the output y _{5 of the} module of the control unit 10, the signal is fed to the control input of the electronic key 8, and the result of generating the remainder of the n-bit number A modulo P is fed from the output of the third n-bit register 7 to the output n-bit bus 9. After the decline ( 2n + 2) -th clock pulse to the inhibitory input of the two-input element FORBID 10.2 receives a logical “0” and a logical “1” signal is set at its output, which is fed to the reset input of the r-bit counter 10.3 and, thus, the counter is reset. The remainder formation cycle is completed.

Consider the work of an arithmetic-logic device for generating a remainder modulo an arbitrary number from a number using an example.

Let n = 4, A = 14, P = 5. The remainder is formed in (2n + 2) = 10 clock cycles.

At the first clock cycle, the module code A = 14 is read from the input n-bit bus 1 into the first n-bit register 2.

At the second clock, the value code P = 5 is read from the input n-bit bus 1 into the second n-bit register 3.

At the third step, since the value of the sum of the doubled zeroed contents of the third n-bit register 7 and the high order A = 1110 _{2 is} equal to one, less than the module P, a new value of the partial remainder q _new = 0001 ₂ is written in the third n-bit register 7, which is the value of the sum of the doubled contents of the third n-bit register 7 and high order A.

At the fourth step, the contents of the first n-bit register 2 are shifted by one bit to the left, in which the value of the factor A = 1110 ₂ is stored, i.e. now in the first n-bit register 2 will be the number 1100 ₂ .

At the fifth step, since the value of the sum of the doubled previous partial remainder q _pre = 0001 ₂ and the highest order A = 1100 _{2 is} equal to three, less than the module P, a new value of the partial remainder q _new = 0011 ₂ is written in the third n-bit register 7, which is the value of the sum of the doubled previous partial remainder q _pre = 0001 ₂ and the highest order A = 1100 ₂ .

At the sixth step, the contents of the first n-bit register 2 are shifted by one bit to the left, in which the value of the factor A = 1100 ₂ is stored, i.e. now in the first n-bit register 2 will be the number 1000 ₂ .

At the seventh step, since the value of the sum of the doubled previous partial remainder q _pre = 0011 ₂ and the high order A = 1000 _{2 is} seven, greater than the module P, a new value of the partial remainder q _new = 0010 ₂ is written in the third n-bit register 7, which is the difference value of the sum of the doubled previous partial remainder q _pre = 0011 ₂ and the highest order A = 1000 ₂ with the module value P = 0101 ₂ .

At the eighth step, the contents of the first n-bit register 2 are shifted by one bit to the left, in which the value of the factor A = 1000 ₂ is stored, i.e. now in the first n-bit register 2 will be the number 0000 ₂ .

At the ninth step, since the value of the sum of the doubled previous partial remainder q _pre = 0010 ₂ and the highest order A = 0000 _{2 is} four, less than the module P, a new value of the partial remainder q _new = 0100 ₂ is written in the third n-bit register 7, which is the value of the sum of the doubled previous partial remainder q _pre = 0010 ₂ and the highest order A = 0000 ₂ .

On the tenth step, the contents of the third n-bit register 7 is supplied to the output n-bit bus 9. Thus, the result of the operation of forming the remainder modulo is 4. The operation was performed correctly, since 14 (mod 5) = 4.

Claims (1)

An arithmetic-logic device for generating a remainder modulo an arbitrary number, containing three n-bit registers, where n is the width of the input numbers, an inverter, a multiplexer, a control unit module, input and output n-bit buses, (n + 1) -bit an adder, wherein the first control input of the first n-bit register is connected to the first output of the control unit module, and the high-order output is connected to the least significant bit of the first information input of the (n + 1) -bit adder, the information input of the second n-bit the histra is connected to the input n-bit bus, the control input is connected to the second output of the control unit module, and the output is connected to the inverter input, the output of which is connected to the lower n bits of the second information input of the (n + 1) -bit adder, the lower n bits of the information output which are connected to the second information input of the multiplexer, a one-bit code of the remainder modulo formation command is fed to the first input of the control unit module, characterized in that an electronic key is entered into it, moreover The input of the first n-bit register is connected to the input n-bit bus, the second control input is connected to the fourth output of the control unit module, and the highest bit of the output is connected to the least significant bit of the first information input of the multiplexer, to the highest bit of the second information input (n + 1) -digit adder, as well as its transfer input, a logical “1” signal is supplied, and its transfer output is connected to the control input of the multiplexer, the output of which is connected to the information input of the third n-bit register the input input of which is connected to the third output of the control unit module, the output is connected to the information input of the electronic key, as well as to the highest n bits of the first information input of the (n + 1) -bit adder, the outputs of the lower (n-1) bits are connected to the highest (n -1) by the bits of the first information input of the multiplexer, the control input of the electronic key is connected to the fifth output of the control unit module, and the output is connected to the output n-bit bus, clock pulses are fed to the second input of the control unit module, and The module control unit comprises a two-input AND gate, two-input inverted element, n-OR input elements, (n-1) -vhodovy OR element, r-bit counter, wherein

, the r-input decoder, and the first input of the two-input element And is the first input of the control unit module, the second input is the second input of the control unit module, and the output is connected to the counting input of the r-bit counter and to the inhibit input of the two-input element BAN, the output of which is connected to the control input of the r-bit counter, the outputs of which are connected to the corresponding information inputs of the r-input decoder, the first output of which is connected to the first output of the control unit module, the second output connected to the second output of the control unit module, each (2k + 1) -th output, where k = 1, 2, ..., n, is connected to the k-th input of the n-input element OR, the output of which is connected to the third output of the control unit module , each (2k + 2) th output of the r-input decoder, where k = 1, 2, ..., n-1, is connected to the k-th input of the (n-1) -input element OR, the output of which is connected to the fourth output control unit module, (2n + 2) the output of the r-input decoder is connected to the fifth output of the control unit module, as well as with the enable input of the two-input element BAN.

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