SU1270765A1 - Statistical analyzer - Google Patents

Abstract

The invention relates to the field of computing and information technology. The purpose of the invention is precision. For this, the analyzer additionally contains a second counter, a signal distributor, and a control unit circuitry characteristic of the technical solution. The principle of operation is to accumulate information about a random process in accordance with the algorithms for obtaining the density and distribution function by the method of discrete samples. The statistical analyzer makes it possible to additionally measure the integral distribution law and to improve the analysis accuracy by using i signal distributor instead of the analog block of the time delay of the prototype. 1 il. N o O) SL

Description

The invention relates to information and measuring technology and can be used to derive the distribution laws of measuring information.

The purpose of the invention is to increase the accuracy and expand the functionality of the analyzer, by determining not only the differential, but also the integral law (function) distribution.

The drawing shows the structural scheme of the proposed statistical analyzer "

The analyzer contains an analog-to-digital converter (ADC) 1, control unit 2, distributor of 3 signals, random access memory (RAM) 4, counters 5 and 6, elements NOT 7-10 of control unit 2, elements OR 11-16 of control unit 2, nor , elements AND 17-24 of control block 2.

Since at the output of ADC 1, the process X (t) under investigation is presented in the following digital codes (discrete sampling method), the estimates of the distribution laws are determined in accordance with the expressions;

integral law (distribution function)

(x, N, At) |,

differential law (density, distribution)

1 Gh

pn

f (x, N, At, 4x)

where At is the sampling interval

x (t);

n is the number of codes whose value is not less than x for the distribution function or is in the interval X + A X for the density p asc;

dx is the interval between analysis levels (quantization step

ADC);

N is the total number of samples, both when determining the differential and when determining the integral distribution law. The accumulation of information in the analysis process is carried out by the first counter 5, and

its storage is in the random access memory 4. Accumulation of information (formation of density or distribution function) is carried out when the statistical analyzer is operating in the input mode (logical 1 or high potential at the input) I / O. Setting the analysis mode (determining density or

distribution functions) is carried out by supplying a logical O or 1J, i.e. low or high potential to the second input of the I / L mode. Clocks are continuously applied to the TI input. These signals go directly to the inputs of the statistical analysis control unit 2. The inputs of this block also receive signals

conversion end of the ADC transfer: P from the output of n bit of the second counter a and hell from the distributor of 3 signals, Qj from the output of the (n + 1) th bit of the second counter 6.

The analyzer is started by applying a start pulse both when determining the differential law (at the output I / D is logical 0) and the integral law (at the input

I / L - logical 1), Before launch, logical 1 is fed to the first input of the input mode setting (I / O), i.e. set the mode of entering information (storage).

It should be noted that the inputs of the zero setting of the first 5 and second b counters and the distributor of the 3 signals have priority over the other inputs of the corresponding blocks. The information input of the statistical analyzer is the information input of the A / D converter 1, and the output is the output of RAM 4.

Claims (1)

Before the start of the analysis, the RAM 4 is reset. After the start pulse is applied, the second counter 6 is set to zero, from the Q output the logical zero signal through the NOT 10 element opens the I-Time clock pulses from the output of the HE 9 element through AND 20 and OR 14 to the summing input of the second counter 6, and direct TIs through AND 24 and IZH 16 to the read entry input of RAM 4. In this case, logical Q is written to all cells of RAM 4 starting from zero. The addressing of the RAM 4 cells is carried out with the help of the second counter 6. Upon completion of the zeroing, a pulse ne is formed at the output of the second counter 6 and is set to 1 renos P bit Q In the future, the analyzer operates as follows. When determining the differential distribution law (at the input I / D logical 0), elements AND 17 to 23 are opened. The transfer pulse P, through the element OR 11, And 17 and OR 13 starts A1 SCH 1. At the end of the conversion, the input to the ADC 1 of information a signal in the form of a continuous random process x (t), the output of ADC 1 produces a pulse of the conversion end (CP), which writes the digital code x- (t) to the second counter 6. This code, acting on the address inputs of RAM 4, connects to the output RAM A is the corresponding memory location. At the same time, the signal KP through the elements AND 23 and OR 15 starts the distributor of 3 signals, to the clocking C-input of which the clock pulses T are received. At the same time, at the outputs a, a, a, and of the distributor of 3 signals successively impulses arise, according to which information from the corresponding cell of RAM A is recorded in the first counter 5 (a), 1 (a) is added to the number recorded in the first counter 5 and by one the number is written by the signal aj through the element OR 16 at the same address. The signal ac restores the distributor of 3 signals to the initial (zero) state and through the elements OR 11, AND 17 and OR 13 again performs the start of the ADC 1. Then the described process repeats until the potential (logic 1 ). The distribution of the integral distribution law (at the input I / D - logical 1) not only the first start of the ADC 1, but all subsequent ones occur under the influence of the transfer signal P, from the output of the second counter 6, and the start of the distributor 3 signals occur under the action of an end pulse conversion (KP) from the output A1 A1 and 1 from the output of the distributor 3 signals. The first P, after zeroing RAM, starts A1ch 1 through the chain: AND 18 and OR 13. The code from the output of ADC 1 is entered into the second counter 6 by the same signal KP through the circuit HJW 12, AND 22, OR 15 The 3 signal distributor is triggered. Under the action of signals from the output of the distributor of 3 signals a, a., A, the recording of information from the corresponding cell A of RAM, its increase by one and recording at the same address occurs. According to the signal a of the distributor, 3 signals of the latter are set to the initial (zero) state and the same pulse and through the elements of AND 19 and OR 1A increased: y-. The contents of the second counter 6, i.e. initiates the next address of RAM A and through the elements OR 12, I. 22, OR 15 again starts the distributor of 3 signals. This procedure of increasing the addresses of the RAM cells A and their contents per unit and its subsequent recording at the same addresses continues until the pulse of output of P, the second counter 6, does not appear, which will restart A1 18 again through circuit 18, OR 13, and so on, as long as a high potential is present at the I / O input (logical 1). Thus, when determining the integral distribution law for each sample of the random process x (t), the addition of the unit occurs not only to the number written at the address corresponding to the sample code, but also to the numbers written in RAM A to all addresses large code received on output of the ADC 1. The end of the analysis and the output of information about the density or distribution function is as follows. A low potential (logical 0) is set at the I / O input of the analyzer and the analyzer’s start pulse is again given. This sets the second counter 6 to zero and the output of RAM A appears at the output of RAM A. The next clock pulse TI, after removing the start pulse through AND 21 and OR 1A, increments the content of the second counter 6 by one The address inputs of RAM A receive an address code equal to one, and the output of RAM 4 is the contents of the first RAM cell; The second GI allows output of the second cell of RAM A to the analyzer output, and so on. This procedure continues until the output Qri + t of the second counter 6 is set to 5, physical 1. Thus, all the cells of RAM 4 are sequentially selected and at the analyzer output we have the ordinates of the differential or integral distribution law. The statistical analyzer contains an analog-to-digital converter whose information input is the information input of the analyzer, a control unit, a random access memory, m information outputs of which, where (1) is the number of histograms of the histogram, are connected to the information analyzer and are connected by cm information the inputs of the first counter, m of the information outputs of which are connected respectively to the m information inputs of the random access memory, characterized by in order to increase accuracy, it contains a signal distributor and a second counter, and the control unit contains from the first to the sixth OR elements, from the first to the fourth HE elements, from the first to the eighth AND elements, and the second outputs of the second counter are connected correspondingly with n address inputs of the random access memory (where 2 is the number of analysis levels, and n information inputs of the second counter are connected respectively with n information outputs of the analog-digital converter, the output of the conversion end It is connected to the recording input of the second counter and to the 40 first inputs of the second OR element and the seventh element AND block, control, the overflow output of the nth digit of the second counter is connected to the first inputs of the first OR element and the second element AND control block, the output (n + 1) the second bit of the second counter is connected to the input of the fourth element NOT of the control unit, the first output of the signal distributor 50 flax with the recording input of the first counter, the summing input of which is connected to the second output of the signal distributor, the third output of which is connected to the first input of the sixth element: W) of the control unit, and the fourth the second input of the sixth elements AND, the output of the fourth element NOT of the control unit is connected to the third inputs of the quarter, fifth and eighth, elements AND, the input starts the analog-digital converter connected to the output of the third element OR of the control unit whose inputs are connected respectively to the outputs of the first and 45 with the output of the sixth IS element, the second input of which is connected to the output of the eighth element I, and the analyzer start input is connected to the inputs for setting the first and second counters and the signal distributor to zero. 65, the output of the signal distributor is connected to the second inputs of the first and second OR elements and the first input of the third element AND control unit, the input clock of the analyzer is connected to the input of the third element NOT, the first inputs of the fifth and eighth element AND control unit and the clock input of the signal distributor, the first The input of the analyzer mode is connected to the input of the second element NOT and the first input of the first, the second input of the second, the first input of the fourth and the second input of the eighth element I of the control unit, the second The first input of the analyzer mode is connected to the input of the first element NOT, the third input of the second, the second input of the third and the first input of the sixth elements AND of the control unit, the output of the first element NOT of the control unit is connected to the second inputs of the first and seventh elements of the control unit, the outputs of the second and third elements are NOT connected respectively to the second inputs of the fifth and fourth elements AND, the outputs of the first and second elements OR of the control unit are connected respectively to the third input of the first and second elements AND, s the peace input of the second counter is connected to the output of the fourth element OR, whose inputs are connected to the outputs of the third, fourth and fifth elements AND; the trigger input of the signal distributor is connected to the output of the fifth element OR whose inputs are connected to the outputs of the sixth and seventh elements AND; read RAM is connected J4 g |