SU1257635A1 - Device for displaying information on screen of cathode-ray tube - Google Patents

Abstract

The invention relates to the field of digital computing and can be used in digital data input / output devices on a television indicator for displaying alphanumeric and graphical information, in particular, when constructing display devices in test automation systems. The aim of the invention is to improve the speed of the device. The device contains a cathode-ray tube, a control unit, a sign generation unit, the first, second and third OR elements, a raster point counter, a scale memory block, a graphite memory block, the first, second and third comparison blocks, first, second, third, the fourth, fifth and sixth registers, marker and time counters, input block, marker abscissa binary code generator, character storage block, graph ordinate counter, code-time converter, linear approximation block, first and second switching blocks. The introduction of new blocks and connections allows the automatic generation of linearly varying values of data arrays for imaging, as well as scaling of graphs according to an arbitrary law. 3 hp f-ly, 17 silt, 2 tab. sl N9 L e: "9: d

Description

The invention relates to digital computing and can be used in input-output devices of digital data on a television indicator for displaying alphanumeric and graphic information, in particular when building display devices in test automation systems.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a block diagram of the device in FIG. 2 is a block diagram of a binary abscissa code generator; FIG. 3 is a code-time converter circuit; in fig. 4 is a block diagram of a linear approximation unit; in FIG. 5 is a block diagram of the control unit i in FIG. 6 is a block diagram of a data input unit; FIG. 7 is a diagram of the first register; FIG. 8- I7 - timing charts of the device.

The device contains a cathode ray tube 1 (Fig. 1), a control block 2, a symbol generation block 3, the first element OR 4, a raster point counter 5, a first comparison block 6, a first register 7, a chart memory block 8, a scale memory block 9 , second comparison block 10, second register 11, third register 12, third comparison block 13, fourth register 14, marker counter 15, current time counter 16, second and third elements OR 17 and 18, data entry block 19, fifth register 20 , shaper 21 binary code abscissa marker, block 22 memory characters, the sixth register 23, the counter 24 ordinates of graphs, converter 25 code - time, linear approximation block 2b, first switching block 27, second switching block 28, first counter 29 (Fig. 2), second counter ZOR first trigger 31, second trigger 32.5 first and second elements And 33, 34 ,, the first frequency divider 35, the first and second switches 36 and 37, the seventh register 38, the eighth register 39, the third element AND 40, the fourth element And 41, the ninth register 42 (FIG. the fourth comparison block 43, the first memory block 44, the ten register 45 the eleventh register 46, the third counter 47, the fifth element AND 48, the sixth element AND 49, the first degaif

Rator 50, seventh element, And 51 | the twelfth register 52 (Fig. 4), the first frequency multiplier 53, the first frequency divider 54, the third counter 55, the second frequency divider 56, the second frequency multiplier 57, the thirteenth register 58, the second decoder 59, the fourth element CMM 60, the fourth counter 61, third trigger 62, five counter 63, eighth, ninth, tenth, eleventh elements 64-67, fourth trigger 68, fifth counter 69 (figure 5), twelfth element 70, fifth fifth-5 71 , AND-OR element 72, first memory block 73, sixth counter 74, thirteen element AND 75, seventh counter 76, third switch 77, second block 78 of memory, eighth counter 79, fourteenth and fifteenth elements AND 80, 81, fifth element ИШ1 82, third decoder 83, d, eighth counter 84, tenth counter 85, fifth and sixteenth elements And 86, 87, third memory block 88,

89 clock pulse generator; register 90 modes, the sixth element OR 91, the first block of 92 buttons, the fourth switch 93, one-shot 0 94, the sixteenth element And 95, the eleventh counter 96, the second block 97 buttons, the third block 98 buttons; the seventeenth element And 99 (FIG. 7), register 100, memory block 101, de 5 encoder 102.

The device works as follows.

The control unit 2 generates horizontal and frame synchronizing pulses (second and third outputs) with a period of 64 µs and 20 ms, respectively (Fig. 8), as well as interlace-scan control pulses with a period of 40 ms (tenth output) and pulses with a frequency of 1 Hz to run the counter 16 times (fourteenth exit) ..

The image on the screen of the cathode-ray tube 1 is obtained by arranging sequential illumination or darkening of the image elements synchronously with the movement of the beam across the screen. The number of elements in the image is VxH, where V is the number of points in the television line, determined by the device’s clock frequency f, H is the number of lines, with the electron raster0

five

50

55

3

The radial tube 1 is rotated 90, so that the beam moves from bottom to top on the screen from left to right. The set of picture elements V-h forms familiarity, where h is the number of lines, V is the number of points along the line, participating in the formation of the symbol.

The dot decomposition of the symbol is formed by a 3 character generation block, with pulses of frequency f / 2 arriving at its input (where f is the initial frequency of the device operation), and the first and second information inputs are supplied with the current column number of the decomposition of the sign (h) and sign code (Fig. 9).

It should be noted that screen captions are divided into two groups: permanent for a particular test mode and variables. For example, information such as the MODE VIBRATION, CHANNEL 1, TIME J31 / 00/00 (changing information is underlined) can be referred to as permanent labels. Variable labels include numerical values of quantities and their dimensions. The permanent inscriptions are placed in the block 22 of the character memory, and the variables are stored in the output registers of the following blocks: in the range register 20, the time counter 16, the marker abscissa binary 21, the code-time converter 25, the register 23, the register 14 channel numbers. Moreover, in the range register 20, the binary-decimal value of the maximum value of the graph along the abscissa is stored. The resolution of the register of 20 range is T) decimal digits. The time counter 16 stores the current test time, which is changed by pulses with a frequency of 1 Hz, arriving at the first input from control unit 2. The digit D is equal to 6 decimal places (two digits per indication of hours, minutes, and seconds).

In the binary abscissa marker generator 21, a binary-decimal value is stored along the abscissa axis of the discrete graphical reference selected by the operator. Maximum bit size DJ, Dj (,. In code converter 25 - time, the binary-tenth ordinates of the first and second graphs of the selected operator are stored.

rum graphic reference. The resolution is determined by the accuracy of the display of the graphs and the range of variation along the axis of the order: Dj 5 + iD, where and AD are the number of ten digits, respectively, to display the maximum value of the range - zone and the resolution of the graph on the ordinate axis,

 O in general register 23 temporarily stores information not required by the operator during operation of the device. This may be, for example, the power of the vibrostand, the sensitivity of the sensor, the number of averages.

etc. The size, Dj, is chosen from the condition D, makc {D2, where D is the size of the i-th value, assigned to general register 23. 20 In the channel number register 14, the sensor number is stored, from which a similar signal is being transmitted to the device operating in the i complex with the proposed device. 5 The size T) n is determined by the number of sensors.

The organization of the first switching unit 27 is defined as, where B is the size of block 27, is equal to the number of binary digits to encode one character, and D is the number of channels equal to the number of alphanumeric characters switched out, b D, g - i-Dj, tD ,,, + D, o, where 5 Dj3 is the number of characters simultaneously issued by the block of 22 character memories and equal to 1.

The control unit 2 detects the address (second information output) 0 switched by the first channel switching unit 27 and the address (first information output) character in the character storage unit 22, if the output of the first switching unit 27 is supplied 5 output of the character storage unit 22. Formation of addresses occurs synchronously with the moving of the beam on the screen. This ensures the necessary arrangement of all the displayed Q-but-digital information.

The formation of graphs on the screen of the cathode-ray tube 1 occurs as follows (Fig. 10). During the period of the inverse sweep of the lowercase rotation, the values of the ordinates of the graphs selected from the block 8 of the graph memory are sequentially entered into registers 7 and 12, and the address is given

from the counter 24 graphs ordinates. During the next straight line scan, a 5 point counter is started, the value of which is fed to the address buses of the scale memory block 9, from which discrete values of the scaling function (x) are selected for each graph point along the ordinate axis. These values are fed to the information inputs of the blocks 6 and 10 of the comparison, the inputs of which receive codes from registers 7 and 12, Blocks 6 and IO of the comparison give out a signal in case

(i)

 U :,

where B, B ,, j are the binary values of the ordinates in registers 7 and 12; y, i - respectively, the value of the scaling function and the number of the point on the y-axis,

The signal from the comparison unit 6 organizes the formation of a light point, and the pulse from the comparison unit 10 ends the illumination of the light line, started by starting the counter of 5 points. Thus, one graph is obtained in the form of points of light, and the other in the form of vertical lines of lower brightness. The luminance decrease occurs due to the video signal being supplied to the fourth input of the cathode ray tube, which has a lower video signal gain than the third input. Non-linear dependencies can also be used as scaling functions. For example, the inverse function can be used to display graph values in a logarithmic scale, where x is the logarithmic scale value corresponding to the ordinate axis. In this case, the size of the registers 7 and 12 and the graphics memory block 8 is determined by the range of change of the function (x) In addition to the alphanumeric and graphic information, the screen displays the horizontal lines of the selected scale values (seventeenth output of the control block 2) and

graphic marker in the form of vertical-, counting in block 8 of the graphics memory

Noah light line (the output of the block 13 comparison). Video signals of the first graphic, sign information.

occurs as follows. The backbone sets the graphic marker to the desired location on the screen, then

25

2576356

the lines and the marker are collected by the OR logic and fed to the third input of the cathode ray tube 1.

J marker occurs as follows. The marker counter 15 stores the current binary value chosen by the operator of the ordinates of the graphs. This value can be successively changed by applying pulses of the reverse counting through the elements OR 17 and 18 from the input block 19 or the linear approximation block 26, the contents of the counter 15 of the marker nonf5. Are continuously compared with the counter code of 24 ordinates of the graphs, and if they match, it is output the signal from comparison unit 13,

Entering the digital in device

20 formations, as well as control of operating modes, are performed by input unit 19. In this case, the first information output receives the code of the input character, followed by a clock signal from the first output and a mode code at the second information output. The following modes of operation of the device are possible: writing to the register 20 of the range, writing to the time counter 16, starting it up and switching the operating mode on an overflow signal; writing to the converter code 25 is the time of the value of the ordinate of the graph specified in the graphic position

jr marker; writing to general register 23; write to the register 4 channel numbers; changing the total map of permanent inscriptions by switching areas of the character storage block 22, selecting, at the request of the operator, any possible scaling function by switching areas of the scale memory block 9, writing graphical samples once to the graphics memory block 8; linear approximation of the graph on two counts; input of graphs from the information input of the device into block 8 of the memory of Graphs-, output of graphs, channel numbers, range numbers, binary values specified in general-purpose register 23 of the values from the device.

Once - write graphic

thirty

40

45

50

occurs as follows. The operator sets the graphic marker to the desired location on the screen, then

cut block 19 entered code converter 25 - time is entered decimal: iii h (. ordinate of graph. Converter 25 decimal value of chart converts into a pulse proportional to duration, at the end of which a record is organized into the second register 11 of the code from block 9 Since the formation of a pulse synchronously with the sweep of a graphic image, at the moment of recording in the second register 1 1 the binary code corresponding to the duration of the pulse from the converter output is present at the output of the scale memory 9. 25 and, consequently, the decimal value of the graph ordinate, taking into account the scaling function. Since the conversion is repeated cyclically, the second register 11 stores the code that is written to the chart memory block 8 by the operator’s command ( one or several buttons) In this case, on the reverse of the vertical scan, the counter of the 24 ordinates of the graphs, using the signal from the thirteenth output of the control unit 2, records the address of the position of the graphic marker, and the eighth pulse in The output of the control unit 2 is organized by recording the contents of the second register 1 through the second switching unit 28 to the block 8 of the graphics memory. In this case, the input unit 19 provides the necessary switching of the information input of the second switching unit 28 to its output.

A two-point linear approximation of the graph is performed as follows. The last graphic count of the previous approximation stage is used as the first reading, the second reading is written to the linear approximation block 26 from the second register t. Moreover, block 26 linear approximation counts the number of ordinates, which moved the graphic marker relative to the first reference. After assigning the second ordinate of the graph in the second register 11, at the operator's command, the linear approximation block 26 begins the automatic formation of a sequence of values of the graph ordinates according to the formula

eight

ZllZl m

where u - i-th countdown graph; TCU corresponding initial and 5-terminal codes of the ordinate of the schedule;

m is the number of points on the x-axis in the interval between the approximated readings,

10 Each value y, through the second switching unit 28, is fed to the first information input of the graphics memory block 8, where the next ordinate value is written down by the tenth output of the control unit 2, and from the third output of the block 26 linear approximation, the signal of the readiness of the code to 20 entries in the block 8 of the graphics memory is removed.

The input of graphs from the information input of the device into the block 8 of the graph memory occurs under the control of an external device that issues information. When the exchange is ready, the external device generates a gating signal (1) (see FIG. II), which prohibits the regeneration of the graphic image and switches control of the counter 24 ordinate graphs to the second input of the device, where the synchronization signals for inputting the data supplied on the information input device. The signals are received by the control unit 2 and, on their basis, generates control pulses for the counter 24 ordinates of the graphs and the writing to the graph memory block 8. At the end of the exchange, external device 0 removes the strobe signal and the regeneration of the graphic image is resumed. The graphics output from the graphics memory block 8 to the external device is carried out according to information and information (2). The timing diagram of the output cycle (Fig, 11) differs from the input only in that ;; The data from block 8 of the graphics memory is read before the next pulse arrives at g to the second input of the device. The output of the binary values of the range register 20, the channel number register 14, the data from the generator 2 of the abscissa values of the graph is transmitted over the second 5 switching unit 28 to the instrument output output and is accompanied by clock signals from the first device.

Shaper 2 of the binary code of the abscissa of the marker works as follows (see Fig 2). The first input of the block receives half-frame synchronization pulses with a period of 40 ms. Pulses with frequency f are fed to the second input, the current binary value of the graphic marker is present at the first information input to the second and third information outputs, respectively, the range number on the abscissa axis and the binary-decimal value, which is in general register 23, are fed. Shaper 21 generates the binary-decimal value of the position of the graphic marker on the abscissa axis with regard to the range and converts the binary-decimal value code into a binary one.

Let the device have the ability to work on N - ranges of the graph on the abscissa. Each i-th range corresponds to the maximum value x),;,. If the device forms the Ng ordinates of the graph, then the position on the abscissa of the k-th ordinate with the i-M range will be

 .

(one)

For the implementation of (), an impulse transform method is used. Its essence is that two sequences of pulses are formed with the ratio of the following periods

Tr

t:

NO

(2)

and k

pulses with a period of decay x pulses.

T. where

X k

Jo

Tr

Frequency divider 35 generates F sets of pulse sequences with different periods of the input signal of frequency f. Switches 36 and 37 switch to the output, respectively, pulse sequences with periods of Tp and T, depending on the number of the range. On the positive edge of the half-frame synchronization pulse. (The tenth output of the control unit 2), the code from the counter is entered into the first reversible counter 29

25763510

15 marker, the second reversible counter ZP is nullified, and the trigger 31 is set to one, allowing pulses to be fed to the negative counts of the counter 29 and the positive counting of the counter 30. After applying pulses to the 29 k counter, it generates an overflow pulse that flips the trigger 31 to zero

 Thus, the counter is thereby counted by the counters 29, 30 and organizes the writing to the register 39 of the code. From the reversible counter 30. The up / down counter 30 is binary-decimal, therefore, according to 5 (3), the binary position value of the marker is written to register 39 for i-ro range.

Binary value generation

20, magnitude 1 is organized similarly, with the only difference that, according to (3), the reversible counter 29 is turned over the negative front of the half-frame synchronization signal, the trigger 32 is set to one and the binary-decimal number from register 23 is entered into the reversible counter 30 general purpose. Mortgage

D pulses from reversing counter 30 are added and the same number is added to reversing counter 29 until an overflow pulse is generated by reversing counter 30. In this case, trigger 32 is set to zero, counting is disabled, and register 38 is written as the binary decimal equivalent the value of the value stored in general register 23.

Transducer 25 code - time is designed to form the binary-decimal values of the ordinates of the first and second graphs, corresponding to the position of the graphic marker, and works as follows. The mode information code from input block 9 comes to the second information input of the block. If the mode corresponds to the input of the graph ordinate, then the decoder 50 generates a write enable signal to the register 42 (offset). The value of the ordinate is recorded sequentially in binary-decimal digits, while from the input block 19 the sign code is sent to the information input of the converter 25, and a synchronization signal is sent to the sixth input. When the beam of the screen of the cathode ray tube I to 11

falls into the position of the graphic marker; a sequence of pulses corresponding to the movement of the beam along the line (see Fig. 13) is fed to the counting input of the zero pre-zeroed during the return stroke, the lines are arranged vertically. The counter 47 code coincides with the position of the beam along the line, and from memory block 44 a binary-decimal value is extracted that is proportional to the position of the beam and depends on the range of variation of the graph along the ordinate axis

L7 -

where y is the binary-decimal code, read from memory block 44 and corresponding to the k-th position of the graph point along the vertical; max range of graph variation along the y axis; L is the number of quantization levels

graphics.

When the code from memory block 44 coincides with register code 42, comparison block 43 generates a signal that records the binary ordinate value of the graph to register 1I, taking into account the scaling function, which can then be written to the graph memory block 8 by an operator command. When the beam of the cathode-ray tube hits the position of the marker, elements 48 and 49 are also opened, permitting the passage of pulses proportional in duration and position to the values of the ordinates of the first and second graphs, respectively (see, FIG. 13). By the first signal (fourth transducer input 25 ) recording is organized into register 45, and the second signal (third input) is organized into register 46 of binary-decimal codes from memory block 44 corresponding to the position of the beam at the moment of recording,

The linear approximation block 26 is intended to form a sequence of linearly dependent codes that fill in free graphic samples between two samples of f and graphics, while

VK-VM

m

y C. U - Z. (4)

"- TPP1

ha

5763512.

For implementation (4, a pulsed g: method is used, according to which for the transformation interval T, Yc and Y | pulses are formed, with 5 T yMau (, t, where t is the period of the pulse sequence, are divided into that and simultaneously algebraically the previous value of the graph's ordinate. Thus, by the 10th end of the interval T, the value of the ordinate is formed.

The linear approximation unit 26 operates as follows (see FIG. 4). From the input unit 19, the initial state setting mode is supplied to the second tS information input of the linear approximation unit 26, according to which the decoder 59 generates the reset signals of the register 20 52, counter 55 and counter 63,

The graphic marker is then moved to the position of the next specified ordinate. Synchronously with the movement of the marker and, the state of the reversing counter 63 / first input of the positive and the second input of the negative count of the reversible counter 63 changes. Thus, when the graphic marker is set to 0, the ordinate set in the reversible counter 63 is stored value of t. Code Y | register 52 is fed from register 1 1, the code Y ,, for the first linear approximation section is zero and placed in the reversible counter 55. With the arrival of the Run linear approximation mode input block 19, the decoder 59 generates a signal (second output) of the 0 The register is 52 of the y code, into the 58 register of the ordinate of the y code, into the counter 61 of the 2t code and installation of the flip-flop 62. anak Then, the half-frame synchronization signals subtract the unit from counter 61 through 0 element 66 and simultaneously apply a negative count pulse to counter 15 of the marker through element 64 until the second output of counter 61 does not have a logical zero level. The second output of the counter 61 is set to the most significant bit of the 2fn code. Thus, the logical zero level at the output

the counter 61 is formed after subtracting m units from it, so the graphic marker is set to the position corresponding to the height, and the logical zero level from the second output of the counter 61 opens the element And 67, On the leading edge of the half-frame synchronization signal (see FIG. the trigger unit 68, and the signals with the frequency f (the second input of the linear approximation unit 26) are fed through the element 67 to the inputs of the frequency multipliers 53 and 57. The multipliers 53 and 57 form the output and the first output, respectively, of the pulses They can be built on k 155IE8 elements.8 Frequency dividers 54 and 56 form y, t and y and t, respectively, on the outputs and can be variegated, for example, on elements K155IE7, the pulse sequence is fed to the first input of the positive, and YY / T to the second input of the negative count of the reversing counter 55 according to (4). The counting continues until an overflow signal is generated at the second output of the frequency multiplier 57, which is outputted to the input of the frequency multiplier 57 will come at +1 pulses. Trigger signal 68 is set to zero by the overflow signal, the counter 55 is disabled, and a code reception readiness signal (the third output of linear approximation block 26) generated in the reverse counter 55 is generated. In addition, a positive edge of the frame synchronization signal is arranged marker in the next position to record the ordinates; With the arrival of the next synchronization signal of the half-frames, the cycle of formation of the ordinate y, is repeated and the required increment (4) is added to the contents of the reversing counter 55. After the m half-frame synchronization signals are applied, the first overflow output of the counter 61 generates a zero reset signal for the flip-flop 62 and zeroing the reversible counter 63. Thus, the linear approximation of the section ends, and the 26 l block; counter

55, the code is obtained from the previous section of the next section.

The control unit 2 operates as follows. At the output of the generator 89 clock pulses, signals of rectangular pulses of frequency f are applied, fed to the fourteenth output of control unit 2 and to the counter input 69 points, in which the beam position code along the line on the screen of the cathode ray tube 1 is obtained. OS is the number of points used to reverse the line scan. A signal of duration is removed from the counter output of 69 points.

k - 6h 2f

(five)

For counting the counter 84 lines. 84 line counter has a conversion factor

No. 4 (H + OK),

(6)

where OK is the number of TV lines used in the reverse frame.

Factor 4 is based on the fact that the 84 line counter counts signals that are half the length of a television line for two half-frames (for interlaced scanning, two half-frames are shifted half a line. When forming symbols in the formation of one point, the signals from the first and second half-frames are used for create a flicker-free image, and the signal from the first or SECOND half-frame participates in the formation of the graphic ordinate in order to increase the resolution in the axial absciss. Overflow signal output from counter 84 lines arranges count of the counter 85 frames. Since the repetition frequency of half images is 25 Hz and the frame counter 85 has a conversion factor K ,. 25, the output pulses from the fourteenth i Hz frequency 2 receives the control block.

The counters of the 69 points and the 84 lines are fed to the address inputs of the memory blocks 73 and 78, at the outputs of which synchronization and control signals are generated;

respectively put in table. 1, 2 and fng, 15,16.

Table 1

Output

Signal assignment of memory block 73

Counter count 24 graphs ordinates

Counter count 76 character positions along the line

Lowercase quench pulse

Horizontal sync pulse that launches horizontal scan

Strobe signal of the graphic part of the line

Record in the register 12

Write to first register 7

The sync signal of the decomposition of the sign along the line

Signal marking of the graphic floor (illumination of the graphic support levels)

Tabliya2

Output

Signal allocation of memory block 78

Frame damping pulse

Frame sync pulse that triggers a frame scan

Semi-frame sync signal (high level means odd half frame, low level even)

The signal strobe graphic part of the frame

Signal signal position of the mark along the frame scan

These signals are generated by reading according to the corresponding

5763516

to the addresses of logical units previously placed in blocks 73 and 78, the elements 70, 86, 87 form logical conjunctions of the signals fed to their inputs 5.

On the reverse line scan (line quenching pulse), the counter 76 of the character position on the line is wrapped and the counting of the 24 ordinates of the graphs through the AND-OR 72 element is forbidden. Similarly, the frame 79 of the sign position by zero frame and set to one

15 flip-flops 71, management of writing to the block 8 of the graphics memory from the block 26 of the linear approximation and from the block 19 input through the elements 80 and 8F, respectively. On the forward run of a frame and line scan (absence of extinguishing pulses), a counter is arranged for 76 character positions on a line, the period of counting pulses is / f, the conversion factor of 76 characters for a character line is equal to

V-TB V

0

five

0

five

0

five

The period of the counting pulses of the counter 79 of the position of the mark across the frame is equal to the length of the television line (64 µs), and the pulses themselves are formed from the counter 84 lines. The information outputs of the counters 76 and 79 are connected to the address inputs of the memory block 88, from which the control codes for switching the information channels of the first switching block 27 are selected. In other words, in memory block 88, information is recorded to place all displayed characters in the proper order. The outputs of the counters 76 and 79 are provided to the first information output of control unit 2 for addressing the character storage unit 22.

When exchanging graphic arrays from the external device, the signal of the exchange strobe is given (the second input of control unit 2). This signal sets zero to trigger 71, which prohibits the counting of 5 points (via element 70), and also counts 24 ordinates of graphs, and allows control of the indicated-gm counter by signals from an external device via the AND-77 element.

(see FIG. 11). The same signals are organized in the graphic memory block 8 via the switch 77. Switching the switch 77 channels is controlled by the decoder 83, to which the mode code is fed from the viod block 19. In addition, in the manual input mode of the graph at the output of the decoder 83, a recording signal is additionally generated, gated with a frame damping pulse and switched to the output of the switch 77 to record in block 8 of the chart memory, In the linear approximation mode, to the write input of block 8 The graphs connect the readiness code of the linear approximation block 26 (the sixteenth input of the control block 2), also gated with personnel fi pm pulse. Gated personnel damping pulses (elements 80 and 8) readiness signals (from linear approximation block 26) and manual input (from decoder 83) are collected using OR logic (OR element 82) to form a signal for recording the position of a graphical marker in the counter 24 of graph ordinates at the time of writing the ordinate to the block 8 of the graphics memory.

Block 19 input works as follows. Pulses of frequency f are supplied to its first input and through element I 34 enables the counting of counter 30 (see Fig. 2), sequentially connecting the output of each button, block 92 of the buttons to the output of switch 93. If the button is not pressed, the first input of element 95 count resolution is applied (via the one-shot 94). When the button is pressed in the block 92 at the moment of its switching at the output of the switch 93, a logic zero level is formed, which starts the single vibrator 9A for the duration of the elimination of the buttons (K + 1-N),

The signal from the one-shot 94 generates a pulse to write the button code, and the code itself is stored at this time in counter 96, the count of which is prohibited by the same pulse. The button code (K + l + N) matches the channel address of the switch 93 and is used to transmit decimal digits and characters to the corresponding blocks of the device. The operation mode of the device is set by the block 98 of buttons. When pressing the corresponding button with a signal from the output

HJIIi 91 in the register 90 is entered the unitary mode code supplied to the second information output of the input unit 19, to the second input of which an overflow signal is sent from the time counter 16, which wraps the mode register 90. The button unit 97 controls the movement of the graphic marker.

Range register 20 accepts a range number code by a write signal in the presence of an appropriate mode decoder 102 and element 99J. At the same time, the binary-decimal value corresponding to the range number is read from memory block 101. For example, if the abscissa axis has the dimension of frequency and the first range is 0-625 Hz, then the inscription 625 Hz is read from memory block 10.

Thus, the introduction of new blocks and links allows to increase the speed of image formation due to the automatic generation of linearly varying values of the data array. At the same time, in comparison with the prototype, additional possibilities appear; conversion from a binary-decimal code to a binary one and vice versa, taking into account the coefficient, scaling the graph according to an arbitrary law (including nonlinear).

Claims (4)

Invention Formula 1 A device for displaying information on a cathode-ray tube (CRT) screen containing a control unit, the first output of which is connected to the first input of the character generator, the output of which is connected to the first input of the first OR element, the output of which is connected to the CRT modulator, the system of which is connected to the second and third outputs of the control unit, the fourth output of which is connected to the input of the raster point counter, the second input of the first element OR is connected to the output of the first comparison unit, the first input which is connected to the output of the first register, the first input of which is connected to the output of the memory block diagrams, block memory scales, the second comparison unit, the second and third registers. the third comparison block, the fourth — the register, the marker counter, the current time counter, the second and third elements OR, the data input unit, the fifth register, the marker abscissa binary code generator, the memory block of characters, the sixth register, which are In order to increase the device speed, an ordinate counter of graphs, a code-time converter, a linear approximation unit of the first and second switching switches were entered into it, the first and second inputs of the control unit being the first and second inputs of the device, the third input of the unit The control unit is connected to the first output of the data input unit connected to the first inputs of the fifth register, current time counter, converter code - time, character storage unit, sixth register, fourth register, linear approximation unit, second switching unit and scale memory unit, the second and third outputs of the data input unit are connected respectively to the second and third inputs of the fifth register, current time counter, converter code — time, the sixth and fourth registers, the fourth output of the data input unit n the first input of the second OR element and the second input of the linear approximation unit, the third input of which is connected to the fifth output of the data input unit connected to the first input of the third OR element, the second inputs of the third and fourth OR elements are respectively connected to the first and second outputs of the linear unit approximation, the third output of which is connected to the fourth input of the control unit, the fourth and fifth outputs of which are connected respectively to the fourth and fifth inputs of the converter code - time, the sixth input to The second input of the second comparison unit is connected to the output of the scale memory unit connected to the second input of the first comparison unit and to the first input of the second register, the second input of the scale memory unit is connected to the output of the point counter the raster, the output of the second register is connected to the second input of the second switching unit and 25 the fourth input block linear approximation, quarters; the output of which is connected to the third input of the second switching unit, the fourth input 5 of which is the third input of the device, the output of the second switching unit is the output of the device and connected to the first input of the graphics memory whose output is connected to the terminal the input of the second switching unit and the first input of the third register, the output of which is connected to the second input of the second block, the second input of the third register is connected to the sixth output of the control unit, the seventh output of which is connected to the second input of the first p gistra, the eighth output of the control unit is connected to the second input of the graphics memory block, the third input of which is connected to the output of the ordinate counter of graphics that is connected to the first input of the third comparison unit whose second input is connected to the output of the counter of the marker connected to the first inputs of the counter Chick of the ordinates of the graphs and the generator of the binary code of the abscissa of the marker; the first and second inputs of the marker of the marker are connected to the outputs of the second and third elements of the SHTI, the output of the third comparison unit is connected to the third input of the first OR element and to the seventh input of the converter 5, the code is the time, the eighth input of which is connected and the second outputs of the converter code - the time is connected respectively to the first and second 0 inputs of the first switching unit, the third input of which is connected to the first output of the fifth register, the second output of which is connected to the second input of the forms The binary marker abscissa binary code 5 and the sixth input of the second switching unit, the seventh input of which is connected to the output of the fourth register connected to the fourth input of the first 0 switching unit, the fifth input of which is connected to the first output of the current time counter, the second output of which is connected to to the ninth output of the control unit, connected to the 5th fifth input of the linear approximation and to the third input of the generator of the binary abscissa code of the marker, the fourth input of which is connected to 21 the tenth output of the control unit connected to the sixth input of the linear approximation unit, the fifth input of the marker marker binary code is connected to the output of the sixth register connected to the test input of the first switching unit, which is connected to the first output of the binary code block generator of the marker, the second input which is connected to the eighth input of the second switching unit, in my input of the first switching unit is connected to the output of the character storage unit, the second input of which is connected to the eleventh input the control unit, the twelfth and thirteenth outputs of which are connected respectively to the second and third inputs of the graph ordinate counter, fourteen output of the control unit is connected to the fourth input of the current time counter, the fifteenth input of the control unit is connected to the ninth input of the first switching unit whose output is connected to the second input of the generation unit the third input of which is connected to the sixteenth output of the control unit, the seventeen output of which is connected to the fourth input of the first element OR, the third output of the converter code - time is connected to the second input of the second register. 2. The device according to claim 1, wherein the TeMj generator that the abscissa binary code generator of the marker contains the first counter, the first input of which is the first input of the former, the fourth input of which is connected to the second and third inputs of the first counter, to the first and second inputs The second counter, to the first inputs of the first and second triggers, the output of the second trigger is connected to the first inputs of the first and second And elements, the second inputs of which are the third input of the driver connected to the input of the first frequency divider connected to the first inputs of the first and second switches, the second inputs of which are the second input of the former; the first output of the first counter is connected to the first input of the seventh register; the second input of the first counter is connected to the first input of the eighth register 0 7635 22 Pa and the second input of the first trigger, the output of which is connected to the first inputs of the third and fourth elements, the second inputs of which are connected to the outputs of the second and first switches, respectively, the outputs of the third and first elements of And are connected respectively to the fourth and fifth inputs of the first counter, the outputs of the second and the fourth And elements are connected respectively to the third and fourth inputs of the second counter, the fifth input of which is the fifth input of the former, the first input of the second counter is connected to the input to smogo register whose output is the first output of the second output of the second counter is connected to a second input of the second flip-flop and a second input of the seventh register, whose output is the second output of the shaper, 3. The device according to claim 1, 1, 5, and 5, in order to transform 0 The time code contains the ninth register, the first input of which is the first input of the converter, the output of the ninth register is connected to the first input of the fourth comparison block, the output of which is the third output of the converter, the second input of the fourth comparison block is connected to the output of the first memory block connected to the first inputs of the tenth and eleventh registers, the input of the first memory block is connected to the output of the third counter, the first and second inputs of which are the fourth and fifth inputs of the converter with accordingly, the second input of the tenth register is connected to the output of the fifth element I, the first input of which is the seventh input of the converter connected to the first input of the sixth element And, the second inputs of the fifth and sixth element And are the eighth and sixth inputs of the converter, respectively The input of the converter is the input of the first decoder, the input of which is connected to the first input of the seventh element AND, the second input of which is the third input of the converter, the outputs of the seventh and sixth element AND to the second inputs of the ninth and eleventh registers respectively. the outputs of the tenth and eleventh registers are respectively the second and third outputs of the transducer, 4. The device according to claim 1, characterized in that the linear approximation unit contains a twelfth register, the first input of which is a quarter input of the block, the output of the twelfth register is connected to the first input of the first frequency multiplier, the output of which is connected to the first input of the first frequency divider, the output of which under the keys to the first input of the third counter, the second input of which is connected to the output of the second frequency divider, the first input of which is connected to the output of the second frequency multiplier, the first input of which is connected to the output the thirteenth register, the first input of which is connected to the output of the third counter, which is the fourth output of the block, the third input of the third counter connected to the first output of the second decoder, connected to the first input of the fourth OR element and the second input of the twelfth register, the second decoder input is the first the input of the block, the second output of the second decoder is connected to the third input of the twelfth register, the input of the thirteenth register and the first input of the fourth counter and the third of its trigger, the second input Werth counter pod2.) 764S2 A the key to the output of the fifth counter, connected to the second inputs of the first and second frequency dividers, the first and second inputs of the fifth counter are 5, respectively, the second and third inputs of the block, the third input of the fifth counter is connected to the output of the fourth element OR, the second the input of which is connected to the first output of the fourth of the fourth counter, connected to the second input of the third trigger, the output of which is connected to the first inputs of the eighth, ninth and tenth elements And, the second inputs of the eighth and 15th and ninth elements And connected to the second The fourth output of the fourth counter, connected to the first input of the eleventh And element, the second input of the tenth And element, is the 20th sixth input of the block, connected to the third inputs of the eighth and ninth And elements, and to the first input of the fourth trigger, the second input of which is connected to the second input 25 of the frequency multiplier, the output of the fourth flip-flop is the third output of the block and is connected to the second input of the eleventh element I, the third input of which is the fifth input 30 of the block, the output of the eleventh element AND is connected to the second input first and second frequency multipliers, the output of a tenth AND gate is connected to the third input of the fourth J ka counters, the outputs of the eighth and ninth AND gates are respectively first and second block outputs. velvd  f "{ XI3 f CpattTfjf. 4fI I G I L. 0tjff.9 (fiueiO / Record ЖПЛГ .... .umr Yirir 2 {ciept) I g i t gz - “i 4g and tut 1Shch yes 7 shtshsh :::: fJ (rig 8 (fiueiO X X X t t I W And If Ml I I AI I 6 W 43 45 (pt / el3 67 i I r 1 I tI 57 IiII  t f II t  S6 5 II fie. 74. . L / E ilMMI  J I "niitumiunniimuimtintiiiiiii . 7 Jill fie.hz tintinUHIilH Jl Jt-tt one I I , I I M n I I t n I t I I n t I I I I I I I J-LTUU-LTL JTJTrirUT 95 ill I 1 I 9Z 94 9B Editor I.Rybchenko Compiled by L.Abrosimov Tehred I.Popovich M.Samborska Proofreader Order 4957/47 Circulation 671. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. d. 4/5 Production and printing company, Uzhgorod, st. Project, 4 JTJTrirUT (rig 16 i I 1 I I i i t I (pus. 17