SU1180834A1 - Electronic chronometer system - Google Patents

Abstract

ELECTRONIC CHRONOMETRIC SYSTEM containing a primary clock consisting of a series-connected crystal oscillator, a frequency divider, pulse counters, the outputs of which are connected to the inputs of a parallel time code converter to a serial unit-decimal code and to the inputs of indicators, with the intermediate outputs of a frequency divider connected to the corresponding decimal code with the inputs of the marker marker pulses, the information pulse puller, and the pulse width calibrated pulse former, the course of which is connected to the second input of the information. pulses, and the outputs of the drivers of information and marker pulses are connected to the corresponding inputs of the converter of a parallel time code to a serial unit. but a decimal code, a communication line and a secondary clock consisting of a counting decade with a decoder, the information outputs of which are connected to the corresponding inputs of digital indicators, the common electrodes of which are connected to the corresponding outputs of the switch, in order to simplify installation and excluding secondary clocks, in the primary clocks a sequential single-decimal code transducer is entered into the pulse number code and a driver of the information-power signal, and at the secondary clocks we introduce power the rectifier, the half-wave extraction unit from the signal, the pulse shaper, the AND circuit and the circuit. MA OR, with the output of the primary clock calibrated by the pulse width is connected to the pen S to the o inputs of the transducer of a serial unit-decimal code (L to the pulse number code and the driver of the information-power signal, and their second inputs are connected respectively to the outputs of the formers pulsing and marker pulses, the output of the converter of a parallel time code into a serial unacoustic-decimal code is connected to the third input of the converter of the sequential CX) decimal code 00 in the pulse number code, the output of which is connected to the third input of the information power signal generator, the output connected via a two-wire line to the input of the power rectifier and the input of the half-wave block, the first output of which is connected to the counting input of the switch , the first input of the OR circuit and through the pulse shaper with the first input of the AND circuit, the second input connected to the second output of the half-wave extraction unit and the second input of the OR circuit, the output connected to C4eTHbuvc input of the counting deck dy with decoder, input

Description

The zero setting of which is connected to the stroke of the circuit AND is connected to the input of the pulse driver maker, and the zero output of the switch.

1180834

The invention relates to instrumentation, in particular to digital chronometric systems, in which information on current time values is transmitted to secondary devices in coded form, and can be used in the construction of clock systems for various industrial and cultural enterprises, facilities, and also in everyday life. The purpose of the invention is to simplify the setting and switching off the secondary clocks. Figure 1 shows the structural scheme of the electronic chronometric system; 2 shows timing diagrams for its operation. Primary clock 1 contains a quartz oscillator 2, a divider 3, frequency counters 4 pulses, digital indicators 5, a converter 6 of a parallel time code into a sequential unit-decimal code, a generator of 7 marker pulses, a driver of 8 information pulses, a driver of 9 calibrated in duration pulses, the converter 10 of a serial unit-decimal code into a number of codes and a shaper 11 of information power signals, a two-wire communication line 12 and a secondary clock 13. with a digital display s containing power vtr DC converter 14, bl. 15 of the half-wave from the signal, the switch 16, the OR circuit 17, the pulse former 18, the I-19 circuit, the counting decade 20 with the decoder and digital indicators 21. In the primary clock, the output of the quartz oscillator 2 is connected to the successively connected divider 3 frequencies and the counters 4 pulses, the outputs of which are connected to the digital indicators 5 and the inputs of the converter 6, the intermediate outputs of the frequency divider 3 are connected respectively to the inputs of the formers 7–9, the output of the imaging unit 9 is connected to another input of the imaging unit 8, and the outputs of the generator The drivers 7 and 8 are connected to the corresponding inputs of the converter 6, the output of the driver 9 is connected to the first inputs of the converter 10 and the driver 11, and their second inputs are connected respectively to the outputs of the driver 8 and 7, the output of the converter 6 is connected to the third input of the converter 10, the output of which is connected with the third input of the driver 11, the output of which is connected to the two-wire communication line 12. In the secondary clock 13, the communication link 12 is connected to the power supply rectifier 14 and block 15, one output of which is connected to the counting input of the switch 16, the input of the OR circuit 17 and, through the driver 18, to the input of the circuit AND 19, and the other output of this block 15 through the circuit And 19 and OR 17 are connected respectively to the installation input About the switch 16 and the counting input of the counting decade 20, the input is set-. ki About which is connected to the output of the pulse generator 18, and the outputs of the decoder of the counting decade 20 are connected respectively to the combined sign electrodes of the digital indicators 21, the common electrodes of which are connected to the outputs of the switch 16. The system works as follows. The pulses generated by the quartz oscillator 2 are fed to a divider 3 frequencies, from the output of which pulses with a frequency of, for example, 1 Hz are fed to a binary-decimal time counter 4, the state of which is indicated by digital indicators 5. From the intermediate outputs of the divider 3 frequencies to the drivers 7-9, signals with different frequencies are received, at. This shaper 9 produces pulses calibrated by duration, following, for example, with a duty cycle of two (FIG. 2a). With the help of these pulses and signals with divider 3

shaper 8 produces bursts of information pulses, for example, ten pulses in each burst (Fig. 26). The shaper 7 generates marker pulses, which mean the beginning of the transfer of the sprinkling of the current time code and follow at the beginning of every sixth packet of information

pulses (fig. 2b) if a six-bit time code is transmitted (hours, minutes and seconds). Under the influence of marker pulses coming from the driver 7, inforg; The time from the counters of 4 pulses in the parallel binary-decimal code is copied to the converter 6, in which this information is converted by means of pulses from the generator 8 to the sequential unit-decimal code (Fig. 2d).

Then, the sequential time code from converter 6 is fed to converter 10, in which, with the participation of signals from drivers 9 and 8 (respectively Fig.2a, b), the sequential unit-decimal code (Fig.2g) is converted into a serial pulse number, then arrives to one input of the imaging unit 11, to the other two inputs of which the marker pulses are received from the imaging unit 7 (FIG. 2B) and the duration-calibrated pulses from the imaging unit 9 (FIG. 2a), under the influence of which the imaging unit 11 organizes information and force si Nala (2E). The informational power signals have a rectangular alternating polarity and follow with a duty cycle of two, and the impulses of, for example, positive polarity are superimposed with information about the current time values in the form of higher frequency pulses (coinciding with the pulses in the packet shown in FIG. .2b), i.e. Each positive pulse of the power signal is modulated by a series of pulses, the number of which is in the series (Figure 2d) and carries information about one value of the decimal digit, and at zero value of the decimal digit, the corresponding power signal does not superimpose. The marker pulse (Fig. 2b) shifts the leading edge of every sixth positive pulse of the power signal by the time it takes off.

(Fig.2d). Further, the information-power signal from the output of the imaging unit 11 via the two-wire communication line 12 enters the secondary clock 13 with a digital indication.

In the secondary clock 13 with digital indication from the communication line 12, the alternating voltage of a rectangular shape is fed to the power rectifier 14, from which the necessary voltages for supplying the electronic part of the secondary clock are removed, and, moreover, to block 15, which represents It is a two-way double rectifier with two outputs, which are removed separately from both positive and negative half-waves of the input alternating voltage, but already one polarity, for example positive (Fig. 3e, g). The rectified signals of the same polarity from both outputs of block 15 are sent to the OR circuit 17, from which the sequential number-impulse time code is removed in the form of bursts of pulses (FIG. 3), the number of pulses in each of which carries information about one decimal digit. These pulses are then fed to the counting input of decade 20, which, prior to the arrival of each bundle of information pulses, is set to zero position by narrow pulses (Fig. 2h) from the output of the imaging unit 18, formed by it on the falling edge of the calibrated pulses taken from one of the outputs of block 15 (Fig.2e). As a result

in decade 20, one decimal digit value is recorded, which in parallel code is applied to the respectively combined sign-forming electrodes of digital indicators 21. At the same time, the switch 16 under the influence of incoming pulses from the output of the block 15 that passes on its counting input goes from one states and connects the common electrodes of the digital indicators 2 to the power source at those times when the state of the decade 20 does not change. At the same time, on indicators 21 sequentially one after the other all primary data transmitted by the primary clock 1 displays chronometric information, and with a frequency that does not cause digital indicators 21 visible for the observer to flash. To ensure common mode operation of the switch 16 relative to the analogous primary clock unit to its installation input About arriving marker pulses (Fig. 2k), which are extracted from the information signals taken from the second output of block 15 (Fig. 2g) by AND 19 circuit using pulses from Atel 18 (Fig. 2z).

Thus, the introduction in the primary clock of the converter of a sequential unit-decimal time code into a number-pulse and formaSrig .1

The information signaling signal reader and, in the secondary clock with digital indication, the introduction of a power rectifier, a half-wave separation unit, a pulse shaper, an AND circuit and an OR circuit allows the secondary power supply channel to be combined with a communication channel due to the high energy intensity of the information and power signal. In addition, the proposed signal format simplifies the input circuitry of the secondary clocks due to its high informative capacity.

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Claims (1)

ELECTRONIC CHRONOMETRIC SYSTEM, comprising a primary clock, consisting of a series-connected quartz oscillator, a frequency divider, pulse counters, the outputs of which are connected to the inputs of the parallel time code converter into a serial single-decimal code and to the indicator inputs, and the intermediate outputs of the frequency divider are connected respectively to the inputs shaper of marker pulses, shaper of information pulses and shaper of calibrated pulse duration, output to which is connected to the second input of the information shaper. pulses, and the outputs of the shapers of information and marker pulses are connected to the corresponding inputs of the parallel time code to serial decimal code converter, a communication line and a secondary clock consisting of a counting decade with a decoder, the information outputs of which are connected to the corresponding inputs of digital indicators, the common electrodes of which connected to the corresponding outputs of the switch, characterized in that, in order to simplify the installation and turn off the secondary clock, in the primary clock input a converter of a sequential single-decimal code to a pulse-number code and a driver of the information-power signal are introduced, and a power rectifier, a block for extracting half-waves from the signal, a pulse driver, an I circuit, and a circuit are introduced in the secondary clock. OR, and the output of the shaper calibrated by the duration of the pulses of the primary clock is connected to the first inputs of the converter of the sequential single-decimal code 'to the number-pulse code and the shaper (information-power signal *, and their second inputs are connected respectively to the outputs shapers of informational and marker pulses, the output of the parallel time code to serial decimal code converter is connected to the third input of the serial ten an additional code into a pulse-number code, the output of which is connected to the third input of the information-power signal driver, the output connected through a two-wire line to the input of the power rectifier and the input of the half-wave input unit, the first output of which is connected to the counting input of the switch, the first input of the OR circuit, and through pulse shaper with the first input of the AND circuit, the second input connected to the second output of the half-wave allocation unit and the second input of the OR circuit, * the output connected to the counting input of the counting decade with a decoder , Zero setting input of which is connected to the stroke of the AND circuit is connected to the input of the pulse shaper ustavyhodu and Novki You are a zero switch.