SU1166126A2 - Interface - Google Patents

Abstract

DEVICE FOR PAIRING on author.St. No. 736086, characterized in that, in order to increase the reliability of information transmission of the device, a comparison block, a preventive mode trigger and two AND elements are entered into it, the first, second and third inputs of the first element AND are connected to the corresponding bit outputs of the readiness register of the program and the output of the trigger of the preventive mode, the unit and zero inputs of which. connected to the device mode setting input and to the seventh MBJM output of the synchronization unit, the eighth output of which is connected to the first input of the second element AND, the second, third and fourth inputs of which are connected respectively to the first outputs of the respective subscriber subscriber and the comparison output block, the control input of which is connected with the output of the first element I, and the first and second information (User inputs - respectively with the second outputs of the respective subchannels of subscribers, the output of the second element AND connection en with the sixth entry of the register of exchange.

Description

1 1 The invention relates to computing and can be used in computer systems to interface a digital computer with external devices. According to the main auth. No. 736086 is known an interface device containing a subscriber subchannels, a priority block, a synchronization block, a READY register. programs, information switchboard, control unit Modulo, exchange register, the first input and output of which are, respectively, the first information inputs and output of the device, the exchange control unit, the first inputs and into the course of which are the corresponding control input and output , and the second input and output are connected respectively to the first output and input of the synchronization unit, the second and third outputs of which are respectively connected to the first inputs of the subscribers' subchannels and the control input of the priority block, the inputs behind which are connected to the first outputs and the second inputs of the respective subchannels of subscribers, the third outputs of which are connected to the control outputs of the program readiness register connected by the information input and output respectively to the second output and input of the exchange register, and the control input the fourth output of the synchronization unit, the fifth output of which is connected to the third input of the control unit modulo, connected by the first input and output respectively to the third output the input of the exchange register, and the second input to the third output of the control unit, the fourth output of which is connected to the fifth input, the exchange register, the fourth output and input of which are respectively connected to the information input and output of the information switch, whose control input is connected to the sixth the output of the synchronization unit, and the outputs and inputs of the group of information inputs and outputs and the inputs of the group of address inputs, respectively, are connected to fourth entrances, second and third outputs of the corresponding subscriber channels, The information inputs and control outputs and inputs of which are with the second information inputs (outputs) and the second control inputs and outputs of the device, respectively, and each subscriber subchannel contains a control node, a register of service signals, the first input and output of which are connected respectively to the first the output and input of the control node, and the second output and input are respectively the control output and the subchannel input, a transfer type switch connected by the first input and output respectively the first output and input of the subchannel swap register, the second input and output of which are respectively the fourth input and the second output of the subchannel, the AND element whose first input is the third input of the subchannel and the output connected to the second input of the control node, the third and fourth outputs of which are connected respectively, with the second control input of the transfer type switch and the third input of the subchannel exchange register, and the fifth output with the third output of the subchannel, readiness trigger connected by the input and output respectively The output of the control node and the first output of the subchannel, the information input (output) of which is the second input (output) of the transfer type switch, and the OR element, whose inputs are the first and second inputs of the subchannel respectively, and the output are connected to the second input of the And disadvantage element The known device consists in low reliability of information transfer. The aim of the invention is to increase the reliability of information transfer. This goal is achieved by the fact that a comparator block, a preventive mode trigger, two AND elements are entered into the device, the first, second and third inputs of the heart And element are connected to the corresponding bit outputs of the program readiness register and the preventive mode trigger, single and zero inputs. which are connected respectively to the input of the device mode setting and to the seventh output of the synchronization unit, the eighth output of which is connected to the first input of the second element I, the second, third and fourth The inputs of which are connected respectively with the first outputs of the respective subchannels of subscribers and the output of the comparison unit, the input input of which is connected to the output of the first element AND, and the first and second information inputs correspondingly with the second outputs of the corresponding subscanded subscribers, the output of the second element AND connected to the sixth entrance of the register of exchange. FIG. T is a block diagram of the device J in FIG. 2 — a block diagram of a subscriber's sub-channel; Figures 3-5 are functional diagrams of a synchronization unit, a subscriber control node and an exchange control unit. The device (FIG.) contains an exchange register 1, an exchange control unit 2, a synchronization unit 3, a priority unit 4, 5 subscriber units, a control unit 6 modulo, information switch 7, program readiness register 8, comparison block 9, preventative mode trigger 10, first element 11 and second element 12. The device communicates with the exchange processor 13 and with subscribers (external devices) 14, and with each subscriber 14 exchange roiskhodit two channels through the Channel 5 "and 5 ,,. Subchannels 5 subscribers (figure 2) contain a subchannel exchange register 15, a subchannel control unit 16, a slash signal register 17, a transfer type switch 18, a subchannel readiness trigger 19, an AND element 20, an EI 21 element. Synchronization unit 3, a control unit 16 and a unit 2 exchange control can be implemented on the basis of the microprogram control principle. Each of them contains (FIGS. 3-5) a constant memory block 22, a micro-command address decoder 23, a micro-command address 24, a micro-command address modifier 25. Blocks 3 and 2 and node 16 operate in accordance with the firmware recorded in block 22 of the permanent memory. The processing of external signals is performed by the modifier 25. The device operates as follows. 264. The exchange processor 13 at the beginning of operation issues a command of the operating mode on the exchange register 1, which is decoded by block 2, which in turn starts block 3, preparing it for autonomous work on receiving and sending information. The processor 13 then issues the word state, which is transmitted via register 1 to register 8, where; during the entire exchange, up to the change of the contents of the register 8. After writing to register 8, block 3 starts the subchannels 5 by applying signals to the inputs of the OR 21 elements. The output signal from the OR 21 element passes through the AND 20 element only if there is a signal from the corresponding bit register 8 on the element And 20. In this case, the signal through the element And 20 passes to node 16, initiating the start of autonomous work of subchannel 5, Running subchannels 5 operate simultaneously and independently, outgoing (or receiving) one word of information into (or from) external device in accordance with a specific time diagram of the latter. Receiving or issuing the word of subchannels 5 is completed by setting trigger 19 to a single state and transitioning subchannel 5 to a state of waiting for communication with register 1. The information exchange of subchannels 5 ready for exchange with the processor 13 occurs in two stages identical for all subchannels 5 In the first stage, the synchronization unit 3, by signaling to the priority unit 4, selects the number of the senior subchannel from among those set ready. Unit 4 allows the operation of one subchannel 5, issuing a signal through the element OR 21 and the element AND 20 to the node 16, which, through the corresponding input of the information switch 7, writes the number of the subchannel 5 to the exchange register 1 with modulo three control bits generated by the control unit 6 position code, i.e. with 1 in the corresponding bit, and starts block 2, which controls the issue of the number of the channel selected under. from register 1 via information buses in parallel code to processor 13, Processor 13 in this novelty

The measure is prepared by the address of the buffer zone of the memory for writing or reading information from the user.

At the second stage, the information word itself is transferred from the selected subchannel 5 to register 1 via switch 7 or vice versa from register 1 to subchannel 5 via switch 7. In this case, the information word is exchanged in a parallel code, and the node exchanges the information word with processor 13 . 16 and block 3, which, by applying a pulse signal to switch 7, transmits a word between registers 15 and 1,

Block 6. At the same time, under the influence of a signal from block 2, it controls the information word, for example, modulo three when receiving information from the processor 13 and generating control bits modulo three when transmitting information in the exchange process. In addition, block 6, under the influence of the signal from block 3, produces control or processing of the check bits in the information word when exchanging with external devices in accordance with a specific type of control received in this external device.

After the end of the second stage, the cycle repeats in the general case with the participation of another subchannel, and Similar. Rule (1st is characteristic of multiplexed channel time sharing between many external devices 14 and exchange processor 13.

Above was described the operation of the device for the exchange with external devices 14, each of which corresponds to its own subchannel 5 ..

Among external devices, 14 --i4j can be very important, the exchange of information with which should occur with maximum confidence. Let, for example, such an important subscriber is external device 14, which with a certain cyclical nature entails an array of finite length with finite increments of data values. A significant increase in the reliability of the proposed device is achieved by parallel reception of information from the external device 14. via the exchange channel through subchannels 5, and 5jj, and the operation of these subchannels takes place in parallel and independently

Simultaneously, so that each subchannel at the same time writes an array of the received information into its memory zone of the exchange processor 13. With a parallel reception of each word of information subchannels 5 | f and 5. will simultaneously put up their readiness on triggers 19 for block 4 priorities. The contents of the information words on the registers 15 of the subchannels 5 and 5, respectively, arrive at the first and second information inputs of the comparison block 9, where they are compared to each other under the influence of a control signal from element 11. At the input of element 11, signals from the outputs of the corresponding bits Dov register 8 program readiness and trigger 10 preventive mode. In the normal operating mode, the trigger 10 is set at the start of operation in the O signal from block 3 (Operating mode).

The signal to the unit input of the trigger 10 exchange processor can set this trigger in the preventive mode. In this case, the operation of block 9 will be blocked,

Block 9, comparing word-by-word information of the indicated subchannels, results in a signal only in case of a mismatch of the values of the information words. This. the signal passes through the element 12 and is recorded as a special feature in the highlighted bit of register 1, on which the information word from subchannel 5p or 3p, is also recorded. This tagged word is transmitted to the corresponding receiving zone of the processor 13 when communicating with one of the subchannels. The program of external communications of the processor 13, when processing the receiving array for any functional task, view the words of the array and reach the word with the label, includes a special subroutine that defines the healthy channel with appropriate functional methods of information reliability control.

The mismatch signal from block 9 passes through the AND 12 element under the influence of a pulse signal from block 3 only under the condition of simultaneous readiness for the exchange of subchannels 5p and 5 ,,

The processor 13, giving the signal to the input of the trigger 10, can transfer 711 the entire entered scheme to the prevention mode, blocking the labeling. If a subroutine malfunctioning subchannel is detected, software control allows you to easily exclude this nonchannel from the task exchange, Hattpimep, the zero value of the corresponding register bit 8. At the same time, the faulty subchannel will not start at all, block 9 will not work in the working mode, and the external device 14 will occur only on one subchannel 5 or 5,, providing possible. the prevention and repair of the equipment of the channel of the communication line without stopping the reception of data from an important subscriber. Thus, the device allows you to increase the reliability of data transmission from important subscribers without time-consuming from subchannels and by recording signs in unmatched words. In the event of a single channel failing, information will flow differently and the system will not be disturbed. In the event of failures in words, it becomes possible to correct data arrays using a software method in the exchange processor.

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Claims (1)

DEVICE FOR PAIRING No. / 36086, characterized in that, in order to increase the reliability of transmitting information of the device, a comparison unit, a preventive mode trigger and two AND elements are introduced into it, and the first, second and third inputs of the first AND element are connected to the corresponding bit outputs of the readiness register programs and the trigger output of the preventive mode, the single and zero inputs of which are connected respectively to the input of the device mode setting and to the seventh output of the synchronization unit, the eighth output of which is connected to the first input to the second element And, the second, third and fourth inputs of which are connected respectively to the first outputs of the corresponding subschannels of subscribers and the output of the comparison unit, the control input of which is connected to the output of the first element of And, the first and second information inputs, respectively, with the second outputs of the corresponding subchannels subscribers, the output of the second element And is connected to the sixth input of the exchange register.