SU1100613A1 - Interface - Google Patents

Abstract

A DEVICE FOR COUPLING containing a channel status register, an information register, a device status register, an information input unit, a reception register, a transmission register, N transmission units and N reception units, whose inputs are device connection inputs, and outputs N transmission units — outputs to the communication channels of the device; the outputs of the reception units are connected to the input status register channel group and the information register input group; the input of the input unit is the input connection of the external subscriber of the device, first The first output of the input unit is connected to the first input of the receive register, the first output of which is connected to the first input of the device’s status register and the first inputs of the transmission units, the second inputs of which are connected to the first output of the device’s status register, the first output of the information register is connected to the first input of the register transmission, the output of which is an output to an external subscriber of the device, is different from the fact that, in order to expand the functionality by providing communication of external subscribers with parallel operating and communication channels, an address comparison node, a state byte decoder, a request decoder, a control signal decoder, a trigger register and a comparison unit, the input group of which is connected to the outputs of the N reception units, are entered into the device, the first input is connected to the first output of the status register channels, the second output of the register of the device is connected to the second input of the comparator unit, the output of which is connected to the control inputs of the registers of the channels and information register and to the first input of the trigger register whose second input is connected to the output of the state byte decoder, the third input is connected to the output of the request decoder, the first input of which and the fourth input of the trigger register are connected to the second output of the input block, the five input of the trigger register, the DP second input of the request decoder and the first input the decoder, the control signals are connected to the second output of the channel status register, the sixth and seventh inputs of the trigger register are connected respectively to the outputs of the control signal decoder and the address comparison node, eight th input flip-flop and a first input of a comparison node addresses connected to the second output register information, the output registers of the trigger

Description

pa is connected to the third inputs of the N blocks of the transmitter, the second inputs of the receive register and the device status register, the third input of the information register and the second inputs of the address comparison node and the decoder of control signals, the third input of which and the third decoder input

requests are connected to the third output of the status register of the device, the output of the decoder signal is connected to the second input of the transmission register, the input of the state byte decoder and the third input of the address comparison node are connected to the second output of the receive register.

The invention relates to computing and, in particular, may; used as a system device for connecting subscribers in a multi-machine computing system of increased reliability.

A device for multichannel communication of external devices is known, in which AND external devices (WU through the control unit are connected to the communication line via time-sharing channels. The display unit supplies the control unit with information on channel occupancy. When it arrives from one of the WU request on the serviced control unit, it polls the display unit and allocates a free channel to the device. In the absence of free channels in the VC, nocbingjgfgpfj a corresponding message.

However, such devices cannot be used in a system that provides a link to the VU with parallel I / O channels.

Closest to the proposed. the technical entity is a device for interfacing external devices with input-output channels consisting of one interface unit with external device control devices and interface units with input-output channels. Each communication unit with a channel maintains a channel connected to it via an input / output interface and contains schemes for specifying addresses of the slave unit, switching nodes, sampling response schemes and input / output circuits. The interface unit with control devices contains the schemes for extracting the status byte analysis and decoding the address of the slave address and the sampling circuit of the instruction of the addresses of the slave 2.

A disadvantage of this device is the impossibility of connecting the slaves to naparmericHo operating input / output channels.

The purpose of the invention is to expand the functionality of the device by providing communication between external devices and parallel I / O channels.

The goal is achieved by the fact that the device for coupling, which contains the channel status register, the information register, the device status register, the information input block, the receive register, the transfer register, the N transfer blocks, and the N receive blocks whose inputs are the connection inputs the communication channels of the device, and the outputs of the N transmission blocks are outputs to the communication channels of the device, the outputs of the reception blocks are connected to the group of inputs of the channel status register and the group of inputs of the information register, the input of the input block is a connection input the external device subscriber, the first output of the input unit is connected to the first input of the prim register, the first output of which is connected to the first input of the device state register and the first inputs of the transmission units, the second inputs of which are connected to the first output of the device state register, the first output of the information register connected to the first input of the transfer register, the output of which is the output to the external subscriber of the device, the address comparison node, the decoder is entered

3

status byte, request decoder, control signal decoder trigger register and comparison unit, the input group of which is connected to the outputs of the N reception units, the first input is connected to the first output of the channel state register, the second output of the device state register, the output of which is connected to the control inputs of the channel status registers and the information register and to the first input of the trigger PeRHcfpa, the second input of which is connected to the output of the state byte decoder, the third input from c to The output of the request decoder, the first input of which and the fourth input of the trigger register are connected to the second output of the input block, the fifth input of the trigger register, the second input of the decoder. requests and the first input of the control signal decoder are connected to the second output of the channel status register, the sixth and seventh inputs of the trigger register are connected respectively to the outputs of the control signals decoder and the address comparison node, the eighth input of the trigger register and the first input of the address comparison node are connected to the second output of the information register , the output of the trigger register is connected to the third inputs of the N transmission blocks, the second inputs of the receive register and the device status register, the third input of the info register and the second inputs of the address comparison and control decoder node — whose third input and third request decoder input are connected to the third output of the device status register, the control signal decoder output is connected to the second transfer register input, the state byte decoder input and the third input of the node address comparisons are connected to the second

the output of the reception register. I

The drawing shows the block diagram of the device.

The interface device contains N reception units 1 by the number of connected input / output channels comparison unit 2, channel state register 3, information register 4., device state register 5., control unit 6 containing the address comparison node 7, decoder 8

status byte, decoder 9 requests for service, decoder 10 control signals, trigger register 11, N blocks 12 of transfer 5 by the number of connected input / output channels, input block 13, reception register 14, transfer register .15.

The interface device is connected with N I / O channels via 0 I / O connection circuits 16 and 17, and with I / O via communication circuits 18 and 19.

The operation of the device can be ... connected either with the receipt of a requirement from an external device, or 5 with the receipt of an I / O command by the channels.

When a command is received, the N parallel channels work to reset the sign of their initial state, and form an additional sign to the interface device for which the I / O command is received. Both signs through

5 receive blocks 1 are written to

3 channel state register. If, the pairing device is not currently occupied (i.e., in register 5, the state of the pairing device

0 there is a sign of the initial state), then the signals from the outputs of the registers

3 and 5 are received at the input of the decoder 9 service requests. The request signal from the output of this circuit resets in the trigger register 11

This is the indication of the initial state of the device and is an I / O channel allowing signals to be output through the transmission blocks 12.

0 The trigger register 11 is a series of successively switching triggers, with the installation of each subsequent triggering the reset and being

5 subject to appropriate conditions. The reset indication of the initial state of the device through the transmission blocks 12 is inserted into the channels that fix the reset of the initial state

0 and expose the address of the external device, which enters the device in question via blocks 1 of the receive. Comparison unit 2 provides an enable signal for recording in

5 register 4 information in the event that Coincidence of signals from all parallel channels is detected when there is a signal occupied by each of the S channels and a signal from the register 5 of the device state. The address of the external device is recorded on register 4, and if it is, it is rewritten to transfer register 15. Identification signals and control signals to an external device are generated by the decoder 10 of the control signals, depending on the signals from the output of the register 3, the channels, the register 5 of the state of the interface, and the state of the trigger register 11. The signals of the state of the interface, 5, the channels arrive through the transmission units 12 and prevent the appearance of new calls from outside the I / O operations of the communication channels. The address received from the subscriber is received via input block 13 from an external device and is written to register 14. The addresses of the control unit received and received are compared by node 7 of the comparison of addresses. In the case of incomparable addresses, the signal from the output of node 7 is received. in the trigger register 11. The message enters the channel through the transmission blocks 12, the trigger register 11 at. this is reset, on the device status register 5, the characteristics of the initial state are set. In the course of operation, the signs of the channel status are entered through blocks 1 into the channel status register 3, information1 into the information register 4. Signals about the availability of information on register 4, as well as channel status signals, go to control unit 6. When a response is received from a subscriber, information is recorded through input unit 13 to register 14 and entered into channels through blocks 12. Identification and control signals from the subscriber entering the control unit 6 causes a change in the state of the trigger register 11 and is sent to the subscriber through the register 15 of the transmission of the response signal. The recording in register 5 of the new state signal and the output of these signals to the channel occurs only in that case. 136 when new instructions from the channel are required, associated with the continuation or termination of the exchange operation, as well as when the channel receives an error message or a normal operation. Communication establishment initiated by the interface device takes place when there is a requirement from the VU and at least one channel that is in the initial state during separate operation, and N channels for parallel operation. The request from an external device is received via input unit 13 to control unit 6 (to service requests encoder 9). The output signal from control unit 6 resets the signals of the initial state of the device, and through transfer unit 12, the contents of register 14 are transmitted to channels. The channel in the initial state perceives the reset of the indications of the initial state of the interface device as a subscriber requirement. The interface device only responds to the subscriber after the receiving units 1 are fixed that the channels (channel) have received a service request, i.e. reset the signs of their original state. The signals from the output of the blocks are recorded on the register 3 and fed to the control unit 6 which, depending on the state of the trigger register 11 and the signals received from the communication channels, forms a response to the subscriber from the output of the decoder 10 control signals. The 8-byte decoder of the external device determines the zero value of the status byte and eliminates the extra bridges between the channel and the interface device. The proposed device allows organizing simultaneous operation of external devices with parallel I / O channels, which makes it possible to use it as part of highly reliable computer systems.

Claims (1)

A MAPPING DEVICE comprising a channel status register, an information register, a device status register, an information input unit, a reception register, a transmission register, N transmission units and N reception units, the inputs of which are inputs of connecting the communication channels of the device, and the outputs of N Transmission units are outputs to the device’s communication channels, the outputs of the reception units are connected to the group of inputs of the channel status register and the group of inputs of the information register, the input of the input unit is the input of the connection of the external subscriber of the device, the first output the input unit is connected to the first input of the reception register, the first output of which is connected to the first input of the device status register and the first inputs of the transmission units, the second inputs of which are connected to the first output of the device status register, the first output of the information register is connected to the first input of the transmission register, the output of which is access to the external subscriber of the device, which is connected with the fact that, in order to expand the functionality by providing communication between external subscribers with parallel working channels with ide, an address comparison node, a status byte decoder, a request decoder, a control signal decoder, a trigger register and a comparison unit, the group of inputs of which are connected to the outputs of N reception blocks, are entered into the device, the first, the input is connected to the first output of the channel status register, the second register output device status is connected to the second ¹ input of the comparison unit, the output of which is connected to the control inputs of the channel status registers and the information register and to the first input of the trigger register, the second input of which connected to the output of the status byte decoder, the third input to the request decoder output, the first input of which and the fourth input of the trigger register are connected to the second output of the input unit, the fifth input of the trigger register, the second input of the request decoder and the first input of the decoder, control signals are connected to the second output channel status register, the sixth and seventh inputs of the trigger register are connected respectively to the outputs of the control signal decoder and the address comparison node, the eighth input of the trigger register and the first the input terminal of the address comparison node is connected to the second output of the information register, the output of the trigger register is connected to the third inputs of the N transmission units, the second inputs of the reception register and the device status register, the third input of the information register and the second inputs of the address comparison node and the control signal decoder, third input which and the third input of the request decoder are connected to the third output of the device status register, the output of the control signal decoder is connected to the second input of the transfer register, the decoder input Ator status byte and the third comparison input node addresses connected to the second output, receive register.