SU1156054A1 - Device for writing information on graph plotter - Google Patents

Abstract

DEVICE FOR OUTPUT INFORMATION TO PLAYER, containing a counter, register, first and second digital-to-analog converters, first and second operational amplifiers and a clock generator, the output of the counter through the first, and the output of the second digital-to-analog converters are connected to the inputs of the first and second operational amplifiers, respectively the outputs of which are informational outputs of the device, differing in that, in order to increase the speed of the device, the first and second elements of NAND, reversible counter and comparator, the first input of which is connected to the information input of the register and V-. The information input of the device, the second input is connected to the output of the reversible counter, the first output is the control output of the device, the second and third outputs are respectively connected to the first inputs of the first and second I-NOT element, the second inputs of which are clock the frequencies, and the outputs are connected to the forward and reverse count inputs of the reversible counter, the count input of the counter and the register recording gate input are controlled by the device's input. ate O) about SP 4; ii

Description

The invention relates to automat. tick and computing technology and is designed to display information from an electronic computer (computer) to a plotter. The aim of the invention is to improve the speed of the device by introducing a reference distance between two adjacent values of the read information. Diagram of the device shown in the drawing. The device contains a counter 1, a register 2, first to second digital input logic converters 3 and 4, first and second oggeration amplifiers 5 and 6, plotter 7, comparator 8, first and second elements II 9 and 10, clock frequency generator 11, reversible counter 12. The device operates as follows. In the initial position, counter 1, register 2 and reversing 8th counter 12 are in the zero state. Upon a command to read information received by the pulse input to the device gating entry, the contents of counter 1 increase as it counts the number of selected code values, and at the same time the first eight-bit information code is entered into register 2, and its four most significant bits are sent to the comparator 8 This code compares this code with the previous one, in this case, the zero state stored in the reversing counter 12. At the outputs of the comparator 8, three signals are generated. A 8 A ft and A 8 {where A is the highest bit of the current code, and B is the older four bits of the previous code). In cases, the corresponding match of the output of the comparator 8 will be logical 1. When A B, the signal goes to the AND-HI element 9, respectively, when AB the signal is sent to the AND-HI logic element 10 The second inputs of the AND-HI elements 9 and 10 are applied to the clock frequency s generator 11. The clock frequency is fed to the direct input of the reversible counter 12 through the AND-HI element 9, and the reverse input of the reversing counter 12 through the IS-NE 10 element is fed. 542 The content of the reversible counter 12 increases in the case of А В and decreases in the case A “B until codes A- and B become equal. If the codes are equal, a logical 1 signal is generated at the output A of the comparator 8, and at the outputs A 8 and A "B, a zero state, which is a prohibition for the arrival of a clock frequency. A & amp output Comparator 8 is the sampling pulse of the next code value of the read information. After comparing the two codes, the reversible counter 12 contains the same code as the register 2. When the following value of the code is supplied to register 2, the comparator compares it with the contents of the reverse counter 12, i.e. with the previous code, and depending on which code is larger, the content of the reversing counter 12 increases or decreases as long as the codes match. The digital codes contained in counter 1 and register 2 are fed to digital-to-analog converters 3 and 4, where they are converted into corresponding. Analog signals. Then the signals arrive at the inputs of the operational amplifiers 5 and 6, respectively. With the help of operational amplifiers 5 and 6, the necessary reference scale is set by the axes X and Y. From the output of the amplifiers, analog signals go to inputs X and Y of the photomultiplier 7. This process occurs until the entire signal is read and displayed by the plotter 7. The frequency of the clock generator 11 is determined by the maximum speed of the plotter actuator 7. When comparing the codes the register 2 and the reversible counter 12 in the comparator B use only four high bits 2 - 2, based on the accuracy of the plotter 7. The use of new units and communications distinguishes the invention from the prototype, so how the device speed increases due to the introduction of a distance reference system between two adjacent values of 1 "{with readable information, 3 For example, if the readout of the output signal is a normally distributed Markov process for output to 1156054. 4, a plotter using the proposed device takes 3 times less time than with a prototype device.

1 Counters1 g

impulse, “Record

peeticTf f

f Compas ktor

5 1 onepout

7

OttHilO

// j / 7

f jQ OwattL POST

6

itel

impulse „rofnoB

Claims (1)

A DEVICE FOR DISPLAYING INFORMATION TO A GRAPHIC CONDUCTOR, comprising a counter, register, first and second digital-to-analog converters, first and second operational amplifiers and a clock generator, a counter output through the first, and register output through the second digital-to-analog converters connected to the inputs of the first and second operational amplifiers, respectively, the outputs of which are the information outputs of the device, characterized in that, in order to increase the speed of the device, the first and second elements are introduced into it you are NAND, a reversible counter and a comparator, the first input of which is connected to the information input of the register and yav-. is connected to the information input of the device, the second input is connected to the output of the reversible counter, the first output is the control output of the device, the second and third outputs are respectively connected to the first inputs of the first and second NAND elements, the second inputs of which are connected to the output of the clock generator, and the outputs are connected to the inputs of the direct and reverse counts of the reversible counter, the counting input of the counter and the gating input of the register entry are the control input of the device.