SU1156053A1 - Device for reading information from two-position transducers - Google Patents

Abstract

1. DEVICE FOR INPUT OF INFORMATION FROM DUAL POSITION SENSORS, containing counters of write and shift pulses, the first pulse generator, the first and second elements OR, the reference frequency generator and input channels, each of which contains the first and second shift registers, the address coder, the comparison element and the switch, the output of the reference frequency generator is connected to the first input of the first pulse shaper, the first output of which is connected to the first inputs of the input channel comparison elements, and the second output to the control the input of the first shift register of each channel and the counting input of the shift pulse counter, whose outputs are the first information output of the device, the outputs of the pulse counter are the second information output of the device, information Bxojo, of the first shift register connected to the second input of the comparison element and to the first information input the switch, the second information input of which is connected to the output of the first shift register and the third input of the comparison element, and the address inputs of the switch Connected with the outputs of the address encoder, characterized in that, in order to increase the speed of the device, a frequency divider, a second pulse shaper, a register, a trigger, a polling unit, a group of OR elements are entered into it, and an input spreader and a second shift are entered into each input channel. the register whose information inputs are the information inputs of the device, the information output under (L is key to the information input of the first shift register, the first control input is to the second code of the first pulse generator 5 second control input - to the output of the second pulse generator, the input of which is connected to the output of the frequency divider, whose input is connected to the output of the etaO5 core frequency generator, the output of the second pulse driver is connected to the counter of the write pulse counter, with the OE second input of the first pulse driver , with the output of the installation in the O flip-flop and with the input — the installation in O of the shift pulse counter, the overflow output of which is connected to the first input of the first OR element, the output of which is connected to the third input of the first pulse generator, and the second input - to the first output of the polling unit, the first input of which is connected to the output

Description

the home of the reference frequency generator, the second input is the control input of the device, the second output i. connected to the setup input of 1 flip-flop, the output of which is the first control output of the device, the second output of the polling unit is connected to the first input of the request generator of one input channel, the first outputs and the first inputs of the neighboring kanach request drivers are connected, the second outputs are connected to the corresponding inputs the second OR element, the output of which is connected to the third input of the polling unit, the third output of which is the second control output of the device and connected to the control input of the register, the outputs of which are third data output device, data inputs connected to the outputs of register elements or groups whose inputs are connected to outputs of switches input channels, control inputs of these switches are connected to the third output of the request, the second inputs of which are connected to the outputs of the comparison elements.

2. The device of claim 1, wherein the polling unit comprises first to fourth triggers, first to fifth inverters, first, second, and third AND-NES elements, a combined sync output of the first trigger, the first input of the first element The NAND and the first inverter input, the combined sync input of the second trigger and the first input of the second NAND element, the combined data input of the first trigger, the second input of the second y-NOT element and the input of the second inverter are first, second and third

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the block inputs, respectively, the output of the first trigger, the combined output of the third trigger and the second input of the first NAND element, the output of the third inverter are the first, second and third outputs of the block, respectively, the output of the first NAND element is connected to the input of the third inverter and the first input The third element AND-NOT, the second input of which is the fourth input of the unit and connected to the inputs of the installation in O flip-flops from first to third, the output of the second element AND-NOT through the fourth inverter is connected to the input of the installation in About the fourth the trigger, the output of the second element IS NOT through the fifth inverter is connected to the synchronous input of the fourth trigger, the output of which is connected to the data input of the third trigger, the synchronous input of which is connected to the output of the first inverter, the output of the second inverter is connected to the inputs of the installation of 1 first and second triggers that inverts the output of the second trigger is connected to the data input of the first trigger.

3. The device according to claim 15, is that the query generator contains the fifth trigger, the fourth and fifth elements of the I-KE, the combined first inputs of which, the installation inputs 1 and O of the fifth trigger are from the first the third inputs, the driver, respectively, the output of the fourth element AND-NOT, the combined non-inverting output of the fifth element AND-NOT, the combined output of the seventh element AND-NOT, and the synchronous input of the fifth trigger are the first to third outputs of the driver, respectively, inverting the output n addition trigger subkey n to the second input of the fourth NAND.

one

The invention relates to automation and computing and can be used in automated control and monitoring systems for entering information about the state of two-position sensors.

A device for inputting information from two-position sensors is known, which contains a switch, the high-order decoder of the address register, the low-address decoder of the address register, and the address register. unit is assigned to change and state of sensors, block of storing sensor s, generator of clock signals, three OR elements, switchboard of split group, block of definition of change of state of sensors contains similar logic circuits, the number of which corresponds to the number of groups in the switch, bl storing the state of the sensors contains shift registers, the number of which also corresponds to the number of groups in switch 1. The drawback of the device is the low speed associated with the sequential polling of the logic circuits of the block for determining the change in the state of the sensors, i.e. it depends on the number of monitored sensors. A device for inputting information from two-position sensors is known. It contains a reference frequency generator, a first pulse generator, a second address register, a second decoder, a time sensor, a pulse distributor, AND groups, OR elements, and second, third and fourth elements. channels, each of which has a switch aitc. the memory block of the sensor state, the block for fixing the change in the state of the sensors, the first decoder, the first address register, the first and fifth elements AND 2. The disadvantage of this device is the complexity associated with the large memory size. The closest in technical essence to the invention is a device for inputting information from two-position sensors, comprising counters of write and shift pulses, the first pulse shaper, the first and second OR elements, the reference frequency generator and input channels, each of which contains the first and second shift registers, address coder, reference element and switch h. The disadvantage of this device is low speed. Increasing the number of controlled sensors increases the polling time of their condition. In this device, a situation is possible when a change in the state of the sensor reads out information 534 about it, but by the time it is read it has time to return to its previous state, therefore there is no message in the received data about a change in its state. These data are discarded during further processing, but the device spends time on their output, which also reduces its speed. The aim of the invention is to improve the speed of the device. This goal is achieved in that the device for inputting information from two-position sensors, containing counters of recording and shifting pulses, the first pulse shaper, the first and second elements OR, the reference frequency generator and input channels, each of which contains the first and second shift registers, the address encoder, the comparison element and the switch, the output of the reference frequency generator is connected to the first input of the first pulse shaper, the first output of which is connected to the first inputs of the comparison elements of the input channels yes, and the second output is to the control input of the first shift register of each channel and to the counting input of the shift pulse counter, whose outputs are the first information output of the device, the outputs of the pulse counter are the second information output of the device, the information input of the first shift register is connected to the second the input of the comparison element and the first information input of the switch, the second information input of which is connected to the output of the first shift register and the third input of the comparison element , and the switch's address inputs are connected to the address encoder steps, a frequency divider, a second pulse shaper, a register, a trigger, a polling unit, a group of OR elements are entered, and a shaper and a second shift register whose information inputs are information in each input channel device inputs, information output is connected to the information input of the first shift register, the first control input is connected to the second output of the first pulse shaper, the second control input is connected to the output

The second pulse generator, the input of which is connected to the output of the frequency divider, the input of which is connected to the output of the reference frequency generator, the code of the second pulse generator is connected to the input of the write pulse counter, to the second input of the first pulse forming unit, to the output of the O setting of the trigger and to the installation input to O, a shift pulse counter, the overflow output of which is connected to the first input of the first element OR whose output is connected to the third input of the first pulse shaper, and the second input to the first at the output of the polling unit, the first input of which is connected to the generator output of the reference frequency, the second input is the control input of the device, the second output is connected to the installation input of 1 flip-flop, the output of which is the first control output of the device, the second output of the polling unit is connected to the first input of the request shaper of one input channel, the first outputs and the first inputs of the adjacent channel request drivers are connected, the second outputs are connected to the corresponding inputs of the second OR element, the output of which is connected the third input of the polling unit, the third output of which is the second control output of the device and connected to the control input of the register j; whose outputs are the third information output of the device; the information inputs of the register are connected to the outputs of the OR elements whose inputs are connected to the outputs of the input channel switches , the control inputs of these KON iyTaTopOBs are connected to the third outputs of the query drivers, the second inputs of which are connected to. the outputs of the elements of comparison.

In addition, the polling unit contains the first to the fourth triggers, the first to the fifth inverters, the first, second and third elements AND-NOT, the combined synchronous input of the first trigger, the first input of the first AND-NOT element and the input of the first inverter, the combined synchronous input of the second trigger and the first input of the second IKE element, the combined data input of the first trigger, the second input of the second IS element and the input of the second inverter are the first, second and third inputs of the block, respectively, the output of the first trigger, the combined output of the third trigger and the second input of the first element IS-NOT the output of the third inverter are the first, second and third outputs of the block

accordingly, the output of the first NAND element is connected to the input of the third inverter and to the first input of the third NAND element, the second input of which is the fourth input

block and connected to the inputs of the installation of the first to the third flip-flop, the output of the second element IS NOT through the fourth inverter is connected to the input of the installation of the fourth trigger O, the output of the second element AND-NOT through the fifth inverter is connected to the synchronous input of the fourth trigger, whose output connected to the data input of the third trigger,

the synchronous input of which is connected to the output of the first inverter, the output of the second inverter is connected to the installation inputs 1 of the first and second triggers, the inverting output of the second trigger is connected to the data input of the first trigger.

The request shaper contains the trigger trigger, the fourth and fifth NAND elements, the combined first

whose inputs, the installation inputs to 1 and O of the fifth trigger are the first to the third inputs of the imager, respectively, the output of the fourth AND-NOT element, the combined non-inverting output of the fifth IS-NOT element, the combined output of the seventh AND-NOT element and the synchronous input of the fifth The trigger are the first to the third driver outputs, respectively,

the inverting output of the first trigger is connected to the second input of the fourth NAND element.

FIG. 1 shows a block diagram of the device; in fig. 2 - temporary diagram, explaining the principle of operation of the device; in fig. 3 shows the first pulse shaper J in FIG. 4 - polling unit; Fig, 5 request shaper,

The device contains a generator 1 reference frequency, a divider 2 frequencies, the first driver 3 pulses, the second driver 4 pulse 7

owls, trigger 5, the counter 6 shift shift, block 7 of the survey, the counter 8 records pulse, register 9, the first element OR 10, the second element. OR 11. a group of 12 elements OR and input channels 13, the first and second shift registers 14 and 15, the address cipherto 16, the comparison element 17, the switch 18, the query driver 19. the communication bus of the device 20-48 triggers 49-52, the elements AND -NOT from first to fifth 53-57, inverters from first to fifth 58-62, trigger .63.

A reset and data processor (not shown), having received a ready signal from the second control output, checks for a signal on bus 42. This signal is generated when trigger 5 changes from a zero to one state. If the signal was, then the data acquisition and processing device reads information from the stubs 23, 26, and 40. If the signal was not 5, then the information is read only from the first and third device information outputs (buses 26, 40). The process of reading information, the data acquisition and processing device generates a response signal to the control input of the device (bus 41). From the second information outputs of the device, the sequence number of the write pulse (bus 23) is read, from the first information outputs of the device (bus 26), the sequence number of the shift pulse is read, which corresponds to the number of information input 43 of the device in the canape (clay 43). From the third information outputs of the device (error 40), the channel address is read (the status of the address encoder 16) and the state of the non-compared bits from the first 14 and second 15 channel shift registers. From the first shift register 14, information is received about the state of the sensors at the previous time (at the time of the previous recording pulse), and from the second shift register 15 at the current time. The sequence number of the write pulse in the ring 23 determines the response time of the sensors, since the period of the pulse flow is a constant value and is determined by the divider 2 frequencies. Block 7 survey.

eight

(see FIG. 4) controls information output from the channels.

On the front of the edge of the signal of the total request (bus 32), the polling block 7 5 generates a data signal Vyogod on bus 28, a polling pulse on shi 30, readiness signal on bus 31. Having received a readiness signal from bus 31, the device

 The data collection and processing generates a light signal, which is fed to the polling unit 7 by the pin 41.

If the bus 32 at this moment there is a signal total

15 request, the polling unit 7 again generates a polling pulse to the bus 30 and the readiness signal to iin 31, and the data output signal continues to operate on the bus 28. If a

20 the signal of the total request is absent, the polling block 7 does not generate a polling pulse and a ready signal, but synchronously with the frequency received at its input via the bus 20,

5 removes the signal Output data on the bus 28.

The algorithm of operation of the request shaper 19 (see FIG. 5) will be considered using the shaper 19 request for the first channel as an example. If the request driver 19 placed a request for bus 33, then the 1-hp pulse polling arriving on the bus 30 is commited to bus 47, and the request for miiHe 33 is removed on the falling edge of the polling pulse. If the request driver 19 has not set the request signal, then the pulse the poll is switched to 0 by bus 35, i.e. enters the request circuit of the second channel.

A device for outputting information about the on-off sensors operates as follows. When the power is turned on, the device is conducted along a general reset circuit (the general reset circuit is not shown in Fig. 1). In this case, the divider 2 frequencies, the counter 8 0 of write pulses, the trigger 5 and the first shift register 14 of each channel are set to the zero state. The shift pulse counter 6 is set to a state corresponding to the presence of a signal at its output (bus 27). End of the comparison cycle. The request generator 19 of each channel is set to a state corresponding to the absence of a signal. The request on bus 33 for the first channel, on bus 34 is for the second channel, etc. The polling unit 7 is set to the state corresponding to the absence of the signal of the data output on the bus 28. The second shift register 15 of each channel and the register 9 after switching on the power can be in an arbitrary state. The end of the comparison cycle from the control output of the counter 6 pulses through the first element OR 10 prohibits the first driver 3 pulses from comparing the pulses to the bus 24 and the pulses to the bus 25. The second fork of the transformer produces 4 pulses to the bus 22. A write pulse is written to the e-recording pulse counter 8, the first shaper of 3 pulses is reset, resets the shift pulse counter 6 to O, and the trigger 5 records information about the state of the on-off sensors via bus 43 to the secondary shift register 15 of each channel . The resetting of the first generator of the 3 pulses means that after the arrival of the recording pulse on the bus 22, the comparison pulse to the bus 24 is generated, and not the shift pulse on the bus 25 (see Fig. 2). After resetting in O of the counter 6 shift pulses from the bus 27, the signal of the end of the comparison cycle is removed, and therefore the inhibit signal is removed from the bus 29, and the comparison and shift pulses are allowed to the first driver of the 3 pulses. These pulses are produced by the first driver of the 3 pulses synchronously with the reference frequency received at its input via bus 20 (see Fig. 2). At the end of each write pulse (bus 22) a comparison cycle occurs during which parallel comparison is made in all channels. the contents of the first 14 and second 15 SLIPOVELECH registers on the comparison elements 17, overwriting the contents of the second shift register 15 into the first shift register 14 in terms of 45, outputting the formats to the sensor data collection and processing device, changing their state to the moment of arrival of the recording pulse. Shifting pulses of the output of the driver 3 of the pulses along the bus 25 shift the information synchronously in the first 14 and in the second 15 shift registers of each channel, and in the pauses between the pulses of the h, hectares of comparison are generated to the bus 24. Moreover, if the bits of the same name of the shift registers 14 and 15 are not equivalent, which corresponds to a change in the state of a two-position sensor, then during the operation of the comparison pulse (bus 24), the comparison element 17 produces a signal Uncomparison to the query circuit 19 of the 48. request generator 19 sets up a Request signal (on bus 33 for the first channel, 1 for 34 for the second channel, etc.). The timing diagram (Fig. 2) is given for the case when two channels simultaneously produce a Request signal in one comparison cycle. The buses 33 and 34 receive signals. A request from two channels arrives at the returns of the second element OR 11. At its output, a signal of the total channel request is received, which goes to the polling element 7 via bus 32. On the leading edge of this signal, the interrogation circuit 7 generates the following: a bus 28 produces a data output signal, a polling pulse to the bus 30, and a readiness signal to the bus 31. The data signal B through bus 28 through the first element OR 10 prohibits the first driver 3 pulses to generate comparison pulses to bus 24 and shift pulses to bus 25. Channel request drivers 19 are connected using buses 30, 35, 36, etc. in a sequential chain, the polling pulse passes through this chain and reads information from the channel that is encountered first in this chain with the query signal set. The readiness signal from polling block 7 via bus 31 its front edge records information from bus 39 to register 9 and enters the first control output of the device. The leading edge of this signal is delayed relative to the leading edge of the interrogation pulse (bus 30) for the time required to prepare information at the information inputs of register 9 (bus 39).

The timing diagram (Fig. 2) shows that the polling unit generates two polling pulses in one comparison cycle. The first polling pulse received on bus 30 to the driver, 19 for the first channel, is sent by it on bus 47 to the switch 18 of the first channel and permits the passage through it of information from bus 44, 45 and 46 to bus 37. The rear edge of the first interrogation pulse (bus 30) is removed. The request is output at the output of the first channel request generator 19 (bus 33). The first polling pulse (bus 30) in the comparison cycle sets the trigger 5 to one. The signal from the output of the trigger 5 is supplied via bus 42 to the second control output of the device. The data acquisition and processing device, receiving control signals from the first and second control outputs of the device, reads data from buses 23, 26 and 40 and generates a response signal to bus 41. If there is a signal of the total request on bus 32 (the signal from the second channel) polling unit 7, having received a response signal via bus 41, again generates a polling pulse to bus 30 and a ready signal to bus 315 and data output signal is stored on bus 28. The second polling pulse, arriving on the bus 30 to the first channel request generator 19, flips it to the bus 35, since the request signal at fault 38 from the first channel was removed by the first polling pulse. Through these 35, a second polling pulse arrives at the second channel request generator 19 and commutes with it to bus 47. A bus 47 sends a polling pulse to switch -18 of the second channel and allows information through bus 44, 45 and 46 to pass to bus 38 and further through a group of 12 OR elements and the bus 39 to the register 9. The second polling pulse removes with its falling edge a Request signal at the output of the second channel request generator 19. A ready signal (bus 31), accompanied by a second interrogation pulse, records information

From the second channel through the bus 39 to the registrar 9 and to the second control output of the device. At the first control output of the device, the signal does not appear, since the trigger 5 has not changed its state, therefore, the data collection and processing device will not produce a combination of information from the second information outputs of the device. Receiving a signal from the second control output only, the data acquisition and processing device performs the acquisition of information from the first and third information outputs of the device and generates a response signal to the bus 41. If there is no signal from the bus 32

request, the removal of which occurred after the removal of the signal Request from the second channel, the polling circuit 7 removes the signal Cytod data on the bus 28, while the pulse

polling (bus 30) and a ready signal (bus 31) are not generated.

Removing the signal Outputting data on bus 28 through the first element OR 10 allows the first driver of 3 pulses to again generate comparison and shift pulses on buses 24 and 25, respectively, only now the shift pulse is generated first, since its output was suspended by the occurrence of a data signal on the bus 28

The end of the comparison cycle occurs after the filling of the counter 6

shift shells, which in this case generates a signal on bus 27, the end of the comparison cycle and prohibits the first element OR 10 to the first one

pulses: generate comparing pulses to bus 24 and shear pulses to bus 25. The next comparing cycle will begin after the next recording pulse, and so on.

In comparison with the known technical solutions, the proposed solution allows to increase the speed of the device for extracting information from on-off sensors.

due to the reduction of the time of information output from the channels. The proposed solution eliminates cyclic sequential polling.

13

channels and thereby reduces the time for detecting those sensors that have changed their state. Information is transmitted to the data acquisition and processing device only from those channels in which the sensors have changed their state. In the known control devices of on-off sensors, the transmission of redundant information about the time of the change in the state of the sensors takes place. In the proposed device, the time information is transmitted with the address information only once. This allows to reduce the time of information transfer to the data collection and processing device, as well as to reduce the amount of data.

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56053H

traversable memory capacity in the device for resetting and processing data, since the amount of information about time has decreased significantly.

5 The invention, in comparison with the known solution, excludes the transfer of such information to a data collection and processing device that does not contain information about a change in the state of the sensor, i.e. when the current and previous sensor states are the same.

The application of the invention in automated control systems increases the speed of these systems by 20%, which allows increasing their throughput.

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Claims (3)

1. A DEVICE FOR INPUTING INFORMATION FROM TWO-POINT SENSORS, comprising recording and shift pulse counters, a first pulse shaper, first and second OR elements, a reference frequency generator and input channels, each of which contains first and second shift registers, an address encoder, a comparison element, and the switch, the output of the reference frequency generator is connected to the first input of the first pulse shaper, the first output of which is connected to the first inputs of the input channel comparison elements, and the second output to the control input the first shift register of each channel and to the counting input of the shift pulse counter, the outputs of which are the first information output of the device, the outputs of the Pulse Counter are the second information output of the device, the information input of the first shift register is connected to the second input of the comparison element and to the first information input of the switch, the second information the input of which is connected to the output of the first shift register and the third input of the comparison element, and the address inputs of the switch are connected to outputs of the address encoder, characterized in that, in order to increase the speed of the device, a frequency divider, a second pulse shaper, a register, a trigger, a polling unit, a group of OR elements are introduced into it, and a request shaper and a second shift register are entered into each input channel, information the inputs of which are the information inputs of the device, the information output is connected to the information input of the first shift register, the first control input to the second output of the first pulse shaper, the second the input is to the output of the second pulse shaper, the input of which is connected to the output of the frequency divider, the input of which is connected to the output of the reference frequency generator, the output of the second pulse shaper is connected to the input of the recording pulse counter, to the second input of the first pulse shaper, with the setting output at 0 ” trigger and with input - setting a shift pulse counter at 0 ”, the overflow output of which is connected to the first input of the first OR element, the output of which is connected to the third input of the first pulse shaper, and the second the input is to the first output of the polling unit, the first input of which is connected to the S-U output.> 1156053 reference frequency generator house "the second input is the control input of the device, the second output is <. connected to the installation input in 1 trigger, the output of which is the first control output of the device, the second output of the polling unit is connected to the first input of the request generator of one input channel, the first outputs and the first inputs of the request formers of adjacent channels are connected, the second outputs are connected to the corresponding inputs of the second element OR the output of which is connected to the third input of the polling unit, the third output of which is the second control output of the device and connected to the control input of the register, the outputs of which are They are the third information output of the device, the information inputs of the register are connected to the outputs of the OR elements of the group, the inputs of which are connected to the outputs of the input channel switches, the control inputs of these switches are connected to the third outputs of the query formers, the second inputs of which are connected to the outputs of the comparison elements. 2. The device pop. 1, wherein the polling unit contains first to fourth triggers, first to fifth inverters, first, second and third AND-HE elements, a combined sync input of the first trigger, the first input of the first AND-NOT element and the input of the first inverter , the combined clock input of the second trigger and the first input of the second AND-NOT element, the combined data input of the first trigger, the second input of the second AND-element and the input of the second inverter are the first, second and third inputs of the block, respectively, the output of the first trigger, the combined output is the third about the trigger and the second input of the first AND-NOT element, the output of the third inverter are the first, second and third outputs of the block, respectively, the output of the first AND-NOT element is connected to the input of the third inverter and to the first input of the third AND-NOT element, the second input of which a fourth input unit and connected to the inputs installation 0 "triggers the first to third output of the second aND-NO element through a fourth inverter connected to the input of the installation on the 0 ^th fourth flip-flop, an output of second aND-NO element through Fr Sa fifth inverter coupled to the clock terminal m of the fourth trigger, the output of which is connected to the data input of the third trigger, the sync input of which is connected to the output of the first inverter, the output of the second inverter is connected to the installation inputs of 1 of the first and second triggers, the inverting output of the second trigger is connected to the data input of the first trigger. 3. The device according to Claim. I mean that the query shaper contains the fifth trigger, the fourth and fifth AND-NOT elements, the combined first inputs of which, the installation inputs are 1 '' and 0 of the fifth trigger are the first to third inputs, the shaper, respectively, the output of the fourth AND-NOT element, the combined non-inverting output of the fifth AND-NOT element, the combined output of the seventh AND-NOT element and the sync input of the fifth trigger are the first to third outputs of the former respectively, the inverting output of the fifth trigger is connected to the second input of the fourth element It is the AND-NOT.