SU1123104A1 - Analog-to-digital converter - Google Patents

Abstract

ANALOG-DIGITAL CONVERTER containing the input source, the first controlled voltage switch, the main analog-to-digital converter, the arithmetic unit and the control unit, the first outputs of which are connected respectively to the control inputs of the first controlled voltage switch, the main analog-to-digital converter, an arithmetic unit, the first input of which is connected to the output of the main analog-to-digital converter that distinguishes the Uai, 1123104 3

Description

The invention relates to electrical measuring equipment and can be used in devices for converting measurement information with increased accuracy requirements. An analog-to-digital converter containing a comparator is known, the first input of which is connected to the input bus, and the second input is via a serially connected digital-to-analog converter calculator, the main analog A digital converter is connected to the output of the comparator l. The disadvantage of this converter is the low conversion accuracy. Closest to the invention, the technical entity is an analog-to-digital converter containing an input source, a first controlled voltage polarity switch, a main analog-to-digital converter, an arithmetic unit, and a control unit. The first outputs of which are connected, respectively, with the control inputs of the first controlled voltage switch, the main analog-digital converter, the arithmetic unit, the first input of which is connected to the output of the main analog-digital converter 2. A disadvantage of the known converter is the relatively large discretization error, which is limited by the basic AChB. In the converter, the requirements of high suppression of common mode voltages and noises and the requirement of low bias voltages and input currents are unattainable at the same time. A reduction in the input common-mode voltage in the circuit is possible if the period of the frequency of this voltage is much longer than the conversion time of the ADC. In this case, the input common-mode voltage introduces an error whose sign does not depend on polarity. input voltage Since the absolute values of these errors in the first and second cycles are very close, they are almost completely mutually destroyed. When penetrating the input common-mode voltage, it becomes necessary to reduce the conversion time of the ADC. Reducing this time also contributes to reducing the effect of P1umov input circuits of the main AShch (for example, its input amplifier) on the conversion result. This is due to the transfer of the spectrum of the useful signal to the region of higher frequencies free from the action of low-frequency noise. However, the reduction in the time of | | e formation of the ADC makes it necessary to use high-speed devices, for example, keys on field-effect transistors, for which large values of input currents are characteristic. So, for example, for the switch N590 KN-2, the leakage current Z., t of the open channel reaches 100 nA. To this value, add the recharge current and capacitance capacitances J VC4, i, r, where C is the capacitance value J Y (j is the value controlling the voltage j, the switching frequency. At {10 kHz, pF, TC 10B, .ii, ". “-Z„ „„ iJ (jI μA. These currents, flowed through the intrinsic resistance of the key g, introduce an error V equal to Vk ,, Ucny,) and reach a value of 220 μV for P 200 mm. So as d, 3, iztst on the first and second cycles are introduced by different elements, mutual compensation of errors does not occur. The resulting error Vpjj cm | {Lee A.g) where Y: |, D and VKA V. corresponding to the 1st and 2nd cycles, is equivalent to the error of the ADC offset and can reach the value of V. Such a high error value excludes the possibility of using the specified converter for converting low level signals with high requirements for attenuating the input common-mode voltage and noise. The aim of the invention is to improve the accuracy of the conversion. The goal is achieved in that the analog-to-digital converter containing the input source, the first controlled voltage switch, the main analog-to-digital converter, the arithmetic unit and the control unit, the first outputs of which are connected respectively to the control inputs the first controlled voltage switch, the main analog-digital converter, an arithmetic unit, the first input of which is connected to the output of the main analog-digital signal In the converter, K – 1 controlled voltage switches, N voltage sources, an operation type determinant, and H adders, the first input of each of which is connected to the output of the corresponding voltage source, and the second input of each i -th adder are connected to the output of each "th controlled voltage switch, and the output, except for the first adder, is connected to the input of each" -1 controlled polarity switch, the input of the last of which is connected to the output of the input A signal, the second outputs of the control unit are connected to the control inputs H -1 of the controlled voltage switches of the voltage and N -1 the inputs of the type of operation, the input of which is connected to the control input of the first voltage switch of the controlled polarity, and the output is with the second input of the arithmetic unit, while the output of the first adder is connected to the input of the analog-digital converter. Figure 1 shows a structural electrical converter circuit; Fig. 2 shows the transfer characteristic of the main AShch. The converter contains an input signal source 1, a first controlled voltage switch 2 polarity, a main analog-to-digital converter (ADC) 3, an arithmetic unit 4, a control unit 5, an operation type determinant 6, a voltage source 7 that generates voltage q / -A, where C1 is the scale step, adder 8, controlled voltage switch 9, voltage source TO, generating voltage / 8, adder 11, controlled voltage switch 12, voltage source 13 generating voltage C / 2, where N - number of adders, adder 14. Source 1 is connected to the input of the N-1 th controlled switch 12, which is connected to the first 0A input of the N -th adder 14. The second input of the N -th adder 14 is connected to the M-m source 13. Output The adder 14 is connected to the input N-2 of the controlled voltage switch polarity (not shown). The output of the first controlled switch 9 is connected to the first input of the second adder 11, the second input of which is connected to the second source 10. The output of the second adder 11 is connected to the input of the controlled switch 2, the output of which is connected to the first input of the first adder 8. Second adder 8 connected to the first source 7 (1 voltage. The output of the first adder 8 is connected to the input of the main ADC 3, the output of which is connected to the input of the arithmetic unit 4. The control inputs of the controlled voltage polarity switches ( switches 2,9 and 12) are shown, the main ADC 3 and the communication input with the arithmetic unit 4 are connected to block 5. The inputs of the determinant 6 are connected to the control inputs of the control of the switches 2, 9, 12 and others. The determinant 6 supplies the input controlling the type of operation of the arithmetic unit 4, the first control signal, for example a logical unit, if the number of controlled polarity switches of the voltage in the second state is even, or a second control signal, for example a logical zero, if the number of controlled switches STUDIO polarity voltage, finding schihs in the second state, is odd. At the first signal on the control of the type of operation of the arctic device 4, the code, which is at its input, after the command from the S block is added to the previously accumulated sum. At the second signal at the input of the control of the type of operation of the arithmetic unit 4, the code, which is at its input, after the command from block 5, is subtracted from the previously accumulated sukma. The conversion result of the ADC is formed at the output of the arithmetic unit 4 in accordance with the formula, 1 JL - .l where LI is the result of the i-th conversion of the main ADC 3; H - the number of transformations of the main ADC;

n is the number of controlled voltage switching units that are in the second state when performing the 1st conversion of the main A / D converter 3.

The process of transformation of A1SC depends on exactly what advantages (reduction of the discreteness error, V1UMOV, the effect of the input common-mode voltage) should be implemented. A reduction in the discreteness error 3–2 times while simultaneously weakening the effect of input common-mode voltages and noise is achieved by implementing the sequence given below.

The conversion process consists of one auxiliary clock and N clock cycles. In the auxiliary clock cycle, as instructed by block 5, iol is written to the arithmetic unit 4, and the controlled voltage switches are set to the first state. Each measure consists of three pits. In the first sub-step of the first cycle 1, in the formula (1), at the command from block 5 of the main ADC 3, the voltage at the input of the voltage to the code r is converted. At the output of the arithmetic unit A, with this, a code L,. On the second push, on command from block 5, the first controlled switch 2 switches to the second state f 2, "1 in formula (1), and the main A / D converter 3 converts the input arithmetic unit 4 voltage at its input 4 code 1/2 (On the third pitch of the first clock cycle, the controlled switch 2 is set to the first state by a command from block 5. On the first pact of the second clock cycle by a command from block 5, the first controlled switch 9 changes to the second state. On the second second stroke tact is repeated operations of the first clock cycle. At the output of the arithmetic unit 4, a code of 1/4 appears (L -Lj -Lj + L.), where Lj and Ly are the codes at the output of the main ADC 3 on the second stroke of the second clock. the command from block 5, the first control switch 9 enters the first state. On the first touch,

for example, the Nth, cycle, as commanded by unit 5, the N-1th controlled voltage switch of the voltage (for example, the N -1th controlled switch 12) changes to the second state. On the second cycle, the 4th cycle repeats i -I cycles in an arbitrary (for example, starting from the 1st and ending i cycles) sequence. On the third punch of the cycle, on command from the 5th block, the N-1st control polarity switch switches to the first state. In the process of performing these actions, the code L is generated at the input of the ADC.

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resulting from the conversion of the ADC.

The operation of the ADC is explained for the case. In this case, switches 9 and 12, sources 10 and 13, adders 11 and 14 (Fig. 1) are absent, and the voltage to be converted is fed to control switch 2, and the operation of the ADC is limited by the auxiliary and first cycles.

On the first pitch of the first cycle, the input voltage of the main ADC 3 receives a voltage equal to 1 V to / 4, where V is the value of the voltage being converted, on the second sub-stroke of the first cycle, the input voltage of the main ADC 3 is equal to 7 V 4 a / 4. At the output of the main ADC 3, codes L, and Uj, respectively, appear at this point. The L (L, -l) code appearing at the output of the arithmetic unit 4 is characterized by half the discrete error than the discrete error of the main ADC 3. This follows from consideration of the transfer characteristic of the main ADC 3 (Fig. 2, curve 15). The action of the first voltage source 7 is equivalent to the displacement of the transfer characteristic of the main A1SC 3 by / 4. As V increases from a value equal to zero, the value of L, - b at the output of the arithmetic unit 4, equal to 1, is reached at (/ 4, / 4. A value equal to 2, is reached at. Thus, the code D-4L has a discreteness equal to / 2, i.e., twice as small as the resolution of the main ADC 3. This makes it possible to treat a device containing a switch 2, a converter 3, a device 4, a block 5, a determinant 6, a source 7, an adder 8, as ASC1 with the transfer characteristic (Fig.2 | Curve 16) and the discreteness error is half that of the main one. ADC 3. Adding to the ADC consisting of these elements, the switch 9, the source 10 and the adder 11 reduces the discretization error by another half.

The weakening of alternating common-mode input voltages and noise while maintaining the accuracy characteristic of an accurate and slow action controlled polarity switch of the voltage network is associated with the possibility of using as an adjustable voltage switch of exact and slow-acting element constructed, for example, on reed switches. The controlled switch 2 of the polarity of the voltage in this case must be fast-acting and can introduce a significant bias voltage without compromising the accuracy of the ADC. The order of actions can be simplified if a sufficiently small, for example, fourfold (), decrease in the error of discreteness. In this case, the reduction of the input common-mode voltage and noise is achieved by performing 2-m (M is a positive integer) transformations of the main ADC 3 in the first state of the controlled switch 12 of the polarity of the voltage and 2m transformations of the main A1SCH-3 in the second state element, each odd transformation of 2M transformations corresponds to the first, and each even one - to the second state of the controlled switch 2. The result of the ADC conversion in this case is formed as the sum of 4M codes, corresponding to at the first and second states of the controlled switch of 12 polarity of voltage. 5 The characters of the Li codes, which form, in accordance with (1), the result of the conversion of the A / D converter L, are determined in accordance with the previously stated order of operation of the arithmetic unit 4

0 and determinant of 6 species. The weakening of the effect of variable in-voltage voltages is associated with a decrease in the absolute error increment introduced by the alternating common-mode voltage to

5 in the interval of two tracks, one after the other, for the transformations of the main ADC 3, and with a statistical averaging of these increments. Noise reduction due to their statistical averaging

0 and the transfer of the spectrum of the useful signal in the region of higher frequencies, free from low-frequency noise.

The use of additional elements favorably distinguishes the converter from the prototype, since with the same set of elements due to the use of voltage sources and adders, it is possible to significantly reduce the error of discreteness, errors from the common-mode signal, noise and input currents.

The effect obtained by increasing the accuracy can be quite significant, if, for example, to use a cheap ADC with a small number of bits instead of an expensive multi-bit ADC. The feasibility of applying the proposed ADC increases in

If there is a very accurate, but small-sized main AShch1, made in the form of a complete module, and access to its internal points (for example, to connect additional bits of the ADC) no.

is ..

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Claims (1)

ANALOG-DIGITAL CONVERTER containing an input signal source, a first controlled voltage polarity switch, a main analog-to-digital converter, an arithmetic device and a control unit, the first outputs of which are connected respectively to the control inputs of the first controlled voltage polarity switch, a main analog-to-digital converter, arithmetic device , ^{1 the} first input of which is connected to the output of the main analog-to-digital converter, characterized in that, with integer In order to increase the conversion accuracy, I-1 controlled voltage polarity switches, N voltage sources, an operation type determiner and N adders are introduced into it, the first input of each of which is connected to the output of the corresponding voltage source, and the second input of each "-th adder is connected to the output each i-th controlled voltage polarity switch, and the output, except for the first adder, is connected to the input of each i-1 controlled voltage polarity switch, the input of the last of which is connected to the output source g of the input signal, with the second | the outputs of the control unit are connected to If the control inputs of N-1 controlled If switches of voltage polarity I ™ and N-1 inputs of a determinant of the form one-q radio, the Nth input of which is connected to the control input of the first controlled switch of voltage polarity, and the output to the second the input of the arithmetic device, while the output of the first adder is connected to the input of the analog-to-digital Converter. 1 1123104