JPH0149055B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to improvements in interface circuits used in input/output parts of digital circuits, such as A/D conversion circuits, D/A conversion circuits, and sample/hold circuits. It is related to.

[Prior art]

An example of a conventional interface circuit is A/
The case of a D converter will be explained. FIG. 1 shows a 1-bit A/D converter used in a conventional cascade type A/D converter. Input signal V _IN is input terminal 1
is sampled and held by the sample and hold circuit (hereinafter referred to as S/H circuit) 2, and this held voltage V _H (=V _IN ) and the reference voltage
V _R /2 is compared in comparison circuit 3. V _H ＜V _R /2
At this time, the output V _OD of the comparator circuit 3 becomes low level L, and the switch S1 is closed and S2 is opened, and the operational amplifier 4
Outputs V _OA = 2V _H = 2V _IN from. When V _H > V _H /2, the output V _OD of the comparator circuit 3 becomes a high level H, the switch S1 is opened and the switch S2 is closed, and the operational amplifier 4 outputs V _OA = 2V _H −V _R = 2V _IN −V _R. Output. FIG. 2 illustrates the relationship between the residual output V _OA from the operational amplifier 4 and the input signal V _IN . That is, after comparing the input signal V _IN with the reference voltage V _R /2 and performing 1-bit conversion, the "remainder" from the comparison voltage is output. If multiple stages of 1-bit A/D converters shown in Figure 1 are connected in cascade and the remainder output of the previous stage is used as the input of the latter stage, the combination of 1-bit outputs (comparison outputs) from each stage will be the A/D converter of multiple bits. Configure /D conversion output.

However, in the case of a 1-bit A/D converter as shown in Figure 1, the offsets of the S/H circuit 2, comparator circuit 3, and operational amplifier 4, and the on-resistances of switches S1 and S2 are all dependent on the A/D converter. This is a factor that limits accuracy. For this reason, it has the disadvantage that good performance cannot be obtained unless complex and expensive components are used, and it is difficult to integrate it into an IC.

Another drawback is that as the number of bits of output data increases, the number of constituent elements increases and the configuration becomes complex.

The situation is similar in the case of the successive approximation type, which is the most common A/D conversion method.The sample-and-hold circuit and comparator are required to have small offsets, and the ladder-shaped resistor circuit and As the number of output bits increases, the number of weighted current sources increases, and high precision is required.

Next, a D/A converter will be described as a second example of a conventional interface circuit.

Figure 3 shows a conventional charge redistribution type D/A converter.
It is a principle explanatory diagram showing the principle of a prototype produced by the University of California as an example. Two capacitors C11 and C12 having the same capacity are initially discharged. First, open all switches and start converting from the LSB.
When the LSB state d ₁ =1, the switch S12 is momentarily closed and the capacitor C11 is charged to the reference voltage _VR . When d ₁ =0, switch S13 is closed. Next, momentarily close only switch S11,
Redistribute the charge. At this time, capacitor C1
1, C12 terminal voltage V ₁₁ (1), V ₁₂ (1) is
d ₁ V _R /2. Subsequently, the switch S12 or S13 is momentarily closed depending on the state _d2 of the bit above the LSB. After that, when only the switch S11 is closed to redistribute the charge, the capacitors C11 and C
12 terminal voltages V ₁₁ (2) and V ₁₂ (2) are as follows.

V ₁₁ (2) = V ₁₂ (2) = 1/2 (d ₂ + 1/2d ₁ ) V _R (1)
If the above operation is repeated, after the kth charge redistribution, capacitors C11 and C12
The terminal voltages V ₁₁ (K) and V ₁₂ (K) are V ₁₁ (K)=V ₁₂ (K)= _k 〓 ⁱ⁼¹ 2 ⁱ di/2 ^K-1 V _R (2), and k bits The D/A conversion of is completed.

The D/A converter shown above consists of two capacitors and an analog switch, and is easy to configure.
Although it is suitable for IC implementation, the conversion accuracy is determined by the matching accuracy of the two capacitors. Therefore, high accuracy cannot be expected when integrated into an IC.
Furthermore, when this D/A converter is used as a part of an A/D converter (successive approximation method, etc.), the offset of the comparator affects accuracy, making it unsuitable for high precision.

Also, Journal of the Institute of Electronics and Communication Engineers '81/9, Vo1.J64-
Also in the switched capacitor type A/D converter by Isaka et al., published in No. 9, offset errors of comparators and operational amplifiers are a problem.

As mentioned in the conventional example above, interface circuits often require many high-precision and expensive key components;
The problem was that it was difficult to convert it into an IC.

〔the purpose〕

The present invention has been made to solve the above problems, and aims to realize an interface circuit that uses fewer high-precision parts and can be easily integrated into an IC.

〔overview〕

In order to achieve the above object, the gist of the present invention is to provide two switch groups each consisting of an arbitrary number of switches each having one end connected to an arbitrary potential, and the other end of each switch group consisting of an arbitrary number of switches each having one end connected to an arbitrary potential. an inverting amplifier whose other ends are connected to its input terminal; and an inverting amplifier whose one end is connected to its output terminal and whose other end is connected to said input terminal. and a switch to which the interface circuit is connected.

[Explanation of Examples]

The present invention will be explained below using the drawings.

FIG. 4 is an electrical circuit diagram showing an embodiment of the interface circuit according to the present invention. In the main circuit 30, 31 is a reference voltage terminal to which a reference voltage V _R is applied, S31 is a switch whose one end is connected to this reference voltage terminal 31, 32 is an input terminal to which an input signal V _IN is applied, and S32 is this input terminal. 32 is a switch whose one end is connected to common, S33 is a switch whose one end is connected to common, and C1 is each of the switches S31, S32, and S constituting the first switch group.
33, the other end of which connects to one end of the capacitor, S
34 is a switch whose one end is connected to common, C
2 is this switch S constituting the second switch group.
a capacitor to which the other end of 34 connects to one end thereof; 3;
Reference numeral 3 denotes an inverting amplifier whose other ends of the capacitors C1 and C2 are connected to its input terminal, and an inverter or the like may be used, for example. S35 is a switch to which the output terminal of the inverting amplifier 33 is connected to one end thereof and one end of the capacitor C1 is connected to the other end;
S36 is a switch whose one end is connected to the output terminal of the inverting amplifier 33 and the other end is connected to the input terminal of the inverting amplifier 33, and S37 is a switch to which the output terminal of the inverting amplifier 33 is connected and one end of the capacitor C2. a switch connected to the other end,
34 is an output terminal for sending out the residual output V _O from the inverting amplifier 33 to the outside. Reference numeral 35 inputs an external clock and the comparison output V _C from the inverting amplifier 33 to each of the switches S31 to S37.
This is a control circuit that generates a control signal to control the opening and closing of the

FIG. 5 is an explanatory diagram showing how the interface circuit having the above-mentioned structure is operated as a 1-bit A/D converter. The operation will be explained below based on FIGS. 5(A) to 5(J) showing each operation step.

(A) Initially, only switches S32, S34, and S36 are turned on. Input voltage Va of inverting amplifier 33
is equal to the offset (or threshold voltage) V _T of the inverting amplifier 33, so the capacitor C
The terminal voltages V ₁ and V ₂ of C1 and C2 are as follows (charged), respectively.

V ₁ =V _IN -V _T V ₂ =V _T (B) Next, only switches S33 and S37 are turned on. Since V ₁ becomes -V _T , charge V _IN・C1 is transferred to capacitor C2 and V ₂ =V _T −V _I C1/C2
becomes.

(C) Only switches S32 and S36 are turned on.
Here, the input V _IN is applied to the capacitor C1 again, and V ₁ =V _IN -V _T. Capacitor C2 enters a hold state and holds the value at (B) as it is.

(D) Only switches S34 and S35 are turned on.
Since V ₂ becomes V _T again, the charge transferred in (B) returns to the capacitor C1, and V ₁ =2V _IN -V _T.

(E) Only switch S31 is turned on. At this time, the inverting amplifier A operates as a comparator, and its input voltage Va becomes Va=V _R −V ₁ =V _R −2V _IN +V _T . When Va is larger than the offset voltage V _T , that is, when V _IN < V _R /2, the output V _O (=
V _C ) is L, and in the opposite case, the output V _O (=V _C ) is H, and a 1-bit A/D conversion output is obtained.

When V _IN <V _R /2, execute step (F) below; when V _IN V _R /2, execute steps (G) to (J).

(F) In the case of V _IN <V _R /2, only switch S35 is turned on. The resulting output V _O =V _T +V ₁ =2V _IN
The remainder output is obtained.

(G) In the case of V _IN V _R /2, the process continues until (J), and first only switches S33 and S37 are turned on. Since V ₁ =V _T , the charge 2V _IN C1 of capacitor C1 is transferred to capacitor C2,
V ₂ =V _T −2V _IN C1/C2.

(H) Next, only switches S31 and S37 are turned on. Since V ₁ =V _R −V _T , charge C1V _R is transferred from capacitor C2. As a result, V ₂ =V _T
-(2V _IN -V _R )C1/C2.

(I) Turn on only switches S33 and S36. Capacitor C1 is reset and V ₁ =-V _T .
The capacitor C2 enters a hold state and holds the charge at (H) as it is.

(J) Turn on only switches S34 and S35.
Since V ₂ =V _T , the charge of capacitor C2 -
(2V _IN -V _R )C1 is transferred to capacitor C1. As a result, the output V _O is V _O =V _T +V ₁ =V _T +
2V _IN −V _R −V _T =2V _IN −V _R. That is,
In the case of V _IN V _R /2, a residual output of 2V _IN -V _R is obtained.

In a 1-bit A/D converter with such a configuration, the offset (or threshold voltage) of the inverting amplifier does not in principle affect the accuracy of the output, so
Something as simple as an inverter can be used. It is also possible to obtain the residual output without using any (high precision) resistors. Furthermore, capacitor C1,
In principle, the value of C2 does not affect accuracy and matching is unnecessary. Since this method uses a capacitor, no current flows in a balanced state, so there is no error caused by the on-resistance of the switch. Another advantage is that a single inverting amplifier can serve as both a hold amplifier and a comparator, making the circuit configuration simple and requiring no high-precision components, making it suitable for IC implementation.

Note that by inserting a buffer in front of the capacitor C1 (point P), the charging time from an external circuit connected to the input portion can be shortened (improvement of input impedance).

FIG. 6 is a block diagram showing a second embodiment of the present invention, in which the 1-bit A/D conversion circuit shown in FIG.
This is a D converter. 41 in the figure
is an input terminal to which the input signal V _IN is applied, S41 is a switch whose one end is connected to this input terminal 41, 42 is a sample and hold circuit whose other end is connected to the input terminal of this switch S41, and 30 is this S/ The main circuit of the 1-bit A/D conversion circuit whose input is the output of the H circuit 42 (see Fig. 3), S
42 is a switch to which the residual output V _O from the main circuit 30 is connected at one end and the other end is connected to the input of the S/H circuit 42; 43 is the comparison output V _C from the main circuit 30 and the external clock. is input to output control signals to each switch including S41 and S42 and multiple bit data output D ₀ to _{D o-1} (n
This is a control circuit that generates bits (in the case of bits).

The operation of the A/D converter having such a configuration is as follows. The input signal V _IN is first held in the S/H circuit 42 by turning on the switch S41. The input V _IN is then applied to the main circuit 30 to generate an A/D conversion output of the first bit (MSB) and a remainder output. This residual output is held in the S/H circuit 42 by turning on the switch S42, and the above procedure is repeated for the required number of bits (n) to output data (A/D conversion output) D ₀ to D _o- Get ₁ .
However, from the second bit onward, the step (A) in FIG. 4 is unnecessary (the voltage held in capacitor C1 in the final step of the previous conversion can be used as is), and the value from the S/H circuit 42 is is used only in step (C).

The A/D converter having such a structure has the advantage of not only having the features of the first embodiment but also being able to realize a high-precision, multi-bit A/D converter with a simple structure. Furthermore, the number of bits can be easily expanded by simply increasing the number of repetitions of the procedure.

FIG. 7 is a block diagram showing a third embodiment of the present invention, in which a plurality of 1-bit A/D converters shown in FIG. 4 are connected in series to form a multi-bit A/D converter. be. The input signal V _IN applied to the input terminal 51 is held by the S/H circuit 52 and then input to the main circuit 30 (FIG. 4) of the 1-bit A/D conversion circuit. The remainder output of the main circuit 30 becomes an input to the next stage main circuit 30, and is similarly connected to the number of main circuits 30 corresponding to the required number of bits.
The comparison outputs Vc ₀ to _{V co-1} from each main circuit 30 and an external clock are applied to the control circuit 53.
Control output and data output (A/
D conversion output) D ₀ to _{D o-1} are generated. In this case, in order to prevent the processing step length of each stage from differing depending on the comparison result shown in FIG. 5(E), for _example , if _V
It is necessary to maintain the state of step (F) until timing (J).

The cascade type A/D in Figure 7 is the circulating type A/D in Figure 6.
The configuration is more complex than that, but it has the advantage of allowing a higher sample rate.

FIG. 8 is an explanatory diagram showing the operation of a fourth embodiment of the present invention in which the interface circuit of FIG. 4 is operated as a differential sample-and-hold circuit. Step 8 is obtained by skipping steps (C) to (G) from each operation step of the 1-bit A/D converter in Figure 5.
This corresponds to steps (A) to (E) in the figure. That is, in the final step (E), the differential output V _O of the two inputs V _IN and V _R
= V _IN − V _R can be obtained.

By appropriately combining the above steps,
The calculation of V _O =±mV _IN ±nV _R (m and n are integers) can also be realized. Also, switches S31, S32 and terminal 3
Similarly to 1 and 32, the number of terms in the above equation can be increased arbitrarily by increasing the number of switches and terminals. Also, gain can be obtained by feedback using a resistive voltage divider circuit in the output section.

By providing an S/H circuit at the output of the above-mentioned differential or arithmetic sample/hold circuit, unnecessary output signals at intermediate steps can be shielded from the outside, and only the necessary output from the final step can be output to the outside. can.

FIG. 9 is an electrical circuit diagram showing a fifth embodiment of the interface circuit according to the present invention, which functions as a D/A conversion circuit. 61 in the main circuit 60
is a reference input terminal to which the reference voltage V _R is applied, S61 is a switch whose one end is connected to this reference input terminal 61, C61 is a first capacitor whose other end is connected to this switch S61, and S62 is a first capacitor whose one end is connected to the reference input terminal 61. a switch S connected to the one end of the first capacitor C61 and the other end connected to common;
64 is a switch whose one end is connected to the reference input terminal 61, and C62 is a switch whose one end is connected to the switch 6.
a second capacitor S, the other end of which is connected to the other end of the first capacitor C61;
65 is a switch whose one end is connected to the one end of the second capacitor C62 and the other end is connected to the common, and S63 is a switch whose one end is connected to the first capacitor C
a switch connected to the one end of the capacitor C61 and the other end connected to the one end of the second capacitor C62;
62 connects the capacitors C61 and C to its input terminals.
S68 is a switch whose one end connects to the output terminal of the inverting amplifier 62 and the other end connects to its input terminal, and C63 and C64 have one end connected to a simple inverter such as an inverter. a capacitor S6 connected to the input terminal of the inverting amplifier 62 to constitute voltage holding means;
6 and S67, one end of which is connected to the capacitor C63,
Switches S69 and S70 have one end connected to the other end of the capacitor C63 and C64, respectively, and the other end connected to the output terminal of the inverting amplifier 62. , S71 has one end connected to the output terminal of the inverting amplifier 62, and the other end connected to one end of the capacitor C61 and the feedback input terminal 63.
a switch 64 connected to the inverting amplifier 62;
This is the output terminal of the main circuit to which the output from is applied. Switch S73, capacitor C65, buffer 65
forms a known sample-and-hold circuit that receives the output V _A from the main circuit 60, and S72
is a switch whose one end is connected to the output terminal of the buffer 65 (which may be a simple one such as a source follower) and whose other end is connected to the feedback terminal 63. 66 is an output terminal for sending the output of the buffer 65 to the outside. 67 is an external clock and 2
This is a control circuit that inputs value input data and sends control signals to each of the above switches.

In addition, switches S61, S62, S63, S72
constitutes a first switch group connected to one end of capacitor C61, and switches S64 and S65 constitute a second switch group connected to one end of capacitor C62.

FIG. 10 is an explanatory diagram showing the operation of the D/A converter configured as described above. Each operation step will be explained below based on FIGS. 10(A) to 10(H).

(A) First, when the i-th input data di is 1 and the switches S61, S66, and S68 di are 0, the switches S62, S66, and S68 are turned on to charge the capacitor C61 to V ₆₁ =diV _R −V _T .
When other than LSB (i=1), capacitor C62 receives voltage V ₆₂ =V _O i _-1 − corresponding to the previous conversion result.
V _T is maintained. When LSB (i=1), switch S65 is turned on and V ₆₂ =0V.

(B) Turn on switches S63, S68, and S66 to redistribute charges to capacitors C61 and C62. The capacitor terminal voltage (first voltage) V ₆₁ after redistribution is V ₆₁ = C61diV _R +C62V _O i _-1 /C61+C62 (3) (For LSB, V _O i _-1 in equation (3) =0
).

(C) Switches S62 and S69 are turned ON to transfer the charge held in capacitor C61 in (B) to capacitor C63. The voltage at one end of the capacitor at this time is V _A =V _T −V ₆₁ C61/C63 (4).

(D) Charge diV _R again, this time using capacitor C62.
(Switch S64 or S65 and S
62, S68 is ON).

(E) Turn on switches S63, S67, and S71, and transfer the charge corresponding to the previous conversion result held in capacitor C64 to capacitor C6.
1, transferred to C62, and redistributed together with the charge held in capacitor C62 in (D). Capacitor terminal voltage after redistribution (second voltage)
V ₆₂ is as follows: V ₆₂ = C61V _O i _-1 + C62diV _R /C61+C62 (5) (For LSB, V _O i _-1 = 0 in equation (5)
).

(F) Turn on switches S62 and S68 to reset the charge on capacitor C61. Capacitor C
62 holds the voltage after redistribution (E).

(G) If not MSB, switch S63, S66,
S71 turns ON, and the charge corresponding to the first voltage _V61 held in the capacitor C63 in (C),
Second voltage V ₆₂ held in capacitor C62
When redistribution is performed with _the charge corresponding _to
(C61 ² +C62 ² ) diV _R +2C61C62V _O i _-1 / (C61+C62) ² (6)
becomes.

When it is MSB, switches S72 and S73 are turned on instead of switch S71, and D/A
The voltage corresponding to the conversion output V _O n is the capacitor C
65 and is output as V _O from the output terminal 66 via the buffer 65.

(H) If not MSB, switch S62, S70
turns ON, and the charge corresponding to V _O i held in capacitor C61 at (G) is transferred to capacitor C6.
4 to prepare for the next bit conversion.

When it is MSB, S67 and S68 are turned on.

The above operation is performed from LSB (i = 1) to MSB.
By repeating the process until (i=n: number of bits of input data), it is possible to perform D/A conversion on n-bit input data.

In a D/A converter having such a configuration, the influence of the matching accuracy of the two capacitors on the D/A conversion output accuracy is shown as follows. In equation (6), C61 and C62 are almost equal, so C61=C,
If C62=C+ΔC, then V _O i=diV _R {C ² +(C+ΔC) ² +2V _O i _-1 C(C+ΔC)/
(C+C+ΔC) ² = 1/2 (diV _R +V _O i _-1 )−(V _O i _-1 −diV _R )ΔC ² /2
(4C ² +4CΔC+ΔC ² )(7). The second term in equation (7) indicates the error term, which is the error term (calculation _{omitted )} in the case of the conventional method as _shown in Figure 3. )(8) takes a much smaller value. For example, if the capacitor matching accuracy is 1%, ΔC/C=
Since it is 0.01, the error term ΔC ² /2 according to equation (7)
The value of (4C ² +4CΔC+ΔC ² ) is 0.0012%, and the value of the error term ΔC/2 (2C+ΔC) according to equation (8) is 0.25%.

In this way, in a D/A converter with the above configuration, the effect of the matching accuracy of the two capacitors on the output accuracy is very small.In other words, even if the matching accuracy of the capacitors is not very good, high accuracy can be achieved relatively easily. can be obtained.

Furthermore, since the system uses a capacitor, no current flows in a balanced state, so there is no error caused by the on-resistance of the switch.

Furthermore, since the offset (or threshold voltage) of the inverting amplifier does not affect the accuracy of the output in principle, something as simple as an inverter can be used. Further, since the sample and hold circuit is included in the loop, the buffer 65 may be a simple one such as a source follower. Also, since high-precision parts are not required, it is suitable for IC implementation.

FIGS. 11 and 12 are a partial circuit diagram and a block diagram showing a sixth embodiment of the present invention.
FIG. 11A is a partial circuit diagram showing modifications to be made to the main circuit when this embodiment is used in a cascade type D/A converter, whereas the embodiment in FIG. 9 is a circulation type. It is. That is, 80 is a 1-bit D/A converter constructed by adding switches S81 and S82 to the main circuit 60 of FIG. 9 so that the conversion result of the previous stage is held in the next stage. 81 is a conversion input terminal for inputting the conversion result of the previous stage. Also, a connection like that shown in FIG. 11B works in the same way.

FIG. 12 is a block diagram showing connections in a cascaded configuration. 91 is a reference input terminal to which a reference voltage is applied, ₉₀ is a main circuit obtained by adding the modification shown in FIG. 11 to the above-mentioned FIG. has been added.
Switch S90, capacitor C90, buffer 9
2 constitutes a sample and hold circuit that holds the output V _A from the final stage (the nth stage when the data input is n bits), and 93 constitutes the D/H circuit from the buffer 92.
This is an output terminal that sends the A conversion output V _O to the outside.
94 is a delay circuit that generates a delay corresponding to each of data inputs d ₁ to d _o ; 95 is an external clock and data input d ₁ via the delay circuit 94;
This is a control circuit which inputs .about.d _o and generates control signals for each switch of the main circuit and sample/hold circuit.

When data inputs d ₁ to d _o are applied, each main circuit 90
In response to the control signal from the control circuit 95, the converter sequentially performs conversion corresponding to each bit of the data inputs d ₁ to _{d o} . In other words, the data input d ₁ in the first stage main circuit 90
After applying the conversion output V _A to the next stage, converting the data input d ₂ in the second stage, and repeating this process up to the nth stage, outputs from the output terminal 93 in the above-mentioned circular form. A D/A conversion output similar to that can be obtained.

Although the D/A converter configured as described above has a slightly more complicated configuration, it has the advantage that the sample rate of D/A conversion is approximately n times faster than that of the cyclic type.

FIG. 13 is an electrical circuit diagram showing a seventh embodiment of the interface circuit according to the present invention, which functions as an A/D converter.

In the main circuit 120, 121 is an input signal V _I
Input signal terminals to which S121 and S123 are added
is a switch whose one end is connected to this input signal terminal 121, 122 is a reference voltage terminal to which the reference voltage V _R is applied, and S122 is this reference voltage terminal 122.
S124 is a switch whose one end is connected to common, C121 is a first capacitor to which the other ends of the switches S121 and S122 are connected, and C122 is a capacitor connected to this first capacitor C121. are substantially the same, and the other ends of the switches S123 and S124 are connected to one end of a second capacitor, 123 is an inverting amplifier to which the other ends of the capacitors C121 and C122 are connected to its input terminal, and S125 is this inverting amplifier 123. S126 is a switch to which the output terminal of the inverting amplifier 123 is connected to one end, and the one end of the capacitor C121 is connected to the other end;
124 is an output terminal to which the output of the inverting amplifier 123 is added; 125 is a feedback input terminal to which a feedback signal FB related to the residual output from the output terminal 124 is input; S127 is a switch whose one end is connected to this feedback input terminal 125 and whose other end is connected to the one end of the capacitor C122, and 126 is a circulation input terminal (necessary only when using the circulation type) connected to the one end of the capacitor C121. be.
127 is the comparison output V _C from the main circuit 120 above.
This is a control circuit which inputs an external clock and generates control signals to each of the switches S121 to S127 of the main circuit 120.

Note that the switches S121, S122, and S125 form a first switch group connected to one end of the capacitor C121, and the switches S123, S124,
S127 forms a second switch group connected to one end of capacitor C122.

Figure 14 shows a 1-bit A/D with the above configuration.
FIG. 3 is an operation explanatory diagram for explaining the operation of the converter. The operation will be explained below according to each step of FIGS. 14(A) to 14(D).

(A) First switch S121, S123, S12
With only 6 ON, input voltage V _I is connected to capacitor C.
121 and C122 are held. Inverting amplifier 1
The input terminal of 23 becomes virtual ground, but the potential becomes V _{T due to the offset (or threshold voltage) V T .}

(B) Next, turn ON only switches S124 and S125.
and transfers the charge of capacitor C122 to C121. The voltage between the terminals of capacitor C122 is
Since V _I -V _T becomes -V _T , charge C122V _I moves to capacitor C121. As a result, the voltage U ₂₁ between the terminals of the capacitor C121 becomes (1+C122/C121)V _I -V _T.

(C) When only the switch S122 is turned on, the inverting amplifier 123 operates as a comparator with a threshold value V _T , and its input potential V becomes V=V _R −(1+C122/C121)V _I +V _T . As a result, the input voltage V _I will be compared with C121/C121+C122V _R ≈V _R /2.

When V _I <C121/C121+C122V _R , the comparison output from the inverting amplifier 123 is L.
(corresponds to data output of logic 0), and proceeds to the next step D1.

When V _I C121/C121+C122V _R , the comparative power from the inverting amplifier 123 is H
(corresponds to data output of logic 1) and proceeds to the next step D2.

(D1) Only switch S125 is turned ON, and V _O =V _I (1+C122/C121) ≈2V _I is obtained as the residual output from the inverting amplifier 123.

(D2) Only switches S122 and S127 are turned ON, and the charge of capacitor C121 is transferred to capacitor C122 to obtain a residual output V _O = (1 + C121/C122) V _I - C121/C122 V _R ≈2V _I - V _R.

FIG. 15 shows a characteristic curve diagram showing the input/output characteristics of the above circuit.

In a 1-bit A/D converter with such a configuration, the offset (or threshold voltage) of the inverting amplifier does not in principle affect the accuracy of the output, so
Something as simple as an inverter can be used. Furthermore, since the number of operation steps is relatively small at 4, the conversion speed is also relatively fast. Furthermore, since it is a switched capacitor type, no current flows in the balanced state, so errors due to the on-resistance of the switch do not occur.

If the 1-bit A/D conversion circuit shown in FIG. 13 is combined with a sample-and-hold circuit, a circular multiple-bit A/D converter can be realized in the same manner as shown in FIG. Further, it is also possible to obtain a cascade type multi-bit A/D converter by constructing the same as that shown in FIG.

In addition, in Fig. 13, capacitors C121 and C
By inserting a buffer into the one end of the capacitor C122, the capacitor C121,
The time required to charge the C122 can be significantly reduced.

FIG. 16 is an electrical circuit diagram showing an eighth embodiment of the interface circuit according to the present invention. Main circuit 2
20, 221 is a reference input terminal to which the reference voltage V _R is applied, and S221 is this reference input terminal 2.
C221 is a capacitor whose one end is connected to the other end of this switch S221, and S222 is this capacitor C22.
A switch whose one end is connected to the one end of 1 and the other end is connected to common, and 222 is the common voltage (if it is not LSB in cascade connection, it is the conversion output from the previous stage)
The input terminal to which S223 is added is this input terminal 22
2, C222 is a capacitor to which the other end of switch S223 is connected, S224 is a switch whose one end is connected to the one end of the capacitor C221, and the other end is connected to the one end of the capacitor C222. The switch 223 to be connected has the capacitor C2 at its input terminal.
21 and the other end of C222 are connected to an inverting amplifier, such as a simple inverter, S225
is a switch whose one end is connected to the output terminal of the inverting amplifier 223 and the other end is connected to the input terminal of the inverting amplifier 223; 224 is a conversion output terminal to which the output terminal of the inverting amplifier 223 is connected;
225 is the conversion output from this conversion output terminal 224
A feedback input terminal S226 feeds back and adds a signal FB related to V _A (V _A itself or a signal via a sample-and-hold circuit), and one end of S226 is connected to the feedback input terminal 225 and the other end is connected to the capacitor C.
This is a switch connected to the one end of 222. 2
26 is an external clock and binary input data
This is a control circuit that generates control signals for each switch forming the switch means of the main circuit based on d ₁ to _{d o} .

Note that the switches S221, S222, and S224 form a first switch group connected to one end of the capacitor C221, and the switches S223 and S226 form a second switch group connected to one end of the capacitor C222.

FIG. 17 is an explanatory diagram showing the operation when the D/A conversion circuit having such a configuration performs a D/A conversion operation for one bit. Each operation step will be explained below based on FIGS. 17A to 17C.

(A) Sample input data Turn on the switch S225 to keep the input terminal voltage of the inverting amplifier 223 at the offset (or threshold voltage) V _T of the inverting amplifier 223. The i-th data input di to be converted is 1
When di=0, switch S222 is turned on and capacitor C22 is turned on.
The terminal-to-terminal voltage V ₃₁ of 1 is charged to a constant voltage V ₃₁ =V _R di−V _T . If the input data is LSB (i=
1) turns on the switch S223 and charges the voltage V ₃₂ between the terminals of the capacitor C222 to V ₃₂ =-V _T . If the input data is not LSB (i≠1), switch S223 is open and capacitor C22 holds the previous (circulation type) or previous stage (cascade type) conversion result V ₃₂ =V _O i _-1 −V _T. Become.

(B) Charge redistribution Next, switches S224 and S225 are turned on to redistribute the charges held in the capacitors C221 and C222 in (A). The terminal voltage of the capacitors C221 and C222 after redistribution, that is, the converted voltage V _O i becomes V _O i=C221V _R di+C222V _O i ₋₁ /C221+C222 (9). Since the values of capacitors C221 and C222 are approximately equal, equation (9) becomes V _O i≒1/2 (V _R di + V _O i _-1 (10). Equation (10) is based on the charge redistribution type D /A conversion.In the case of a cyclic type, V ₃₂ =V _O i-V _T at this time is held in the capacitor C222 and used for the next bit conversion.

(C) Conversion output This is the case of cascade type, when switch S226 is
When turned on, the converted voltage V _O i is output as a buffer through the inverting amplifier 223 as an output voltage V _A , and becomes the input V _I of the next stage.

In a 1-bit D/A converter having such a configuration, the offset (or threshold voltage) of the inverting amplifier does not affect the accuracy of the output in principle, so something as simple as an inverter can be used. Furthermore, since the number of operation steps is small, the conversion speed is relatively fast. Also, since it is a switched capacitor type, no current flows in the balanced state, so errors due to the on-resistance of the switch do not occur.

In the case of the 1-bit D/A converter shown in FIG.
As in the case of Fig. 12, multiple bit D/A
The transducers can be configured in a circular or cascade configuration.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize an interface circuit that uses fewer high-precision parts and can be easily integrated into an IC.

[Brief explanation of drawings]

Figure 1 is an electric circuit diagram showing an example of a conventional interface circuit, Figure 2 is a characteristic curve diagram showing the input/output characteristics of the circuit in Figure 1, and Figure 3 is a second example of a conventional interface circuit. 4 is an electric circuit diagram showing an embodiment of the present invention; FIG. 5 is an operation explanatory diagram for explaining the operation of the circuit shown in FIG. 4;
FIG. 6 is a block diagram showing the second embodiment of the invention, FIG. 7 is a block diagram showing the third embodiment of the invention, and FIG. 8 explains the operation of the fourth embodiment of the invention. FIG. 9 is an explanatory diagram of the operation for
FIG. 10 is an operation explanatory diagram for explaining the operation of the circuit in FIG. 9;
12 is a partial circuit diagram showing a sixth embodiment of the present invention, FIG. 12 is a block diagram thereof, FIG. 13 is an electric circuit diagram showing a seventh embodiment of the present invention, and FIG. 15 is a characteristic curve diagram showing the input/output characteristics of the circuit shown in FIG. 13, and FIG. 16 is an electric circuit diagram showing the eighth embodiment of the present invention. , FIG. 17 is an operation explanatory diagram for explaining the operation of the circuit of FIG. 16. S31-S37, S61-S65, S68, S
83, S84, S121~S127, S221~
S226...Switch, C1, C2, C61, C6
2, C121, C122, C221, C222...
Capacitor, 33, 62, 123, 223...inverting amplifier.

Claims (1)

[Claims] 1 A first switch, one end of which is connected to a reference voltage, a first capacitor, the other end of which is connected in relation to one end of the first switch, and a second switch, one end of which is connected to a common. , a second capacitor to which the other end of the second switch is connected to one end; an inverting amplifier to which the other ends of the first and second capacitors are connected to its input terminal; and an inverting amplifier connected to the output of the inverting amplifier. and a third switch that applies a signal related to the output of the inverting amplifier to one end of the second capacitor.