SU1113793A1 - Information input device - Google Patents

Abstract

1. A DEVICE FOR INPUT OF INFORMATION containing a control unit, interface blocks, priority block, memory block and the first multiplexer, the output of which is connected to the information input of the memory block, information inputs to the information outputs of the interface block, characterized in that in order to increase the reliability of the device by eliminating the loss of input information, the write-read signal generator and the second multiplexer are entered into it, the information inputs of the interface blocks are information inputs of the device The inputs of the interface unit, the first input of the write-read signal generator and the first input of the control unit are the installation input of the device, the outputs of the control unit group are connected to the synchronous inputs of the interface blocks whose control outputs are connected to the inputs of the priority unit, the information outputs of which are connected to the inputs of the control unit group, the control output of the priority block is connected to the second input of the control unit, the first output of which is connected to the address input of the first multiplexer , the outputs from the first to the third signal generator are recorded, the second and third outputs of the control unit are connected to the control inputs, the address of the address, the write addresses, the control input and the control input of the memory block, respectively, the outputs of the memory block are connected to information the inputs of the second multiplexer, the address input of which is connected to the second output (P of the control unit and is a gate output of the power supply, the second. The input-signaling input is the sync input of the device readout, its third and fourth inputs are connected to the third and fourth outputs of the control unit, respectively, the fourth output to the third input of the control unit. co vl 2. The device according to claim 1, that is, that each 00 block of the interface contains the first counter, the first shift register and the first trigger, the input setting to the first trigger zero, the installation input of the first counter, the sync input and the output of the first trigger is input to the installation, the synchronous input and control output of the block, respectively, the outputs of the counter are connected to the input of the setting to zero of the first trigger and to the control input of the switch

Description

The first shift register, whose inputs and counting input of the counter are the information input of the block, the outputs of the first shift register are the information outputs of the block.

3. The device according to claim 1, wherein the priority block contains AND elements of the first group, the AND-NEH elements and the OR element whose inputs are block inputs and connected to the first inputs of the NAND element, the speed bar is controlled the output of the unit and connected

with the first input of one of the AND elements of the first group, the second input of which is connected to the output of the NAND element, the second input of which is connected to the output of the OR element, the outputs of other AND elements of the first group are connected to the second inputs of the corresponding AND NAND elements, the outputs of which are connected to the second inputs of the corresponding elements And the first group and are informational outputs of the block,

4. The device according to claim 1, which is based on the fact that the record-match signal shaper contains the first element I, the second

and the third counters, the installation inputs of which are the first input of the block, the first and second inputs of the first And element are the second and third inputs of the block, the outputs of the first And element and the second counter, the bit outputs and the overflow of the third counter are the outputs of the first on the fourth one, respectively, the output of the first element I is connected to the first input of the second counter.

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5. The device according to claim 1, characterized in that the control unit comprises a second shift register, a register of the second element AND, a second group of elements AND, the second and third triggers, a clock generator and an encoder, the first output of the second shift register is connected to the installation input the second trigger and to the synchronization input of the register, the second and third outputs are the third and fifth outputs of the block, respectively; the third output of the second register is connected to the synchronous input of the second trigger and the non-inverting inputs of the elements And the second group s, the inverting inputs of which are connected to the register outputs and the encoder inputs, the output of which is the first output of the block, the outputs of the elements of the second group are the outputs of the block group, the reset inputs of the second and third counters, the second and third triggers, and the second shift register are first the input of the block, the first output of the clock generator is connected to the clock input of the second shift register, the second output is the fourth output of the block, the inverting output of the second trigger is connected to the first input of the second element coagulant And, the second input of which unit is a second input, and an output connected to the data input of the second shift register, the register inputs are inputs of block groups unit in the set input and output of the third flip-flop are the third input and the second output unit respectively.

The invention relates to automation and computer technology and can be used in information-measuring systems for entering information into a holographic device.

A device for entering information containing an input unit is known.

matching, consisting of input converters and response node, output matching unit, consisting of information receivers, two switches, clock generator, distributor, control unit, two accumulators, comparison circuits, zero-code decoder.

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node of formation of time delays, group of elements OR, node of priority l3.

The disadvantage of the device is reduced performance.

The closest to the invention to the technical essence is a device for inputting information, comprising a control unit, interface blocks, a memory block and a first multiplexer, the code of which is connected to the information input of the memory block, and information inputs to information outputs of the interface blocks 21 .

The disadvantage of this device is reduced reliability, since the waiting time is great when polling information channels, which leads to loss of information.

The aim of the invention is to improve the reliability of the device by eliminating the loss of input information.

This goal is achieved by the fact that a device for inputting information containing a control unit and interface blocks, a priority block a memory block and a first multiplexer, the output of which is connected to the information input of the memory block, and information inputs to the information outputs of the interface block, the shaper and the second multiplexer are entered; the information inputs of the interface blocks are the information inputs of the device, the inputs of the interface block installation, the first input of the signal generator, The readout and the first input of the control unit are the installation input of the device, the outputs of the control unit group are connected to the sync inputs of the junction block j whose control outputs are connected to the inputs of the priority block, whose information outputs are connected to the inputs of the control unit group, the control output of the priority block is connected the second input of the control unit, the first output of which is connected to the address input of the first multiplexer, the outputs from the first to the third shaper of the write-connect signal, the second and the third the outputs of the control unit are connected to the control inputs by coupling, the addresses of the interface, the addresses for 137934

records, with the control input and with the memory control input of the memory block, respectively, the memory block outputs are connected to the information input W, the second multiplexer, whose address input is connected to the second output of the control unit and is the gate output of the device, the second input of the signal generator

O write-read is input. synchronization reading device, the third and fourth inputs are connected to the third and fourth outputs of the control unit, respectively,

5 fourth exit - with the third input of the control unit.

Each gate contains the first counter, the first shift register and the first trigger, the zeroing input of the first trigger, the installation input of the first counter, the clock input, and the output of the first trigger are installation input, the clock input, and the control output of the block

5, respectively, the counter outputs are connected to the zeroing input of the first trigger and to the control input of the first shift register, the inputs of which and the counting counter count are information input of the block, the outputs of the first shift register are information outputs of the block.

The priority block contains AND elements of the first group, and NAND elements

5 and the OR element, whose inputs are the inputs of the block and connected to the first inputs of the elements of NAND, the output is the control output of the block and is connected to the first input of one

0 of the AND elements of the first group, the second, swarm input of which is connected to the output of the NAND element, the second input of which is connected to the output of the OR element, the outputs of other elements AND the first group are connected to the second inputs of the corresponding NAND elements, the outputs of which are connected with the second inputs of the corresponding elements And the first group and are information

unit outputs.

The read-write signal shaper contains the first element AND, the second and third counters, the installation inputs of which are the first input of the block, the first and second inputs of the first element AND are the second and third inputs of the output 5

The first element and the second counter, the bit outputs and the overflow output of the third counter are the outputs of the first to fourth block, respectively, the output of the first element I is connected to the first input of the second counter.

The control unit contains the second shift register, the register, the second element And, the second group of elements And, the second and third triggers, clock generator and encoder, the first output of the second shift register is connected to the input of the unit of the second trigger and the input of the synchronization register, the second and the third outputs are the third and fifth outputs of the block, respectively, the third output of the second register is connected to the synchronous input of the second trigger and to non-inverted inputs of elements AND of the second group, the inverting inputs of which are connected The outputs of the register and the inputs of the encoder, the output of which is the first output of the block, the outputs of the elements of the second group are the outputs of the block group, the reset inputs of the second and third counters, the second and third triggers, and the second shift register are the first input of the block, the first the output of the clock pulse is connected to the clock input of the second shift register, the second output is the fourth output of the block, the inverting output of the second trigger is connected to the first input of the second And element, the second input of which is the second input of the block and the output are connected to the information input of the second shift register; the inputs of the register are the inputs of the group of the block, the input of the unit setting and the output of the third trigger are the third input and the second output of the block, respectively.

Diagram of the device shown in the drawing. ,

The device contains an interface unit 1, a priority unit 2, a control unit 3, a driver signal record-match 4, the first reg. Shift register 5, the first counter 6, the first trigger 7, the elements AND-NO 8, the elements AND of the first group 9, the element OR 10, element 11, second shift register 12, second

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trigger 13, register 14, encoder

15, clock generator

16, the third trigger 17, the elements And the second group 18, the memory block 19,

5, the second multiplexer 20, the second and third counters 21 and 22, the first element And 23, the first multiplexer 24, the installation input device 25.

JQ The device works as follows.

An embedding pulse, which is sent to the input 25 of the device, resets the counters 6 and the trigger. 7 of the blocks 1, the trigger 13, the trigger 17 and the register of the 12 block 3, the counters 22 and 21. The input information of the asynchronous streams goes to the inputs of blocks 1 and is stored in the first 2Q register register 5, after filling which, at the output of counter 6, a signal is generated that arrives at the first input of the trigger 7, which generates a ready signal. At the same time, counter 6 permits the arrival of information from the input of the device into the second half of register 5, and the volume of the register is chosen such that the possible waiting time of the information writing queue in block 19 is longer than the total recording time of information from all higher priority blocks 1. The ready signal from the output, trigger 7 enters block 2 at the first inputs

 elements of the NAND group 8 (daisy chain) and to the corresponding inputs of the elements OR 10. In the priority block 2, the signal with the highest priority is selected, and the ready signal received from the input block with a lower number has a higher priority. With the appearance of the readiness signal at the input of the element OR 10, at its output a start signal of the control unit 3 is generated, which is fed to the first input of the element 11. In the initial state, the trigger 13 of the control unit 3 is reset and from its inverse to the second input of the element And 11 receives 1, allowing the passage of the start signal of the control unit, while from the output of the element 11, the start signal enters the information input of the register 12. With the arrival of the next clock pulse arriving at the control input of the register 2,

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at its first output, a pulse is generated that arrives at the first control input of the trigger 13, this triggers the flip-flop and the signal of the logical zero that occurs at its inverse output enters the second input of the And 11 element and blocks the control unit 3. At the same time, the signal From the first output of register 12 it enters the control input of register 14, and the word of the state of the daisy chain present at the information inputs of the register 14 is recorded. The word of the state of the deisy chain from the information outputs of register 14 enters the inputs of the encoder 15 and at the same time on the inverse in; odes of elements And 18 of the second group. The encoder 15 senses the word of the daisy chain and at its output generates a code arriving at the control of the input of the multiplexer 24, which connects the corresponding block 1 to block 19. With the arrival of the next clock pulse, the second record of the information output is generated at the second output of the register 12 the fifth control input of the block 19. In this case, the input information is recorded at the address of the counter 22, arriving at the third control input of the block 19

With the arrival of the next clock pulse, a pulse is formed at the third output of register 12, which arrives at the input of counter 22 and increments it, while the pulse arrives at the inputs of elements AND of group 18, on the inverse inputs of which the word of the daisy chain state is present. Passing through the corresponding element AND of the group 18, the pulse arrives at the second control input of the trigger 7 corresponding to the block, having made it reset. Simultaneously, the pulse from the third output of the register shift arrives at the second control input

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the trigger 13, at the inverse output of which a logical unit appears, which is fed to the second input of the element 11, produces a 5 blocking of the control unit. After filling the first half of the memory block 19, the write address counter is zeroed and at the same time at its second output a signal appears

0 arriving at the input of the trigger 17 of the control unit, carried out his transfer. The signal from the trigger output 17 goes to the fourth control input of block 19, prepares its second half for recording, and writes the first half for reading, while the signal goes to the control input of multiplexer 20, opening the corresponding

0 channel to get information from block 19.

In addition, the same signal on the gate output of the device informs the computer about the read information generated in block 19.

The read pulses are continuously received from the input of the generator 16 to the second input of the element AND 23 of the forming body 4, however, the reading of the filled part of the block 19 is carried out by the pulses received at the second control input of the block 19 from the output of the element 23, when there is a clear signal from computer

at the second input of the element 23. The cell addressing of the block 19, when read, is performed by the counter code 21, which goes to the first control

the input of the block 19. The increment of the counter 21 is performed on the falling edge of the read pulses.

The use of the invention improves the reliability of the device

j since it provides intermediate storage of all input information at block 19, which eliminates the loss of input information, thereby increasing the reliability of the device.

Claims (5)

1. INPUT DEVICE INFORMATION containing a control unit, interface units, priority unit, memory unit and a first multiplexer, the output of which is connected to the information input of the memory unit, information inputs - to the information outputs of the interface unit, characterized in that, in order to increase the reliability of the device by eliminating losses input information, a write-read signal generator and a second multiplexer are introduced into it, the information inputs of the interface blocks are the information inputs of the device, the installation inputs of the blocks with voltages, the first input of the write-read signal generator and the first input of the control unit A are the input of the unit'device, the outputs of the group of the control unit are connected to the sync inputs of the interface units, the control outputs of which are connected to the inputs of the priority unit, the information outputs of which are connected to the inputs of the group of the control unit, the control unit priority output is connected to the second input of the control unit, the first output of which is connected to the address input of the first multiplexer, the first to third outputs are formed STUDIO zapisschityvanie signals, second and third outputs of the control unit are connected to the read control input E, the read addresses, write addresses, with vho-. the control house and with the recording control input of the memory unit, respectively, the outputs of the memory unit are connected to the information inputs of the second multiplexer, the address input of which is connected to the second output of the control unit and is the gate output of the device, second. The input of the write-read signal generator is the synchronization input of the reader of the device, its third and fourth inputs are connected to the third and fourth outputs of the control unit, respectively, and the fourth output is to the third input of the control unit. 2. The device pop. 1, characterized in that each interface unit contains a first counter, a first shift register and a first trigger, the zero input of the first trigger, the first counter installation input, the clock input and the first trigger output are the installation input, clock input and control output of the block, respectively, counter outputs are connected to the zero input of the first trigger and to the control input of the first shift register, the inputs of which and the counter counter input are the information input of the block, the outputs of the first shift register are and formational unit outputs. 3. The device according to p. ^ Characterized in that the priority block contains AND elements of the first group, AND-NOT elements and an OR element, the inputs of which are inputs of the block and connected to the first inputs of AND-NOT elements, the output is the control output of the block and connected with the first input of one of the AND elements of the first group, the second input of which is connected to the output of the AND element, the second input of which is connected to the output of the OR element, the outputs of the other elements of the first group are connected to the second inputs of the corresponding AND elements, the outputs of which are connected to in the second inputs of the corresponding elements And of the first group and are the information outputs of the block ·. 4. The device according to p. ^ Characterized in that the write-read signal generator contains the first element And, the second and third counters, the installation inputs of which are the first input of the block, the first and second inputs of the first element And are the second and third inputs of the block, the outputs of the first of the And element of the second counter, the bit outputs and the overflow output of the third counter are the outputs of the first to fourth block, respectively, the output of the first And element is connected to the first input of the second counter. 5. The device according to p. 1, characterized in that the control unit contains a second register sdvy g, a register, a second element And, a second group of elements And, a second and third triggers, a clock generator and an encoder, the first output of the second shift register is connected to the input setting the second trigger into the unit and to the register synchronization input, the second and third outputs are the third and fifth outputs of the block, respectively, the third output of the second register is connected to the sync input of the second trigger and the non-inverting inputs of the elements of the second group, and the inverting inputs of which are connected to the outputs of the register and the inputs of the encoder, the output of which is the first output of the block, the outputs of the elements And the second group are the outputs of the group of the block, the reset inputs of the second and third counters, the second and third triggers and the second shift register are the first input of the block, the first output the clock generator is connected to the clock input of the second shift register, the second output is the fourth output of the block, the inverting output of the second trigger is connected to the first input of the second element And, the second input of which is the second input of the block, and the output is connected to the information input of the second shift register, the inputs of the register are the inputs of the block group, the unit input and the output of the third trigger are the third input and second output of the block, respectively.