SG11201811269RA - Method of processing wafer having protrusions on the back side - Google Patents

Method of processing wafer having protrusions on the back side

Info

Publication number
SG11201811269RA
SG11201811269RA SG11201811269RA SG11201811269RA SG11201811269RA SG 11201811269R A SG11201811269R A SG 11201811269RA SG 11201811269R A SG11201811269R A SG 11201811269RA SG 11201811269R A SG11201811269R A SG 11201811269RA SG 11201811269R A SG11201811269R A SG 11201811269RA
Authority
SG
Singapore
Prior art keywords
wafer
international
protective film
front surface
pct
Prior art date
Application number
SG11201811269RA
Inventor
Karl Heinz Priewasser
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of SG11201811269RA publication Critical patent/SG11201811269RA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 04 January 2018 (04.01.2018) WIP0 I PCT Hu °million OH oI0IIIIIIII110101001110l IIII111110I110IIIIII (10) International Publication Number WO 2018/002035 A2 (51) International Patent Classification: HO1L 21/78 (2006.01) HO1L 21/683 (2006.01) (21) International Application Number: PCT/EP2017/065825 (22) International Filing Date: 27 June 2017 (27.06.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 1611198.1 28 June 2016 (28.06.2016) GB (72) Inventor; and (71) Applicant: PRIEWASSER, Karl Heinz [AT/DE]; Kili- hofstrasse 30a, 81825 Miinchen (DE). (74) Agent: HOFFMANN EITLE PATENT- UND RECHTSANWALTE PARTMBB, Association 151 et al.; ArabellastraBe 30, 81925 Munich (DE). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — without international search report and to be republished upon receipt of that report (Rule 48.2(g)) (54) Title: METHOD OF PROCESSING WAFER 2 14 6 r ) 25 13 2 18 Fig 4 (57) : The invention relates to a method of processing a wafer (W), having a first side (1) with a device area (2) comprising a plurality of devices, and a second side (6) being opposite to the first side (1), wherein the second side (6) has a plurality of protrusions (14) protruding along a thickness direction of the wafer (W). The method comprises providing a protective film (4), providing a base O sheet (7) having a cushioning layer (13) applied to a front surface (17) thereof, attaching a front surface of the protective film (4) to the O O 013 1-1 an adhesive (9), and attaching a back surface of the protective film (4) opposite to the front surface thereof to the cushioning layer (13). The protrusions (14) protruding along the thickness direction of the wafer (W) are embedded in the cushioning layer (13) and a back second side (6) of the wafer (W), wherein the protective film (4) is adhered to at least a peripheral portion of the second side (6) with surface (18) of the base sheet (7) opposite to the front surface (17) thereof is substantially parallel to the first side (1) of the wafer (W). O The method further comprises processing the first side (1) of the wafer (W). C
SG11201811269RA 2016-06-28 2017-06-27 Method of processing wafer having protrusions on the back side SG11201811269RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1611198.1A GB2551732B (en) 2016-06-28 2016-06-28 Method of processing wafer
PCT/EP2017/065825 WO2018002035A2 (en) 2016-06-28 2017-06-27 Method of processing wafer

Publications (1)

Publication Number Publication Date
SG11201811269RA true SG11201811269RA (en) 2019-01-30

Family

ID=56891701

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201811269RA SG11201811269RA (en) 2016-06-28 2017-06-27 Method of processing wafer having protrusions on the back side

Country Status (8)

Country Link
US (1) US10991612B2 (en)
JP (2) JP6958924B2 (en)
KR (1) KR102311579B1 (en)
CN (1) CN109417049B (en)
DE (1) DE112017003219B4 (en)
GB (1) GB2551732B (en)
SG (1) SG11201811269RA (en)
WO (1) WO2018002035A2 (en)

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DE112017007552T5 (en) 2017-05-18 2020-01-30 Disco Corporation Protective cover for use in processing a wafer, handling system for a wafer, and a combination of a wafer and a protective cover
DE102018200656A1 (en) * 2018-01-16 2019-07-18 Disco Corporation Method for processing a wafer
DE102018202254A1 (en) 2018-02-14 2019-08-14 Disco Corporation Method for processing a wafer
JP7201342B2 (en) * 2018-06-06 2023-01-10 株式会社ディスコ Wafer processing method
JP2020009890A (en) * 2018-07-06 2020-01-16 株式会社ディスコ Wafer processing method
JP2020009891A (en) * 2018-07-06 2020-01-16 株式会社ディスコ Wafer processing method
JP7139048B2 (en) * 2018-07-06 2022-09-20 株式会社ディスコ Wafer processing method
JP7181020B2 (en) * 2018-07-26 2022-11-30 株式会社ディスコ Wafer processing method
DE102018214337A1 (en) 2018-08-24 2020-02-27 Disco Corporation Process for processing a substrate
DE102019211540A1 (en) * 2019-08-01 2021-02-04 Disco Corporation METHOD OF EDITING A SUBSTRATE

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Also Published As

Publication number Publication date
CN109417049A (en) 2019-03-01
GB2551732A (en) 2018-01-03
CN109417049B (en) 2023-09-05
JP2019520708A (en) 2019-07-18
WO2018002035A3 (en) 2018-04-19
KR20190021440A (en) 2019-03-05
DE112017003219T5 (en) 2019-03-21
DE112017003219B4 (en) 2023-06-15
KR102311579B1 (en) 2021-10-08
JP2021177575A (en) 2021-11-11
JP7205810B2 (en) 2023-01-17
US20200273739A1 (en) 2020-08-27
GB2551732B (en) 2020-05-27
GB201611198D0 (en) 2016-08-10
WO2018002035A2 (en) 2018-01-04
US10991612B2 (en) 2021-04-27
JP6958924B2 (en) 2021-11-02

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